cs 61c l31 verilog i (1) garcia, spring 2004 © ucb lecturer psoe dan garcia ddgarcia...

CS 61C L31 Verilog I (1) Garcia, Spring 2004 © UCB

Lecturer PSOE Dan Garcia

www.cs.berkeley.edu/~ddgarcia

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures

Lecture 31 – Verilog II

2004-04-09

Fewer Princeton As! They had been giving

up to 46% of its students As; they has vowed to drop it to 35%. Berkeley EECS has 17% As for lower div & & 23% As

for upper div. “At Cal, an A is an A!”

cnn.com/2004/EDUCATION/04/08/princeton.grade.ap/www.eecs.berkeley.edu/Policies/ugrad.grading.shtml


Review• Verilog allows both structural and behavioral

descriptions, helpful in testing

• Syntax a mixture of C (operators, for, while, if, print) and Ada (begin… end, case…endcase, module …endmodule)

• Some special features only in Hardware Description Languages

• # time delay, initial vs. always

• Verilog easier to deal with when thought of as a hardware modeling tool, not as a prog lang.

• Want to Monitor when ports, registers updated

• Verilog can describe everything from single gate to full computer system; you get to design a simple processor


Corrections/Clarifications from last time• No semicolons after end next to endmodule, nor after endmodule(When in doubt, tutorial beats slides)

begin …end

endmodule

• Timing: Review time, variable update, module invocation, and monitor


Review: Verilog Pedagogic Quandary• Using Verilog subset because full Verilog supports advanced concepts that are not described until >= CS 150, and would be confusing to mention now

• Trying to describe a new language without forcing you to buy a textbook, yet language bigger diff than C vs. Java

• Hence Wawrzynek Verilog tutorial• We’ll go through most of tutorial together

• Do the tutorials, don’t just Read them


Time, variable update, module, & monitor

• The instant before the rising edge of the clock, all outputs and wires have their OLD values. This includes inputs to flip flops. Therefore, if you change the inputs to a flip flop at a particular rising edge, that change will not be reflected at the output until the NEXT rising edge. This is because when the rising edge occurs, the flip flop still sees the old value. So when simulated time changes in Verilog, then ports, registers updated

or #2(Z, X, Y);

Z

X

Y


Example page 6 in Verilog Tutorial//Test bench for 2-input multiplexor.

// Tests all input combinations.module testmux2;reg [2:0] c;wire f;reg expected;mux2 myMux (.select(c[2]), .in0(c[0]), .in1(c[1]), .out(f));initial

beginc = 3'b000; expected=1'b0; ...•Verilog constants syntax N’Bxxx where

N is size of constant in bits B is base: b for binary, h for hex, o for octal xxx are the digits of the constant


Example page 7 in Verilog Tutorial… begin

c = 3'b000; expected=1'b0;repeat(7)begin#10 c = c + 3'b001;if (c[2]) expected=c[1];

else expected=c[0];end

#10 $finish;end

•Verilog if statement, for and while loops like C•repeat (n) loops for n times (restricted for)• forever is an infinite loop

•Can select a bit of variable (c[0] )• $finish ends simulation


Example page 7 in Verilog Tutorial...

endinitial

begin$display("Test of mux2.");$monitor("[select in1 in0]=%b out=%b expected=%b time=%d",c, f, expected,

$time);endendmodule // testmux2

•Verilog “printf” statements •$display to print text on command• $write to print text on command, no new line•$strobe prints only at certain times•$monitor prints when any variable updated


Output for example on page 7 (no delay)Test of mux2.

[select in1 in0]=000 out=0 expected=0 time=0








•Note: c output is 3 bits (000 … 111) because c declared as 3 bit constant


Example page 10 Verilog Tutorial // 4-input multiplexor built from // 3 2-input multiplexors

module mux4 (in0, in1, in2, in3, select, out);input in0,in1,in2,in3;input [1:0] select;output out;wire w0,w1;mux2

m0 (.select(select[0]), .in0(in0), .in1(in1), .out(w0)),m1 (.select(select[0]), .in0(in2), .in1(in3), .out(w1)),m2` (.select(select[1]), .in0(w0), .in1(w1), .out(out));

endmodule // mux4

What are m0, m1, m2?

What is size of ports?


Part of example page 11 Verilog Tutorial ...

case (select) 2'b00: expected = a;2'b01: expected = b;2'b10: expected = c;2'b11: expected = d;

endcase; // case(select)...

•Verilog case statement different from C• Has optional default case when no match to other cases• Case very useful in instruction interpretation; case using opcode, each case an instruction


Rising and Falling Edges and Verilog• Challenge of hardware is when do things change relative to clock?

• Rising clock edge? (“positive edge triggered”)

• Falling clock edge? (“negative edge triggered”)

• When reach a logical level? (“level sensitive”)

• Verilog must support any “clocking methodology”

• Includes events “posedge”, “negedge” to say when clock edge occur, and “wait” statements for level


Example page 12 Verilog Tutorial// Behavioral model of 4-bit Register:// positive edge-triggered,// synchronous active-high reset.module reg4 (CLK,Q,D,RST);input [3:0] D;input CLK, RST;output [3:0] Q;reg [3:0] Q;always @ (posedge CLK)

if (RST) Q = 0; else Q = D;endmodule // reg4• On positive clock edge, either reset,

or load with new value from D• Note: Says 32-bits in tutorial, but its 4-bits


Example page 13 Verilog Tutorial...initialbegin

CLK = 1'b0;forever#5 CLK = ~CLK;

end...• No built in clock in Verilog, so specify one• Clock CLK above alternates forever in 10 ns period: 5 ns at 0, 5 ns at 1, 5 ns at 0, 5 ns at 1, …


Example page 14 Verilog Tutorialmodule add4 (S,A,B);• a combinational logic block that forms the sum (S) of the two 4-bit binary numbers (A and B)

• Tutorial doesn’t define this, left to the reader

• Write the Verilog for this module in a behavioral style now

• Assume this addition takes 4 ns


Example page 14 Verilog Tutorialmodule add4 (S,A,B);input [3:0] A, B;output [3:0] S;reg S;

always @(A or B) #4 S = A + B;

endmodule• a combinational logic block that forms the sum of the two 4-bit binary numbers, taking 4 ns

• Above is behavioral Verilog


Example page 14 Verilog Tutorial//Accumulatormodule acc (CLK,RST,IN,OUT);input CLK,RST;input [3:0] IN;output [3:0] OUT;wire [3:0] W0;add4 myAdd (.S(W0), .A(IN), .B(OUT));reg4 myReg (.CLK(CLK), .Q(OUT), .D(W0), .RST(RST));endmodule // acc• This module uses prior modules, using wire to connect output of adder to input of register


Example page 14 Verilog Tutorialmodule accTest;reg [3:0] IN;reg CLK, RST;wire [3:0] OUT;acc myAcc (.CLK(CLK), .RST(RST), .IN(IN), .OUT(OUT));initial

beginCLK = 1'b0;repeat (20)#5 CLK = ~CLK;

end ...• Clock frequency is __ GHz?


Example page 14 Verilog Tutorial...

initialbegin#0 RST=1'b1; IN=4'b0001;#10 RST=1'b0;

endinitial$monitor("time=%0d: OUT=%1h",

$time, OUT);endmodule // accTest• What does this initial block do?• What is output sequence?• How many lines of output?


Finite State Machines (FSM)

• Tutorial example is bit-serial parity checker

• computes parity of string of bits sequentially, finding the exclusive-or of all the bits

• Parity of "1" means that the string has an odd number of 1's

“Even” stateOUT = 0

IN = 0 “Odd” stateOUT = 1

IN = 0

IN = 1

IN = 1


Example page 16, Verilog Tutorial//Behavioral model of D-type flip-flop:

// positive edge-triggered,// synchronous active-high reset.module DFF (CLK,Q,D,RST);input D;input CLK, RST;output Q;reg Q;always @ (posedge CLK)

if (RST) #1 Q = 0; else #1 Q = D;endmodule // DFF• Loaded on positive edge of clock


Example page 3, Part III Verilog Tutorial//Structural model of serial parity checker.

module parityChecker (OUT, IN, CLK, RST);output OUT;input IN;input CLK, RST;wire currentState, nextState;DFF state (.CLK(CLK), .Q(currentState), .D(nextState), .RST(RST));xor (nextState, IN, currentState);buf (OUT, currentState);

endmodule // parity

Verilog doesn’t like itwhen you feed outputsback internally…


Peer Instruction

A. To test FSMs, you need to test every transition from every state

B. Modules must be updated with explicit calls to them, ala scheme

C. If input not explicitly set, output of CL defaults to ‘0’

ABC1: FFF2: FFT 3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT


In conclusion• Verilog describes hardware in hierarchical fashion, either its structure or its behavior or both

• Time is explicit, unlike C or Java

• Time must be updated for variable change to take effect

•monitor print statement like a debugger; display, write, strobe more normal

• Modules activated simply by updates to variables, not explicit calls as in C or Java


Lecture over…


Example page 3, Part III Verilog Tutorial//Test-bench for parityChecker.

// Set IN=0. Assert RST. Verify OUT=0.// IN=0, RST=1 [OUT=0]

// Keep IN=0. Verify no output change.// IN=0, RST=0 [OUT=0]

// Assert IN. Verify output change.// IN=1 [OUT=1]

// Set IN=0.Verify no output change.// IN=0[OUT=1]

// Assert IN. Verify output change.// IN=1 [OUT=0]

// Keep IN=1. Back to ODD.// IN=1[OUT=1]

// Assert RST. Verify output change.// IN=0, RST=1 [OUT=0]

• Comments give what to expect in test


Example page 3, Part III Verilog Tutorial...

module testParity0;reg IN;wire OUT;reg CLK=0, RST;reg expect;parityChecker myParity (OUT, IN, CLK, RST);always #5 CLK = ~CLK;...• Note initializing CLK in reg declaration• No begin ... end for always since

only 1 statement


Example page 3, Part III Verilog TutorialinitialbeginIN=0; RST=1; expect=0;#10 IN=0; RST=0; expect=0;#10 IN=1; RST=0; expect=1;#10 IN=0; RST=0; expect=1;#10 IN=1; RST=0; expect=0;#10 IN=1; RST=0; expect=1;#10 IN=0; RST=1; expect=0;#10 $finish;

endinitial$monitor($time," IN=%b, RST=%b, expect=%b OUT=%b", IN, RST, expect, OUT);endmodule // testParity0


Example output, p. 4 Part III Verilog Tutorial5 IN=0, RST=1, expect=0 OUT=0

10 IN=0, RST=0, expect=0 OUT=020 IN=1, RST=0, expect=1 OUT=025 IN=1, RST=0, expect=1 OUT=130 IN=0, RST=0, expect=1 OUT=140 IN=1, RST=0, expect=0 OUT=145 IN=1, RST=0, expect=0 OUT=050 IN=1, RST=0, expect=1 OUT=055 IN=1, RST=0, expect=1 OUT=160 IN=0, RST=1, expect=0 OUT=165 IN=0, RST=1, expect=0 OUT=0• Output not well formated; so uses $write,

$strobe line up expected, actual outputs


Example page 3, Part III Verilog Tutorial...

#10 $finish;end

alwaysbegin$write($time," IN=%b, RST=%b, expect=

%b ", IN, RST, expect);#5 $strobe($time," OUT=%b", OUT);#5 ;

endendmodule // testParity2•$write does not force new line, $write and $strobe only prints on

command, not on every update


Example output, p. 7 Part III Verilog Tutorial

0 IN=0, RST=1, expect=0 5 OUT=010 IN=0, RST=0, expect=0 15 OUT=020 IN=1, RST=0, expect=1 25 OUT=130 IN=0, RST=0, expect=1 35 OUT=140 IN=1, RST=0, expect=0 45 OUT=050 IN=1, RST=0, expect=1 55 OUT=160 IN=0, RST=1, expect=0 65 OUT=0•$write does not force new line, $write and $strobe only prints on

command, not on every update


Peer Instruction• Suppose writing a MIPS interpreter in Verilog. Which sequence below is best organization for the interpreter?

I. A repeat loop that fetches instructions

II. A while loop that fetches instructions

III. Increments PC by 4

IV. Decodes instructions using case statement

V. Decodes instr. using chained if statements

VI. Executes each instructionA. I, IV, VI

B. II, III, IV, VI

C. II, V, VI, III

D. IV, VI, III, II

E. V, VI, III, I

F. VI, III, II


Verilog Odds and Ends• Memory is register with second dimension

reg [31:0] memArray [0:255];

• Can assign to group on Left Hand Side{Cout, sum} = A + B + Cin;

• Can connect logical value 0 or 1 to port via supply0 or supply1

• If you need some temporary variables (e.g., for loops), can declare them as integer

• Since variables declared as number of bits, to place a string need to allocate 8 * number of characters

reg [1 : 6*8] Msg; Msg = ”abcdef”;


ROM Module used for MIPS Interpreter 1/2//Behavioral model of Read Only Memory:// 32-bit wide, 256 words deep,// asynchronous read-port,// initialize from file on positive// edge of reset signal, by reading// contents of "text.dat" interpeted// as hex.//

...


ROM Module used for MIPS Interpreter 2/2module ROM (RST,address,readD); input RST; input [31:0] address; output [31:0] readD; reg [31:0] readD; reg [31:0] memArray [0:255]; always @ (posedge RST) $readmemh("text.dat", memArray); always @ (address) readD = memArray[address[9:2]];endmodule // ROM• 32-bit registers, 256 word x 32 bit memory• Loads from file on reset, address => readD


Register File used for MIPS Interpreter 1/4//Behavioral model of register file:// 32-bit wide, 32 words deep,// two asynchronous read-ports,// one synchronous write-port.// Dump register file contents to console// on positive edge of dump signal.//


Register File used for MIPS Interpreter 2/4module regFile (CLK, wEnb, DMP, writeReg, writeD, readReg1, readD1, readReg2, readD2); input CLK, wEnb, DMP; input [4:0] writeReg, readReg1,

readReg2; input [31:0] writeD; output [31:0] readD1, readD2; reg [31:0] readD1, readD2; reg [31:0] array [0:31]; reg dirty1, dirty2; integer i;• 3 5-bit fields to select registers: 1 write register, 2 read register


Register File used for MIPS Interpreter 3/4always @ (posedge CLK) if (wEnb) if (writeReg!=4'h0) begin array[writeReg] = writeD; dirty1=1'b1; dirty2=1'b1; end

always @ (readReg1 or dirty1) begin

readD1 = array[readReg1];dirty1=0;

end


Register File used for MIPS Interpreter 4/4 always @ (readReg2 or dirty2)

beginreadD2 = array[readReg2];dirty2=0;

end always @ (posedge DMP) for (i=0; i<32; i=i+1) $display("r%0d:%h", i, array[i]); initial array[0]=0;endmodule // regFile• Why dirty1, dirty2? Why initial array[0]=0? Why

display if DMP? Why check !=0 write?


Your feedback (162 submissions) 1/2

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cs 61c l31 verilog i (1) garcia, spring 2004 © ucb lecturer psoe dan garcia ddgarcia...

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