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Cree’s SiC Power MOSFET Technology:
Present Status and Future Perspective
Lin Cheng and John W. Palmour
Cree, Inc.
August 14, 2014
9th Annual SiC MOS Workshop, UMD, USA, Aug 14-15, 2014
Distribution authorized to U.S. Government
Agencies for administrative or operational use.
Sponsored in part under Cooperative
Agreements W911NR-10-2-0038 and W911NF-
12-2-0064 and Subcontract # 0145-SC-20579-
0285. Includes Cree confidential information.
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.2
Outline
The last frontier for SiC Power MOSFETs
Breakthrough in SiC MOS Stability & Reliability
Next-Generation SiC Power MOSFETs
Future Perspective
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.3
The Last Frontier for SiC - Cost
Performance √
Reliability √
Cost: by optimal chip design
by improved Fab yield
by robust reliability
Transformerat 20 kHz
Transformerat 100 kHz
SiCSolution
SiC solution is 60%smaller at 20% lowercost than Si solution.
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.4
Long-term Reliability
Extrapolated MTTF of~ 107 hours at VGS = 20V
TDDB of Gate Oxide on 1200 V/80 m
Gen 2 MOSFETs at 150C
Accelerated HTRB Testing at 150C
Extrapolated MTTF of~ 3 x 107 hours at VDS = 800 V
Tested to failure atvery high voltages
Tim
e(H
ou
rs)
Vd Stress (V)
Tim
e(H
ou
rs)
Vg Stress (V)
Tested tofailure atvery high
VGS!
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.5
HTGB at 150C VGS =-10 V Lot 1
Qualification Data for NBTS at 150C: 3 Lots x 75 Parts
C2M (1200 V/80 m) SiC MOSFETs ratedfor Max. VGS of -10 V.
Full automotive qualification running todemonstrate 1,000 hours of VTH stabilityat 150C
New process started shipping intodistribution in April 2014
HTGB at 150C VGS =-10 V Lot 2
HTGB at 150C VGS =-10 V Lot 3
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 200 400 600 800 1000
Vth
Hours
In-Situ Monitored Data
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.6
HTGB at 150C VGS =25 V Lot 1
Qualification Data for PBTS at 150C: 3 Lots x 75 Parts
HTGB at 150C VGS =25 V Lot 2
HTGB at 150C VGS =25 V Lot 3
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 200 400 600 800 1000
Vth
Hours
In-Situ Monitored Data
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 200 400 600 800 1000
Vth
Hours
In-Situ Monitored Data
C2M (1200 V/80 m) SiC MOSFETs ratedfor Max. VGS of +25 V.
Full automotive qualification running todemonstrate 1,000 hours of VTH stabilityat 150C
New process started shipping intodistribution in April 2014
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.7
C2M VTH Stability Under BTS Beyond Datasheet Specs
Extremely stable for 1,000 hours under BTS at elevated temp.
o Accelerated beyond data sheet to see any measurable change
o Average shift under positive bias: DVTH = 0.06 V
o Average shift under negative bias: DVTH = 0.01 V
VGS = -15VT = 150C
Positive Bias (PBTS) Accelerated at 175C Negative Bias (NBTS) Accelerated at -15 V
VGS = +20VT = 175C
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.8
C2M Body Diode Stress @ 110% Rated IDS(DC), 150C
Negligible shifts in MOSFET VTH, VDSON, IR after 1,000 hrs
body diode stress at IDS = 22 A (DC), VGS = -5 V, 150C:
o 20 x C2M0080120D (1200 V/80 m) SiC MOSFEFTs
o Max. VTH of MOSFET < 0.02 V, average VTH ~ 0.002 V.
o Max. VDSON of MOSFET < 0.09 V, average VDSON ~ 0.01 V.
o Max. IDSS of MOSFET < 5 A, average IDSS ~ 2.8 A.
1
1.5
2
2.5
3
3.5
0 200 400 600 800 1000
VT
H(V
)
Time (Hour)
Body-diode stressing condition:
IBDF = 22 A (DC), VG = -5 V, TJ=150C.
VTH measured at ID=1 mA and VD=10 V.
Shift in MOSFET VTH
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 200 400 600 800 1000
VD
SO
N(V
)
Time (Hour)
Body-diode stressingcondition:
IBDF = 22 A (DC), VG = -5 V, TJ=150C.
VDSON measured at ID=20 A and VG=20 V.
Shift in MOSFET VDSON Shift in MOSFET Rev. IDSS
0
10
20
30
40
50
0 200 400 600 800 1000
Re
ve
rse
I DS
S(
A)
Time (Hour)
Body-diode stressing condition:
IBDF = 22 A (DC), VG = -5 V, TJ=150C.
Reverse IDSS measured at VDs=1250 V, VG=0V.
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.9
Avalanche Ruggedness of C2M SiC MOSFETs
Unclamped Inductive Switching (UIS) Testing
1mA@1650V
Further reduction in RON,SP of Cree’s 3rd
Generation SiC Power MOSFETs since last MOS
Workshop in August, 2013
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.11
3rd Generation (Gen-3) SiC MOSFETs
Gen-2 DMOS Gen-3 DMOS
Same high-reliability DMOSFET Structure,
but optimized to dramatically reduce die size.
N+ 4H SiC Substrate
P-Well
N+ N+
Source
Source Contact Metal
Degenerately doped Poly Si Gate
Inter-metal Dielectric
Gate Oxide
Drain Contact Metal
N+ 4H SiC Substrate
P-Well
N+ N+
Source
Source Contact Metal
Degenerately doped Poly Si Gate
Inter-metal Dielectric
Gate Oxide
Drain Contact Metal
Optimized doping
Smaller pitch
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.12
0
1
2
3
4
5
0 400 800 1200 1600
I D(
A)a
tV
G=
0V
BVDS (V)
Adie = 6.82 mm2 (2.35 x 2.9)
Active area: 3.41 mm2
1620 V @ 4.67 A
at VG = 0 V
1200 V/80 m, Gen-3 MOSFETs: 2.7 m.cm2 in R&D, 2014
At VG = 20 V, ID = 15 A:
RON,SP (25C) = 2.7 mcm2
RON,SP (150C) = 4.9 mcm2
0
5
10
15
20
25
30
35
40
0 1 2 3 4 5 6 7
I D(A
)
VD (V)
VG = 0 V ~ 20 V
Increment = 5 V
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.13
Negligible BTS VTH shifts for Gen-3 MOSFET at 175C
Excellent VTH stability is demonstrated repeatedly at 175C
Same excellent gate yield and repeatability as Gen-2 MOSFET in
volume production
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 100 200 300 400 500 600
VT
(V)
Time (hr)
In-Situ Monitored Data
NBTS at 175C, VGS = -10V PBTS at 175C, VGS =+20V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 100 200 300 400 500 600
VT
(V)
Time (hr)
In-Situ Monitored Data
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.14
Gen-3 MTTF Lifetime Higher Than Gen-2 MOSFETs
• Gen 2 Extrapolated MTTF of 3E7 hours at VDS = 800 V and 150C
• Gen 3 lifetimes are higher than Gen 2 at 175C
Tim
e(H
ou
rs)
MTTF Prediction from Accelerated Field Testing
Gen 2 Tested tofailure (50%) at
150C
Gen 3 with only
10% failures at
175C
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.15
1
10
100
100 1,000 10,000
RO
N,S
P(m
c
m2)atV
G=
20
V
Breakdown Voltage (V)
Gen 3, 3.3 kV
Gen 3, 10 kV
Gen 3, 15 kV
Gen 3, 6.5 kV
Gen 3, 900 V
Gen 2, C2MFamily 1.2 kV
Gen 1, 1.2 kV
Gen 3, 1.2 kV
Scaling of State-of-Art Gen-3 SiC Power MOSFETs in R&D
RCh/RON becomes larger
for lower-V MOSFETs.
For Gen-3 1200V MOSFET,
RCh > 40% of total RON.
Future Prospective
Reduce RCh/RON by:
o Improving MOS INV
o Higher packing density
High-mobility 4H-SiC (0001) MOSFETs with
Chemically Modified MOS-Interface
9th Annual SiC MOS Workshop, UMD, USA, Aug 14-15, 2014
Daniel J. Lichtenwalner, Lin Cheng, & John W. Palmour
Jointly funded by Cree IR&D and Army HEPS Programs
Cree, Inc.
August 14, 2014
Distribution authorized to U.S. Government
Agencies for administrative or operational use.
Sponsored in part under Cooperative
Agreements W911NR-10-2-0038 and W911NF-
12-2-0064 and Subcontract # 0145-SC-20579-
0285. Includes Cree confidential information.
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.17
OUTLINE
1. Motivation
1. Channel resistance
2. MOS interface passivation
2. Experimental: interface modification
1. Device Fabrication
2. Measurements
3. MOSFET channel properties (All data reserved to be published later)
1. Field-Effect Mobility
2. MOS Interface charge
4. MOSFET gate oxide properties (All data reserved to be published later)
1. Material characterization
2. Electrical properties
5. Summary
D. J. Lichtenwalner, L. Cheng, J. Palmour
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.18
1.1 MOSFET channel resistance
• Graph shows resistance limits dueto drift layer.
• For low voltage devices, channelresistance becomes a large % oftotal device resistance.
Ways to lower Rchan:
• Increase channel packing density
• improve channel mobility 1E-06
1E-04
1E-02
1E+00
1E+02
1E+02 1E+03 1E+04
On
Re
sist
ance
(Oh
m-c
m2)
Breakdown Voltage (V)
Resistance limit
Si
SiCpresently
w/ IncreasedCh. Mobility
e.g., 1700VBD: Rch ~25% of Ron
600VBD: Rch ~40% of Ron
D. J. Lichtenwalner, L. Cheng, J. Palmour
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.19
NO, N2O anneal:
• **FE Mobility ~35 cm2/V.s (Si-face)
~85 cm2/V.s (A-face)
• *Interface N ~5×1014 cm-2 (Si-face)
N ~9×1014 cm-2 (A-face)
• ~ideal SiO2 oxide quality
*,**G. Lui et al., EDL 34 (2013).
**Lichtenwalner et al., MRS spring meeting (2013, 2014).
Phosphorous processing:
• *FE Mobility ~85 cm2/V.s (Si-face)
~125 cm2/V.s (A-face)
• *Interface P ~1.8×1014 cm-2 (Si-face)
P ~1.6×1014 cm-2 (A-face)
• ~Poor oxide quality/stability; Phostypically throughout oxide
1.2 MOS interface passivation (Group V)
Data: Yi Xu et al., ARL workshop Aug. 22, 2013.
S. Kotake et al., Mat. Sci. Forum 679-680 (2011).
D. J. Lichtenwalner, L. Cheng, J. Palmour
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.20
Sodium effects:
• *FE Mobility to 220 cm2/V.s (Si-face)
• **Interface Na ~1×1014 cm-2 (Si-face)
• Device m, VT unstable, mobileions
* B. Tuttle et al., JAP 109 (2011).
** F. Allerstam et al., JAP 101 (2007).
Hydrogen anneals:
• *FE Mobility ~5 cm2/V.s (Si-face)
to 200 cm2/V.s (A-face)
• **Interface H ~6×1013 cm-2 (A-face)
• Hydrogen doesn’t benefit Si-face;weakly bonded, MOS instability
* H. Yano et al., APL 78 (2001).
** T. Endo et al., Mat. Sci. Forum 600-603 (2009).
1.2 MOS interface passivation (Group I)
F. Allerstam et al., JAP 101 (2007).
T. Endo et al., Mat. Sci. Forum 600-603 (2009).
D. J. Lichtenwalner, L. Cheng, J. Palmour
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.21
The Ideal Passivation:
• Interface concentrations >1×1013
cm-2 needed to passivate thermaloxide/SiC NIT states.
• All concentrated at interface.
• Strongly bonded, stable interface.
Our Approach:
• Investigate effects of Group I &Group II elements.
• Utilize deposited SiO2 as the gateoxide.
Project initiated by A. Agarwal, J. Palmour atCree and initially funded by Cree IR&D in 2010.
U.S. Patent applications: 20120326163 Dec 2012
20120329216 Dec 2012
20130034941 Feb 2013
1.2 MOS interface passivation: approach
D. J. Lichtenwalner, L. Cheng, J. Palmour
9th Annual SiC MOS Workshop, UMD, USA, August 14-15, 2014L. Cheng and J. Palmour
Copyright © 2014, Cree, Inc.22
Lateral MOSFET Fabrication:
• Al+ doped p-type SiC (0001)channel
• Deposited passivation layer
• Deposited SiO2 gate oxide
• Poly-Si gate
Measurements: Lateral MOSFET:
• ID-VD
• ID-Vg vs Temp
(VT, F.E. mobility)
• Quasi-static gate C-V
(Tox, Vfb, VT, Qf)
• Gate Ig-Vg
(CB, VB F-N barrier height, EBD)
(All data reserved to be published later)
2. Experimental: Si-face SiC lateral MOSFETs
P-epi SiC
N+ N+
Gate
SiO2
IL
DS
D. J. Lichtenwalner, L. Cheng, J. Palmour
Thank you!
Question?