cpe/ee 427, cpe 527, vlsi design i: laboratory assignment …milenka/cpe527-05f/labs/lab3.pdf ·...

CPE/EE 427, CPE 527, VLSI Design I: Laboratory Assignment #3

Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville

Adapted in part from University of Utah, Dept. of Electrical Engineering Author: Allen Tanner

1. INTRODUCTION In this lab exercise you will use Cadence’s schematic capture tool to create a ripple-carry accumulator circuit. To accomplish this, you will first build the Full Adder circuit (adding two 1-bit signals). Next, you will build a symbol to contain your circuit, which will be the building block that higher bit adders can be constructed from. Thus, using this Full Adder symbol, you will build a 2-bit accumulator circuit. Next, you will perform a functional test of this circuit using Cadence’s Verilog Simulation tool (which interacts with SimVision). In order to perform the verilog simulation, you will create a verilog stimulus file that will be used to test your circuit. Finally, you will construct an 8-bit accumulator circuit on your own, and then functionally test it for accuracy.

You will base your design on the TSMC 0.25um 5-metal 2.5V/3.3V process (lambda = 0.15um).

2. CADENCE STARTUP From your home directory, change directories into your cadence working directory:

% cd cadence

Make a directory for lab3 and change into that directory:

% mkdir lab3

% cd lab3

Start the cadence tool:

% uah-cadence-setup

% icfb&

3. CREATE LIBRARY In the Library Manager window, create a library to contain your lab3 work (call it anything you want), and attach the TSMC 0.30u CMOS025 (5M, HV FET) technology process to that new library.

4. CREATE RC ADDER CIRCUIT/SYMBOL As was done in lab 2, add a new cell to your new library to contain the schematic of the Full Adder circuit and build it as shown in Figure 1. Note that this will be different from lab 2 in that you will not be building your circuit from the transistor level, but you will be instantiating gates

VLSI Design I, Lab 3

of 14

from a pre-existing library that contains basic circuit building blocks. Use the OSU_tsmc025 library for this purpose.

Figure 1. Full Adder Circuit.

Create the symbol for the Full Adder as shown in Figure 2. (Note that when you create the new cell in your library for the symbol, make sure that the name is the same as that used for the schematic cell. This will ensure that the circuit and symbol are “linked”.) In this lab, you will create a symbol from “scratch”, as opposed to importing the symbol as was done in lab 2. The process of creating a custom symbol is done as follows:

• Go to Add->Shape->Rectangle to create the body of your symbol. • Go to Add-> Pin to add the pins for your symbol, noting the direction for each pin

you place (They should match the assignments of the pins that were made in the schematic!). The rotate button also comes in handy here, so keep the pin creation interface window available.

• Go to Add->Label, and place the [@instanceName] label, which will serve as a placeholder for the reference designator. Repeat this once more, but change the


of 14

label type to nomalLabel, type in the name of your symbol (i.e., RCAdder), and place this on your symbol.

• Go to Add->Selection Box and hit Automatic. • Finally, go to Design->Check and Save and make sure there are no errors that

occur in the CIW window. • You can close the symbol editor window.

Figure 2. Full Adder Symbol.

5. CREATE 2-BIT ACCUMULATOR Using your Full Adder symbol as a building block, you will create the 2-bit accumulator circuit as shown in Figure 3.


of 14

Figure 3. 2-bit Accumulator.

You will find the udp_dff symbol in the OSU_tsmc025 library. The wide nets are buses, and they must be created with care, as follows (in the following order!):

1. Note the following terminology: wire equals a single bit; bus equals many bits, and can thus have several wires connected to it.

2. Extend single-bit wires from your symbol (you will have to double-click the “floating end”) that you want to group into a bus.

3. Label the wires according to how you want them grouped in the bus (i.e., Sum<1>, Sum<0>, etc). This will go ahead and assign net names to your wires.

4. Create a pin for your bus that will be named as you want the bus to be named (i.e., Sum<1:0>).

5. Position the pin so that it will be aligned with the ends of the wires that were created in #2.

6. Add a bus (type capital ‘W’ on your keyboard), first clicking on the pin, and then clicking on each wire that you want included in your bus. Clicking first on the pin will give the bus the same name as that of the pin.


of 14

Take note of the function of the accumulator, and that the outputs from the D flip-flops are “connected” back to the input by giving the ‘B’ input the same name as the output. (Naming a wire by the same name causes the netlist to join these two wires electrically.)

6. FUNCTIONAL SIMULATION Now that you have created your circuit, you will perform a functional simulation on it. This process will be explained in detail, as this is introducing a new tool.

1. To start VerilogXL simulation, open up the schematic to simulate and in the schematic editing window (i.e., from your 2-bit accumulator circuit), select Tools → Simulation → Verilog-XL. The Setup Environment window appears, as shown in Figure 4, with all the fields filled. The run directory can be changed or left as default (it is very important to have a separate run directory for each design). Press OK.

Figure 4. Setup Environment Window.

2. A window titled Virtuoso Schematic Composer Analysis Environment for Verilog-XL Integration appears, as shown in Figure 5. This is the window from which the simulation can be invoked.


of 14

Figure 5. Verilog-XL Simulation Window.

3. But before starting simulation the environment needs to be setup and an input stimulus file for the circuit (which in terms of Verilog is called test fixture) needs to be created. The test fixture is the command file written in Verilog that drives the simulation.

4. Select Setup → Record Signals…. In the Record Signal Options window, which appears as shown in Figure 6, change the save list to All Signals (to record all signals) or Top Level Primary I/O and press OK. Note: To make changes to the Record Signal Options later on, make sure that the interactive simulation is stopped. If it is not stopped then select Simulation → Finish Interactive.

Figure 6. Record Signals Options.

5. Next select Stimulus → Verilog… and a prompt window appears asking if you wish to create a template. Press Yes. Note: All the process of setting up the test fixture file must be done before starting Interactive Simulation. If interactive simulation is already started, select Simulation → Finish Interactive.

6. In the Stimulus Options window, which appears as shown in Figure 7, select copy. In the Copy From: frame, select the File Name from the list as testfixture.verilog. The File Name in the Copy To: frame can be changed or left as default. Press Apply.


of 14

Figure 7. Stimulus Options.

7. Next select Edit mode and choose testfixture.new (or the file name you have given to the test fixture) from the Field Name. Select Make Current Test Fixture and Check Verilog Syntax and Press Apply.

8. The default editor (most likely textedit) will open up. Type in the text fixture as shown in Figure 8. Then save the test fixture and close the editor. Any syntax errors present will be indicated. Please fix the errors before going to the next step. Note what’s going on with this test fixture. First it defines some temporary variables for use by the test fixture. Then it defines the names and sizes of the signals that the test fixture will drive and sense from your circuit. Then it generates input values to send to the circuit. Note that the “#” statement in the Verilog test fixture is the equivalent of elapsing the listed amount of time in the simulation, and the “~” operation inverts the existing binary value of the given variable.


of 14

Figure 8. Verilog stimulus file.

9. Now in the Stimulus Options window select the Select mode. In this mode, select File Name field as testfixture.new (if its not already selected) and press OK.

10. Start the Verilog simulation by selecting Simulation → Start Interactive. This netlists your design, checks the netlist for errors, and compiles the netlist and test fixture for simulation. The Verilog Schematic Composer Analysis Environment for Verilog-XL Integration window will change as shown in Figure 9.


of 14

Figure 9. Verilog window after netlisting.

11. Run the simulation by choosing Simulation → Continue.

12. Waveforms can be viewed in SimVision by selecting Debug → Utilities → View Waveform…. The Waveform 1 - SimVision window appears as shown in Figure 10.

Figure 10. SimVision Waveform Window.


of 14

13. Now select Windows → New Design Browser and the Design Browser 1 – SimVision window appears as shown in Figure 11.

Figure 11. Design Browser Window.

14. In the Scope Tree list select test. The different input and output signals to be viewed can now be selected from the Signals/Variables of scope list. Use the shift or control key to select multiple signals. Now, right click on the selected signals and in the menu that appears, select Send to target Waveform Window.

15. This will now plot the variables in the Waveform 1 – SimVision window. Select View → Zoom → Full X to see the waveforms as shown in Figure 12. Compare the results as shown in Figure 12 with your verilog test stimulus file so that you can see what each verilog command does in your functional output file.


of 14

Figure 12. SimVision Waveform Output.

16. The Waveforms in the SimVision window can be printed by selecting File → Print Window… option. While printing you can add Designer Name, Company Name, etc.

The Verilog test stimulus file can be written in different ways. See Figures 13 and 14 as more examples (note that these stimulus files are strictly for a 2-bit adder circuit). Figure 14 could be used to exhaustively check the performance of such a 2-bit adder circuit, and the SimVision waveform output results for this input stimulus is shown in Figure 15. It’s good practice to compare figures 14 and 15 and see the cause and effect.


of 14

Figure 13. Verilog Stimulus File Example 1.


of 14

Figure 14. Verilog Stimulus File Example 1.


of 14

Figure 15. Waveform Output results.

7. ASSIGNMENT Make an 8-bit accumulator circuit based on the preceding work flow and perform a functional test on your design to ensure accurate performance.

• Hand in the following printouts: o your Full Adder circuit (20%) o your 8-bit accumulator circuit (20%) o your SimVision waveform output results (20%)

• Show the instructor your SimVision waveform output results (in the tool window) and demonstrate that your design is working properly. How high does your accumulator count? (40%)

cpe/ee 427, cpe 527, vlsi design i: laboratory assignment …milenka/cpe527-05f/labs/lab3.pdf ·...

Documents