cpe/ee 421 microcomputersmilenka/cpe421-05f/notes/cpe421-s01_21.pdf · cpe/ee 421 microcomputers u...

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CPE/EE 421/521 Microcomputers 1

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CPE/EE 421Microcomputers

Instructor: Dr Aleksandar MilenkovicLecture Notes

S01

*Material used is in part developed by Dr. D. Raskovic and Dr. E. Jovanov


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CPE/EE 421 Microcomputers

Syllabustextbook & other referencesgrading policyimportant datescourse outline

Prerequisitesmemory organizationdecodingcombinatorial and sequential logicimportant for system architecture

Microcomputer Lab (EB 106)Introduction sessions Lab instructor

Class#1

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CPE/EE 421 Microcomputers

LAB Sessionon-line LAB manualAccess cardsAccounts

Lab Assistant: Joel Wilder

Lab sessions • Lab session #1: Monday 6:00 – 8:00 PM• Lab session #2: Monday 8:00 – 10:00 PM

Sign-up sheet - if needed


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Microcomputer

Stand alone system based on a microprocessor

An embedded system –dedicated to a specific application

control system/monitoring systemoptimization for a single function (system resources, extension, …)block diagram

• inputs → processing → outputs

Number of microprocessors in our environment?

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Block Diagram

µP 78 ºINPUT PROCESSING OUTPUT

control signalsTemperature sensor

System

t, states A/D µP system D/A

Input Processing Output


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Microprocessor System ArchitectureSystem Architecture

Single Board Computers (SBC)block diagram (modules, cards)

System busMultibus, VME, ISA, PCI, …Multiple masters

CPUClock and CPU Control Circuits

• 1 MHz - 1 GHz• power-up and reset circuits

Address DecoderAddress and Data Bus BuffersBus Arbitration ControlMemory management


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Microprocessor System Architecture #2

Memory ModuleVirtual memory / Physical memoryROM, RAM, video memorystatic/dynamic

Peripheral Moduleserial interface

• RS232 (CRT, mouse), USB, Firewire (IEEE 1394)

parallel interface• printer interface

timer• time/frequency measurement

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Microprocessor System Architecture #3

PC architecture

ISA

PCI

Memory

CPU


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Block Diagram of a personal computer

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A Typical Small Embedded System – Digital Thermometer

Todd D. MortonEmbedded Microcontrollers

Copyright ©2001 by Prentice-Hall Inc.


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A Microcontroller-Based System

Todd D. MortonEmbedded Microcontrollers

Copyright ©2001 by Prentice-Hall Inc.

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A Microcontroller-Based System

LCD

Switches

RS232 controller

Thermistor

Analog I/O

RS232

2-axes joystick

Adj. Vol. Regul.

LEDs

µCKeypad


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Wireless Body Area Network

PersonalServer

Emergency Server

Physician’s Server

Medical Server(Mayo Clinic)

GPRS

ZigBee orcustom wireless

Internet

BodyArea

Network

PPG &movement sensor

Movementsensors

ECG &tilt sensor

Wireless gateway &temperature/

humidity sensor

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Conventional Computer Architecture

Von Neumann Architecture

PE(Processing Element)

Control Unit

ALU

Read/WriteMemory

I/O(peripherals)

address

control

data

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2

1

0

Memory

log2N

W bits


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Microprocessors - History

Implementationssize (room, cabinet, desktop, handheld, …)speed (doubling 18-20 months)power consumption

Von Neumann ArchitectureProcessing Elements

• sequential execution

Read/Write Memory• linear array of fixed size cells• Data and instruction store

I/O unitAddress/Data/Control bus

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Intel: First 30+ Years

Intel 4004November 15, 19714-bit ALU, 108 KHz, 2,300 transistors, 10-micron technology

Intel Pentium 4August 27, 200132-bit architecture, 1.4 GHz (now 3.08), 42M transistors (now 55+M), 0.18-micron technology (now 0.09)


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HTechnology Directions: SIA Roadmap

Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735 .580 .255 .110 .049 .022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm2) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183

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History #2

PE(Processing Element)Read/Write

Memory

address

data


ProgramMemory

DataMemory


Harvard Architecture

address

data

data

address


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History #3

Processor/memory discrepancyMemory hierarchyOn-chip/off-chip memory

Microprocessor executionFetch > Decode > Execute

System on a chip - MicrocontrollerCost, smaller PCB, reliability, power. Applications

EvolutionMicroprocessorMicroprocessor-on-a-chipSystem-on-a-chipDistributed-system-on-a-chip

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History #4

Challengesscalability

• billions of small devices• performance

availability• hardware changes• system upgrade• failures• code enhancements

fault tolerance


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HHistory #5Year Processor MIPS1969 4004 0.061970’s 808x 0.641982 286 11985 386 51989 486 201993 Pentium 1001996 P II 2501999 P III 5002000 P 4 1500

0

200

400

600

800

1000

1200

1400

1600

286 386 486 Pentium P II P III P 4

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HTechnology Trends

The natural building block for multiprocessors is now also about the fastest!

Perfo

rman

ce

0.1

1

10

100

1965 1970 1975 1980 1985 1990 1995

Supercomputers

Minicomputers

Mainframes

Microprocessors


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Clock Frequency Growth Rate

• 30% per year

0.1

1

10

100

1,000

19701975

19801985

19901995

20002005

Clo

ck ra

te (M

Hz)

i4004i8008

i8080

i8086 i80286i80386

Pentium100

R10000

P4

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HTransistor Count Growth Rate

•100 million transistors on chip by early 2000’s A.D.•Transistor count grows much faster than clock rate

40% per year, order of magnitude more contribution in 2 decades

Tran

sist

ors

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

19701975

19801985

19901995

20002005

i4004i8008

i8080

i8086

i80286i80386

R2000

Pentium R10000

R3000

P4


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HGeneral Technology Trends

DEC AlphaHP 9000

750

IBMRS6000

540MIPS M2000MIPS

M/120Sun 4260

020406080

100120140160180

1987 1988 1989 1990 1991 1992

IntegerFP

• Microprocessor performance increases 50%-100% per year• Transistor count doubles every 3 years• DRAM size quadruples every 3 years• Huge investment per generation is carried by huge

commodity market

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Conventional Computer Architecture



Control Unit

ALU

Read/WriteMemory

I/O(peripherals)

address

control

data

N

3

2

1

0

Memory

log2N

W bits


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HStorageDivergence between memory capacity and speed more pronounced

Capacity increased by 1000x from 1980-95, speed only 2xGigabit DRAM by c. 2000, but gap with processor speed much greater

Larger memories are slower, while processors get fasterNeed to transfer more data in parallelNeed deeper cache hierarchiesHow to organize caches? Speed Size

ns ~KB

10ns ~MB

100ns ~100MB

10ms ~10GB

>100ms ~TB

Registers

Cache

Main memory

Hard disk

Archive

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Instruction Sets

Software costs growing faster than hardware costs (1970s)

Machine language v.s. HLLSupport for high-level languagesGap between high level languages and computer hardware - semantic gap

CISC - Complex Instruction Set ArchitectureVariety of instructions and addressing modesDEC VAX

HLLCA - High Level Language Computer Architecture


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RISC Architectures

Resolve problems using simpler architecture"The case for the reduced instruction set computers" Patterson & Ditzel [1980]

Stanford MIPS (Hennessy, 1981)

Commercial processors: MIPS R2000 (1986), IBM RS6000, SPARC, PowerPC, etc.

Good design methodology

Efficient pipelining and compiler-assisted scheduling of pipeline

Make the Common Case Fastfavor the frequent case

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cycleii

i TCPInT ⋅⋅=∑

RISC Methodology

Program execution time:

For all instructionsin the instruction set processor cycle time [s]

cycles per instruction

instruction count


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HInstruction Frequency

(%) load 22 cond. branch 20 compare 16 store 12 add 8 and 6 sub 5 mov reg-reg 4 or 1 xor, not, etc. 1 uncond. branch 1 call 1 return, jmp indirect 1 shift 1

80x86 Instruction Mix for SPECint92 Programs [PatHen96]

70%

42%

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HInstruction Execution

IF ID OF EX ST IFMem

PC 1000 1000

A=B+C A+=Cresult = op1 OPERATION op2 ADD R1, M(1000)

t

100ns 100ns1ns 1ns

…

When f = 5MHz (’70s) Tcycle = 200nsTmem = 200ns

When f = 1000MHz (’90s) Tcycle = 1nsTmem = 50ns

…

3 × 100ns = 300ns2 × 1ns = 2ns

302ns


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HPipelinetimeIF

program

ID

IF

OF

ID

IF

EX

OF

ID

IF

ST

EX

OF

ID

IF

IF

ST

EX

OF

ID

#100

#4#3

if( ) … #2#1 CPI = 1

INSTR

#1

#2

#4

#2

#5

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System Memory

N

3

2

1

0

W BytesSystem memory

addressWord

addressByte

address

log2N log2W

128 KB

101…

128 KB (32K*4B)

2Example: 2 banks, 32 KW each, 4-byte words

A0A1A2A16A17A31

log24=2log232K=15log2B=1

Word address Byte

Bankaddress

Select

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