course topics - outline · 3 expressions and operands expressions are constructs that combine...
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Course Topics - Outline
Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 – Behavioral modeling B Lecture 7 – Behavioral modeling C Lecture 8 – Data flow modeling Lecture 9 – Gate Level modeling Lecture 10 – Tasks and Functions Lecture 11 – Advanced Modeling Techniques Lecture 12 - Coding Styles and Test Benches Lecture 13 - Switch Level modeling
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Lecture 4 - Operators
Expressions and Operands Operators Types Bus Operators Arithmetic Operators Bitwise Operators Reduction Operators Logical Operators Relational Operators Conditional Operator Operators Precedence Signed arithmetic Exercise 4
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Expressions and Operands
Expressions are constructs that combine operators and operands to produce a result.
Operands can be any one of the data types defined in the previous lecture: integers real numbers nets registers times bit-select (one bit of vector net or vector register) part select (selected bits of vector net or vector register) memories function calls (discussed later)
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Operators
Operators are of three types:
Unary
Binary
Ternary
Unary operators precede the operand
Binary operators appear between two operands
Ternary operators have two separate operators that separate three operands
a = ~ b ; // ~ is a unary operator. b is the operand
a = b && c ; // && is the binary operator. a and b are operands
a = b ? c : d ; // ?: is a ternary operator. b, c and d are operands
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Operators Types
Bus Operators
Arithmetic Operators
Bitwise Operators
Reduction Operators
Logical Operators
Relational Operators
Conditional Operator
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Bus Operators
A = 8'b10001011
Operator Example
[ ]
{ }
{{ }}
<<
>>>
>>
Description
Bit/Part Select
Concatenation
Replication
Shift left logical
Shift right arithmetic
Shift right logical
A[0] = 1'b1; A[5:2] = 4'b0010 ;
{A[5:2],A[7:6],2'b01} = 8'b00101001
{3{A[7:6]}} = 6'b101010
A<<2 = 8'b00101100
A>>3 = 8‘b00010001
A>>>3 = 8‘b11110001
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Arithmetic Operators
A = 8'b10001011 = 139 B = 8’b00001100 = 12
Operator Example
+
-
*
/
%
Description
Addition
Subtraction
Multiplication
Division
Modulus
A + 12 = 151 = 8‘b10010111
A – 10 = 129 = 8‘b10000001
A * 3 = 417 = 9‘b110100001
A / 2 = 69 = 7'b1000101
A % 5 = 4 = 3'b100
** Power (exponent) B ** 2 = 144 = 8'b10010000
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Bitwise Operators
A = 8'b10001011
Operator Example
~
&
|
^
~^
Description
Inverse / NOT
AND
OR
XOR
XNOR
~A = 8'b01110100
A[2] & A[1] = 1'b0
A[2] | A[1] = 1'b1
A[2] ^ A[1] = 1'b1
A[2] ~^ A[1] = 1'b0
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Reduction Operators
A = 8'b10001011
Operator Example
&
~&
|
~|
^
Description
AND
NAND
OR
NOR
XOR
&A = A[0] & A[1] & … A[7] = 1'b0
~&A = ~(A[0] & A[1] & … A[7]) = 1'b1
|A = A[0] | A[1] | … A[7] = 1'b1
~|A = ~(A[0] | A[1] | … A[7]) = 1'b0
^A = A[0] ^ A[1] ^ … A[7] = 1'b0
~^ XNOR ~^A = ~(A[0] ^ A[1] ^ … A[7]) = 1'b1
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Logical Operators
A = 8'b10001011
Operator Example
!
&&
||
==
!=
Description
NOT
AND
OR
EQUAL
NOT EQUAL
!A[1] = FALSE, !A[2] = TRUE
A[0] && A[1] = TRUE
A[0] || A[2] = TRUE
A[3:0] == 4'b1011 = TRUE
A[3:0] != 4'b1011 = FALSE
<,<=,>,>= COMPARE A[3:0] < 13 = TRUE
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Relational Operators
>, >=, <, <= : Determine relative value. Registers and nets are treated as unsigned. Real and Integer operands, may be signed. If any bit is unknown, the result will be unknown. Result is one bit value: 0, 1 or X
==, != : Logical equality, inequality. Registers and nets are treated as unsigned. Real and Integer operands, may be signed. If any bit is unknown (or high-impedance), the result will be unknown. 1-bit result 0,1 or X
===, !== : case equality, inequality. The bitwise comparison includes X and Z values. All bits must match for equality. The result is either True or False. 4 ‘b 110Z == 4 ‘b110Z => FALSE
4 ‘b 110Z === 4 ‘b 110Z => TRUE
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Conditional Operator
The conditional operator (?:) can be used in place of the if statement when one of two values is to be selected for assignment.
The general form of the conditional operator is: :: = <cond_expression> ? <true_expr> : <false_expr> If the first expression is TRUE, then the value of the
operator is the second expression. Otherwise the value is the third expression.
May be a part of a procedural or continuous statement. Conditional operator can be used both in behavioral and
gate level structural modeling. Example: 2-to-1 MUX Y = (sel)? A : B ; B
Y
sel
0
1 A
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Operators Precedence
Operators Operators Symbols
Unary
Multiply, Divide, Modulus
Add, Subtract
Shift
Equality
Relational
+ - ! ~
* / %
+ -
<< >> >>>
< <= > >=
== != === !==
Reduction
Logical
Conditional
&, ~&, ^, ^~, |, ~|
&&
?:
Highest Precedence
Lowest Precedence
If no parentheses are used to separate operands then Verilog uses the following rules of precedence: (good practice: use parentheses)
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Signed data types
For integer math operations, data types of the operands are used to determine if signed or unsigned arithmetic should be performed.
To perform signed arithmetic, both operands must be signed. If any operand in an expression is unsigned, unsigned operations are performed.
Verilog 1995 provides only one signed data type, 32bits integer. reg and net data types are unsigned.
The rule still applies for Verilog 2001 but now all regs, wires and ports can be declared as signed.
Sized numbers, bit and part select results and concatenation, yield unsigned values.
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Signed arithmetic – Verilog 2001 extensions
Verilog 2001 provides a new specifier, the letter ‘s’ that can be combined with the radix specifier to indicate that the literal number (sized value) is a signed value. For example, 2 represented as a 3-bit signed hex value would be specified as 3’sh2. Somewhat confusing is specifying negative signed values. The value -4 represented as a 3-bit signed hex value would be specified as -3’sh4.
A decimal number is always signed. Function return values can be declared as signed. Operands can be converted from unsigned to signed,
using system functions as casting operators, $unsigned and $signed.
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Type Casting
Operands can be converted from unsigned to signed, using system functions as casting operators, $unsigned and $signed.
The casting operators, $unsigned and $signed, have effect only when casting a smaller bit width to a larger bit.
Casting using $unsigned(signal_name) will zero fill the input. For example A = $unsigned(B) will zero fill B and assign it to A.
Casting using $signed(signal_name) will sign extend the input. For example, A = $signed(B).
If the sign bit is X or Z the value will be sign extended using X or Z, respectively.
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Signed declarations examples
reg signed [63:0] data ; wire signed [7:0] vector ; input signed [31:0] a ; function signed [128:0] alu ; integer i : // 32 bit signed value 16'hC501 // an unsigned 16-bit hex value 16'shC501 // a signed 16-bit hex value reg [63:0] a; // unsigned data type always @(a) begin result1 = a / 2; //unsigned arithmetic result2 = $signed(a) / 2; //signed arithmetic end
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Signed Addition and Signed Multiplication
module add_signed_2001 ( input signed [2:0] A, input signed [2:0] B, output signed [3:0] Sum) ; assign Sum = A + B ; endmodule module mult_signed_2001 ( input signed [2:0] a, input signed [2:0] b, output signed [5:0] prod) ; assign prod = a*b ; endmodule
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MIPS 5-stage pipeline Architecture
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MIPS Instruction Set Architecture (ISA)
I type instructions have opcode, address of 1 operand, address of destination result and a 16bits Constant (imm). Imm should be sign extended to 32bits signed number for addi. Imm should be zero extended to 32bits signed number for ori. Sh – 5bits shift amount for shift operations
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MIPS Instructions Set
Notes Format/Opcode/Func Meaning syntax Name Category
Signed operands
20h 0 R $d=$s+$t add $d,$s,$t Add Arithmetic
Signed operands
22h 0 R $d=$s-$t sub $d,$s,$t Sub
Signed operands
- 8 I $t=$s+ C (signed)
addi $t,$s,C Addi
Unsigned operands
25h 0 R $d=$s|$t or $d,$s,$t Or Logical
Unsigned operands
- Dh I $t = $s | C ori $t,$s,C Ori
Unsigned operands
0 0 R $d=$t<<sh sll $d,$t,sh Shleft logical
Bitwise Shift
Unsigned operands
2 0 R $d=$t>>sh srl $d,$t,sh Sright logical
Unsigned operands
3 0 R $d=$t>>>sh
sra $d,$t,sh Sright arithm
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MIPS Execution Unit Block Diagram
in1
in2
result
op
32
32
32
3
MU
XM
UX
1st operand
2nd operand
extended shift amount
Imm_extend
32
32 5 zero extend
16 z_s extend
rf_do1
ALU
ctrl ALUop
sel2
sel1
0
1
0
1
z_s
imm
sh_extend
rf_do2 32
32
shamt
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MIPS / ALU Instructions
Instructions: Signed Operations: 1. add (signed) : result = in1 + in2 ; 2. sub (signed) : result = in1 - in2 ; 3. addi (signed) : result = in1 + imm ; Unsigned Operations: 4. or (bitwise logic) : result = in1 | in2 ; 5. ori (bitwise logic) : result = in1 | imm ; 6. shift left logical (sll): result = in2 << sh ; 7. shift right logical (srl): result = in2 >> sh ; 8. shift right arithmetic (sra): result = in2 >>> sh ;
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Exercise 4
Parity Checker Check data integrity by comparing received parity bits with calculated parity values. Employ the reduction XOR operator ^[data] for parity calculation.
MIPS ALU Design a limited functionality MIPS ALU module Implement the following Instructions: Signed Add, Add immediate, Sub. Use signed arithmetic. Bitwise Or, Or immediate. Unsigned. Shift left logical, Shift right logical, Shift right arithmetic, Unsigned. Use signed, negative number to demonstrate the difference between arithmetic & logical right shift.
Advanced Exercise: MIPS Execution Pipeline Stage.