cosynthesis algorithms partitioning

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Winter-Spring 2001 Codesign of Embedded Systems 2

Topics Introduction

Preliminaries

Hardware/Software Partitioning

Distributed System Co-Synthesis


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Topics Introduction

A Classification

Examples

Vulcan

Cosyma


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Introduction to

HW/SW Partitioning The first variety of co-synthesis applications

Definition

A HW/SW partitioning algorithm implements aspecificationon some sort of multiprocessorarchitecture

Usually

Multiprocessor architecture = one CPU + someASICs on CPU bus


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Introduction to

HW/SW Partitioning (contd) A Terminology

Allocation

Synthesis methods which design the multiprocessortopology along with the PEs and SW architecture

Scheduling

The process of assigning PE (CPU and/or ASICs) time toprocesses to get executed


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Introduction to

HW/SW Partitioning (contd) In most partitioning algorithms

Type of CPU is fixed and given

ASICs must be synthesized What function to implement on each ASIC?

What characteristics should the implementation have?

Are single-rate synthesis problems

CDFG is the starting model


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HW/SW Partitioning (contd) Normal use of architectural components

CPU performs less computationally-intensive

functions ASICs used to accelerate core functions

Where to use?

High-performance applications

No CPU is fast enough for the operations

Low-cost application

ASIC accelerators allow use of much smaller, cheaperCPU



A Classification Criterion: Optimization Strategy

Trade-off between Performanceand Cost

Primal Approach Performance is the primary goal

First, all functionality in ASICs. Progressively move moreto CPU to reduce cost.

Dual Approach

Cost is the primary goal

First, all functions in the CPU. Move operations to theASIC to meet the performance goal.



A Classification (contd) Classification due to optimization strategy

(contd)

Example co-synthesis systems Vulcan (Stanford): Primal strategy

Cosyma (Braunschweig, Germany): Dual strategy


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Co-Synthesis Algorithms:HW/SW Partitioning

HW/SW Partitioning Examples:

Vulcan



Partitioning Examples:

Vulcan Gupta, De Micheli, Stanford University

Primal approach

1. All-HW initial implementation.2. Iteratively move functionality to CPU to reduce

cost.

System specification language

HardwareC

Is compiled into a flow graph




Vulcan (contd)nop

x=a y=b

1 1x=a; y=b;

HardwareC

cond

x=e y=f

c>d cd)x=e;

else y=f;

HardwareC


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Vulcan (contd) Flow Graph

is executed repeatedly at some rate

can have initiation-time constraints for each node t(vj)+lijt(vj) t(vj)+uij

can have rate constraints on each node

miRiMi


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Vulcan (contd) Vulcan Co-synthesis Algorithm

Partitioning quantum is a thread

Algorithm divides the flow graph into threadsandallocates them

Thread boundary is determined by

1. (always) a non-deterministic delay element, such as waitfor an external variable

2. (on choice) other points of flow graph Target architecture

CPU + Co-processor (multiple ASICs)


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Vulcan (contd) Vulcan Co-synthesis algorithm (contd)

Allocation

Primal approach Scheduling

is done by a scheduler on the target CPU

is generated as part of synthesis process

schedules all threads (both HW and SW threads)

cannot be static, due to some threads non-deterministicinitiation-time


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Cost estimation

SW implementation Code size

relatively straight forward

Data size

Biggest challenge.

Vulcan puts some effort to find bounds for eachthread

HW implementation

?


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Performance estimation

Both SW- and HW-implementation From flow-graph, and basic execution times for the

operators


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Vulcan (contd) Algorithm Details

Partitioning goal

Allocate each thread to one of two partitions CPU Set: FS Co-processor set: FH

Required execution-rate must be met, and total costminimized


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Vulcan (contd) Algorithm Details (contd)

Algorithm steps

1. Put all threads in FHset2. Iteratively do

2.1. Move some operations to FS.

2.1.1. Select a group of operations to move to FS.

2.1.2. Check performance feasibility, by computing

worst-case delay through flow-graph given the newthread times

2.1.3. Do the move, if feasible

2.2. Incrementally update the new cost-function to reflectthe new partition


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Vulcan cost function

f(w) = c1Sh(F

H) - c2Ss(F

S) + c3B - c4P + c5|m|

c: weight constants

S(): Size functions

B: Bus utilization (


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Complementary notes

A heuristic to minimize communication Once a thread is moved to FS, its immediate successors

are placed in the list for evaluation in the next iteration.

No back-track

Once a thread is assigned toF

S, it remains there Experimental results

considerably faster implementations than all-SW, butmuch cheaper than all-HW designs are produced


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Co-Synthesis Algorithms:HW/SW Partitioning

HW/SW Partitioning Examples:

Cosyma


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Cosyma Rolf Ernst, et al: Technical University of

Braunschweig, Germany

Dual approach1. All-SW initial implementation.

2. Iteratively move basic blocks to the ASICaccelerator to meet performance objective.

System specification language Cx

Is compiled into an ESG(Extended Syntax Graph)

ESGis much like a CDFG


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Cosyma (contd) Cosyma Co-synthesis Algorithm

Partitioning quantum is a Basic Block

A Basic Blocks is a branch-free block of program Target Architecture

CPU + accelerator ASIC(s)

Scheduling

Allocation Cost Estimation

Performance Estimation

Algorithm Details


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Cosyma (contd) Cosyma Co-synthesis Algorithm (contd)

Performance Estimation

SW implementation Done by examining the object code for the basic block

generated by a compiler

HW implementation

Assumes one operator per clock cycle.

Creates a list schedule for the DFG of the basic block. Depth of the list gives the number of clock cycles required.

Communication

Done by data-flow analysis of the adjacent basic blocks.

In Shared-Memory

Proportional to number of variables to be accessed


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Cosyma (contd) Experimental Results

By moving only basic-blocks to HW

Typical speedup of only 2x Reason:

Limited intra-basic-block parallelism

Cure:

Implement several control-flow optimizations to increase

parallelism in the basic block, and hence in ASIC Examples: loop pipelining, speculative branch execution with

multiple branch prediction, operator pipelining

Result:

Speedups: 2.7 to 9.7

CPU times: 35 to 304 seconds on a typical workstation


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Winter Spring 2001 Codesign of Embedded Systems 29

What we learned today HW/SW Partitioning: One broad category of

co-synthesis algorithms

Criteria by which a co-synthesis algorithm iscategorized

cosynthesis algorithms partitioning

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