cosa: integrated verification for agile hardware design
TRANSCRIPT
SCALING UP FORMAL TOOLS FOR POSH OPEN-SOURCE HARDWARESTANFORD/PRINCETON
SHARAD MALIK
INTEGRATION EXERCISE, DETROIT, 17 JULY 2019
UPSCALE
Goals
Develop verification tools and techniques that are:Fast (overnight)Formal (exhaustive)ScalableAutomaticOpen-source friendly
…and that encourage clean interfaces
Team
Clark Barrett
CS Department, Stanford University
Expertise in constraint solving and formal verification
Co-founder of Satisfiability Modulo Theories (SMT) research area
ACM distinguished scientist; Haifa Verification Conference Award; IBM Software Innovation award
Aarti Gupta
CS Department, Princeton University
Expertise in formal verification, program analysis, decision procedures
Led industry research dept for 10 years (NEC Labs)
Fellow of ACM; three NEC technology commercialization awards
Subhasish Mitra
CS/EE DepartmentsStanford University
Expertise in robust computing, design, validation, and test
X-Compact test compression widely used in industry
Fellow of IEEE and ACM; SRC Technical Excellence Award; Intel Achievement Award; ACM/IEEE Technical Impact Award in EDA
Mark Horowitz
CS/EE DepartmentsStanford University
Expertise in analog and digital design
High-speed I/O in industry (founder of Rambus Inc)
Fellow of IEEE and ACM; Natl Academy of Engineering; American Academy of Arts and Science; Don Pederson IEEE Technical Field Award
Sharad Malik
EE DepartmentPrinceton University
Expertise in digital design, propositional satisfiability (SAT)
Award-winning SAT solver (Chaff) widely used in research and industry
Fellow of IEEE and ACM; DAC most-cited paper; CAV award; ACM/IEEE Technical Impact Award in EDA
Research Program
1.Open-source model checking tools (alternative to commercial tools)2.Instruction Level Abstractions (ILAs) to model complex interfaces3.Special models for analog/mixed-signal components4.Symbolic QED, A-QED, and ILA-based tools to verify digital blocks5.E-QED for system-level prototyping6.Open-source high-speed Phy (to demonstrate mixed-signal techniques)
SYMBOLIC QED: DEMO VIDEO [LINK]
–
+
– +Formal
Directed
AUTOMATIC
THOROUGH
Symbolic QEDUses model checking
Processors, accelerators,Billion-transistor chips
Detected bugs
Random
Design +
Instruction Set Architecture
~~
~~Symbolic
QED
RTL
Today’s Demos
1.Using A-QED to Verify Accelerators2.Using ILA Specifications to Generate Sound Co-Simulation Models3.Analog Emulation Using Digital FPGAs
8
A-QED
Existing accelerator verification
Time consuming, manual, not thorough
Key Idea
Symbolic QED concepts for stand-alone hardware accelerators
Existing Symbolic QED verifies processor + accelerator
A-QED targets high-level and RTL accelerators
Today’s demo: A-QED with High Level Synthesis
Further opportunities: A-QED + ILA (Instruction-Level Abstraction)
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Demo: A-QED for HLS Designs
A-QED RTL automatically synthesized with accelerator
Interface connectivity generated by HLS tool
A-QED RTL only used for verification
Symbolically analyzes all interleavings of two data sets
AES Demo: single function accelerator (non-programmable)
All data loaded at start of operation
High Level Accelerator +
A-QED Checker
High Level Synthesis
(HLS)
Accelerator RTL+
A-QED Checker RTL
Demo by: Eshan Singh, Stanford (LINK)
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Part 2: Using ILA Specifications to Generate Sound Co-Simulation Models
Collaboration with Xilinx POSH performer -Outcome of San Diego Integration Exercise
ILAng manual and documentation: https://bo-yuan-huang.gitbook.io/ilang/Publicly open-sourced on GitHub: https://github.com/Bo-Yuan-Huang/ILAngILAng model database: https://github.com/PrincetonUniversity/IMDb
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• Instruction-Level Abstraction (ILA) provides specification forsoftware accessible devices/accelerators
• RTL formally verified against ILA specification• Use sound high-level co-simulation models generated from
verified ILAs
Generating Sound Co-Simulation Models from ILAs
OS/bin
QEMU(core)
Xilinx co-sim lib
devicesimulator
verified ILA model
hand-crafted high-level model
Low-level RTL model
sim-vs-designmismatch
simulationspeed
Demo by: Yue Xing, Princeton (LINK)
Demo at San DiegoIntegration Exercise
analog_model.py analog_model.sv
Write Python model Automatically compiled into synthesizable SystemVerilog
“Analog” Digital
MSDSL
msdsl is on GitHub:https://github.com/sgherbst/anasymod
results.vcd
AnalogModel
Digital
Generate FPGA bitstream
anasymod is on GitHub:https://github.com/sgherbst/anasymod
ANASYMOD
Upload to FPGA and run emulation
View/process results
top.bitGTKwave, Simvision,
etc.
Change test parameters and re-run
Demo by: Steven Herbst, Stanford (LINK)
UPSCALE
Websitehttp://upscale.stanford.edu/
GitHubhttps://github.com/upscale-project
Demos/VideosSymbolic QED http://upscale.stanford.edu/materials/sqed.mp4
Mixed-signal emulation http://upscale.stanford.edu/materials/hslinkemu.mp4
A-QED http://upscale.stanford.edu/materials/aqed.mp4
ILA http://upscale.stanford.edu/materials/ila.m4v
The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.