cortex-a5: arm’s lowest power, smallest area processor ... seminar presentations... · 2 arm...

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Cortex-A5 The smallest, lowest power ARMv7 application processor

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ARM Cortex A Series - Applications CPUs

focused on the execution of complex OS and user

applications

ARM Cortex R Series - Deeply embedded

processors focused on Real-time environments

ARM Cortex M Series - Microcontroller cores

focused on very cost sensitive, deterministic,

interrupt driven environments

Perf

orm

an

ce

The ARM Cortex™ Family

Cortex-M3

Cortex-R4(F)

Cortex-M0

Cortex-A8

SC300

Cortex-M1

x1-4

Cortex-A9

Cortex-M4

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Cortex-A5 is a Cortex-A Processor

Cortex™-A processors feature virtual memory management

for running advanced OS eg. Linux, Android™, Windows

Embedded Compact.

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Cortex-A5: What’s unique about it?

Most energy efficient applications

processor with internet ability

The smallest application processor

capable of running Linux and Android

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Cortex-A5 in Mobile

Designed for low cost smart

phones

1/3 area, power of Cortex-A9

ARMv7-A (Cortex-A8, A9) compatible

Differentiates vs. high end smart phones

2012 Mobile Market

Mobile audio Leverages ARM and NEON software

Software solution in 1-2mW or less

Offload tasks from main CPU

Low-Cost (Voice centric)

39%

Web-enabled Feature Phone 28%

Entry-level smartphone

17%

Premium Smartphone

16%

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Cortex-A5: low cost internet everywhere

General purpose MPUs

Digital televisions

Smart energy meters

Low cost printers

STB audio systems

Digital picture frames

Full OS support in the smallest power and area

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Cortex-A5 is…

ARM9 power and area

>ARM11 performance

100% Cortex-A8/A9 compatible

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0

1

2

3

DMIPS Performance mW/MHz Core Area

Rela

tive t

o A

RM

926

greater than

ARM1176 performance

less than

ARM926 power ~ARM926 area

Co

rtex-A

5

AR

M11

76

AR

M926

Cortex-A5 provides…

Co

rte

x-A

5

AR

M1176

AR

M926

Co

rtex-A

5

AR

M1176

AR

M926

Integer core only, no NEON, no cache

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TrustZone for secure transactions

Thumb-2 for code density, performance

NEON multimedia performance

A-Class processors feature…

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Cortex-A5 – High Volume and Value

Power-efficient Performance 1.6 DMIPS/MHz per core

Full application compatibility with Cortex-A and classic ARM processors

Great browsing performance

Feature set of Cortex-A9 Neon, FPU, TrustZone

Symmetric Multi-processing

Highly configurable

Uniprocessor only version available

Optional NEON / FPU

Optional external L2 cache 128KB – 8MB

ARM® Cortex™-A5 MPCore

4

3

2

1-2x 64-bit AMBA AXI Bus Interface

ACP

Cortex-A5 ARMv7

32b Core

NEON SIMD engine

Floating

Point Unit

4-64K

I-Cache

4-64K

D-Cache

Core 1

Snoop Control Unit (SCU)

40nm Process Targets

Performance 1.0-1.2GHz (Shipping in Silicon)

Total Power Sub100mW power/core

* Measurements for a single core with 32K L1 Caches,

NEON, FPU

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Need even more performance?

Cortex-A5 Multiprocessor – up to 4 coherent cores

Includes :

Snoop Control Unit (SCU) for coherency

Interrupt controller

Timers

Accelerator coherency port

2nd AXI port

Highly configurable

1-4 cores

Optional NEON / FPU

L2 cache 128KB – 8MB

ACP for coherent I/O

Cortex-A5MP CoreSight™ Multicore Debug and Trace

Generic Interrupt Control and Distribution

Dual 64b AMBA3 - Advanced AXI Bus Interfaces

Snoop Control Unit (SCU) Cache to

cache

transfers

Snoop

Filtering

Accelerator

Coherence Timers

NEON/FPU Data Engine

Integer CPU - TrustZone, Th-2

L1 Cache



L1 Cache



L1 Cache



L1 Cache

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Cortex-A5 Typical Configurations

Market CPU

Configuration

Notes

Mobile

Consumer

Cortex-A5 MP2 w L2

Entry Smartphone

Low-cost consumer

Lowest cost

ARMv7-A

Embedded Uni-Processor

Small area CPU

with MMU for top-

end of MCU

product line

Enterprise Cortex-A5 MP4 w L2

Small area multi-

core CPU as

offload accelerator

A5

A5 A5

A5

A5 A5

A5

SCU

SCU

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Example Cortex-A5 SoC NIC-400 Network Interconnect

Hierarchical design

Advanced Quality of Service

(QoS) for performance and latency

Level 2 Cache Controller

Increase CPU performance

Reduce external memory

accesses

Dynamic Memory Controllers

LPDDR2, DDR2

LPDDR, DDR, NVM

Programmable DMA Controller

Off load the CPU

Multi-channel

Cortex-A5

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Summary

The Cortex-A5 processor is the lowest area, power and high

performance application processor in the market today

Cortex-A5 processor has a very diverse application space

Large volume low-cost smartphones

Diverse home entertainment and networking solutions

Low-cost microcontrollers

More scalable and efficient dataplane solutions

Cortex-A5 processor leverages the eco-system and software

developed for the Cortex-A8 and Cortex-A9

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© 2012 Copyright Atmel Corporation 15

SAMA5D3 series

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ARM MPU Portfolio

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What’s new?

ARM® Cortex-A5TM core with ARMv7 Thumb2 instruction set

and Floating Point Unit (VFPU)

More performance

CPU frequency up to 536MHz

Bus speed up to 166MHz

More power-efficient

<1mA in Idle mode

More features

Gigabit Ethernet with IEE1588 support

2 CAN ports (8 mailboxes each)

High-end LCD with overlay channels and post processing

controller

32-bit external bus interface with DDR2/LPDDR/LPDDR2

support

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SAMA5D3 Derivatives

SAMA5D31 SAMA5D33 SAMA5D34 SAMA5D35

LCD

10/100 EMAC

10/100/1000

EMAC

Dual CAN

ISI

USB

Secure Boot

Crypto

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ARM® CortexTM-A5

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SAMA5D3

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Power-up Sequence

Simplified power-up sequence

Establish VDDIOP and VDDIOM first, then VDDPLL, and at last

VDDCORE

SAMA5D3-EK Power Circuitry

One dual step-down DC-DC converter and One LDO

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Operating points vs. Power supplies

Voltage Range

Crystal

frequency

(MHz)

DIV, MUL+1

PLL

frequency

(MHz)

Core

frequency

(MHz)

Bus

frequency

(MHz)

SDRAM

memories

Full Range

VDDCORE

[1.08V..1.32V]

12

16

24

48

1, 66

1, 50

3,100

3, 50

792

800

800

800

396

400

400

400

132 (div3)

133 (div3)

133 (div3)

133 (div3)

LP-DDR1,

DDR2,

LP-DDR2

VDDCORE

[1.2V..1.32V]

12

16

24

48

1, 89

2, 67

2, 89

4, 67

1068

536

1068

536

534

536

534

536

133 (div4)

134 (div4)

133 (div4)

134 (div4)

LP-DDR1,

DDR2,

LP-DDR2

VDDCORE

[1.2V..1.32V]

VDDIODDR

[1.75V..1.90V]

12

16

24

48

1, 83

2, 125

3, 125

6, 125

996

1000

1000

1000

498

500

500

500

166 (div3)

167 (div3)

167 (div3)

167 (div3)

DDR2 only

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Power consumption

Power consumption in active mode:

All peripheral clocks enabled

Power consumption in low power modes:

Processor clock

(PCK)

Bus speed

(MCK) PLLA

Power consumption on

VDDCORE

400 MHz 133 MHz 792 MHz 88 mA

498 MHz 166 MHz 996 MHz 106.3 mA

536 MHz 134 MHz 1068 MHz 110mA

Mode Conditions Power consumption on

VDDCORE

Idle

(MCK=133MHz)

Idle state, waiting for an interrupt

Peripheral clocks disabled 19 mA

Ultra low power ARM Core clock is 500Hz

Peripheral clocks disabled 0.3 mA

Backup Device only VDDBU powered 1.2 µA (on VDDBU)

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Memories

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External memories

The SAMA5D3 features

A multi-port DDR Controller

An External Bus Interface with Nandflash controller and Static Memory controller

8-16bit

32bit

DDR2/LP-DDR/LP-DDR2 support

4-bank/ 8-bank memories

1.8V

SLC/MLC nandflash support

PSRAM, SRAM, NORFlash,

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Security

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Security features

True Random Number Generator (TRNG)

Pass NIST Special Publication 800-22 and Diehard Random Tests Suites

Encryption Engine:

AES: the Advanced Encryption Standard

TDES: Triple Data Encription Standard

SHA: Supports Secure Hash Algorithm

Secure Boot Solution

03/14/201

2

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Connectivity

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Connectivity

3 FS/HS USB ports with on-chip transceivers

One device controller

One host controller with integrated root hub (3 downstream ports)

2 Ethernet MAC controllers

One 10/100Mbps ethernet controller (EMAC)

One 10/100/1000Mbps Gigabit ethernet controller (GMAC)

2 CAN controller with 8 mailboxes each

Softmodem interface (SMD)

3 High Speed MCI ports

4 USARTs, 3 UARTs, 1 DBGU

2 SSC

3 TWI with I2C and SMBUS support

03/14/201

2

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User interface

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LCD interface highlights

Dual AHB Master interface

Display size up to 1280x720 (720p) for TFT panels

Five-layer Overlay

1 High-end overlay (HEO)

2 Overlay windows (OVR)

1 Base layer (background)

1 HW cursor layer

Overlay channels enables different hardware 2D acceleration

PiP, alpha blending, scaling, rotation, color conversion, chroma upsampling

Post processing controller

03/14/201

2

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5-layer Overlay benefits

Support for multiple “overlay planes” to display windows on top of the image without destroying the image located below.

Background picture (Base layer)

Window with video (High-end HEO layer)

Dock (OVR1

layer) HW Cursor

(HCC layer)

On Screen Display

On-screen

display (OVR2 layer)

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Supported 2D acceleration features

Alpha blending

Rotation

Image rotation by 90°, 180°, 270°

Vertical and Horizontal flip

Scaling

With a non integer ratio

Up to 1280x720 pixels

Color conversion

YUV (Y’CbCr) to RGB

Chroma Upsampling

YUV 4:2:0 to YUV 4:4:4

Supported

Layers OVR1 OVR2 HEO HCC

Alpha

Blending

Rotation

Scaling

Color

Conversion

Chroma

Upsampling

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Control

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Control peripheral highlights

12-channel 12-bit ADC @ 1Msps

Auto calibration

5-wire resistive touchscreen support

One 4-channel 16-bit PWM

Two 3-channel 32-bit timers

Up to 160 GPIOs

03/14/201

2

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SAMA5D3-EK Evaluation Kit

CPU modules approach

Main Board (SAMA5D3x-MB)

CPU Modules (SAMA5D31-CM, SAMA5D33-CM, SAMA5D34-CM and SAMA5D35-CM)

Display module (SAMA5D3x-DM)

JTAG-ICE on board (SAM3U)

HDMI connector

MaxTouch LCD module available

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SAMA5D3x Software Deliverables

Early deliverables

Linux 3.4 Buildroot Distribution (early)

Final deliverables

Buildroot Distribution

OpenEmbedded/Angstrom Linux Distribution

Real Time Linux distribution

Android 4.0 distribution (source code)

QT Graphical library (source code)

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Development tools support

Developer Studio 5 www.arm.com/ds5

http://www.arm.com/products/tools/software-tools/ds-5/debugger/index.php



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CMSIS DAP

Supports AMP debug Cortex A5 and Cortex M

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Vybrid Module

www.phytec.com

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Vybrid and CMSIS DAP

A companion Kinetis chip is pre programmed with the CMSIS

DAP firmware

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Cosmic Board for Vybrid

Retail price $55.00 and $65.00

www.phytec.com/products/single-board-computers/

cortex-a5: arm’s lowest power, smallest area processor ... seminar presentations... · 2 arm...

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