copy of seminar ii 2

8/7/2019 Copy of Seminar II 2

1/20

M.E. (E&TC) Review of High Frequency PLL

Chapter 1

Introduction

1.1 Background:-Phase locked loops (PLLs) are an essential component in many wireline

and wireless applications for clocking and frequency synthesis. The challenges

of developing stable, low jitter clock sources become greater as the operating

frequency is increased. With the integration of digital and analog circuits

CMOS technologies are a preferred solution because of their documented high -

frequency performance and well established manufacturing base.

The generation of higher frequency clock signals continues to be driven

by wireless applications and high - speed digital links. There is an advantage

from a phase noise perspective to generate multiplied clock frequencies using a

low - order multiple instead of the lager multiplication factors commonly used.

This low multiplication factor requires that the components of the phase locked

loop (PLL) be able to operate at higher frequencies.

A phase locked loop, or more commonly abbreviated as PLL is basically

a closed loop feedback system. The action of the PLL is to lock the output

frequency and phase to the frequency and phase of an input signal. The input

signal can be sinusoidal or digital. Phase locking is not a new principle.

Synchronous reception of radio signals using PLL technique was described as

early as in 1932. The implementation of PLL with discrete components involves

circuits of considerable cost and complexity. For this reason, the use in the past

has been limited to specialized measurements. The development of monolithic

PLL now makes it highly economical as well as reliable.

The early applications of PLL were the synchronous detection of radio

signals. Starting in the 1960s' the NASA satellite programmers used the PLL

technique to determine the frequency of the signals transmitted by satellite.

However, there was an uncertainty of several kHz in the received signal due to

oscillator drift and Doppler shift. The transmitted signal was of very narrow

bandwidth, but because of the frequency drifts it was necessary that the receiver

bandwidth be much wider, with a resultant increase in noise, as receiver noise

SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING 2009-2010

1


2/20


power is proportional to the bandwidth. However, the satellite communication

system was improved by using a phase - locked loop to lock onto the

transmitted frequency, and thus permit a much narrower bandwidth with much

less output noise content.

1.2 Relevance:-

The digital phase - locked loop, DPLL, is a circuit that is used frequently

in modern integrated circuit design.In fact, the PLL is used in communication

system in two fundamentally different ways : (i) as a demodulator, where it is

used to follow phase or frequency modulation, and (ii) to track a carrier or

synchronizing signal which may vary in frequency with time. When operating

as a demodulator, the PLL may be thought of as a matched filter operating as a

coherent detector. When used to track a carrier, it may be thought of as a narrow

- band filter for removing noise from a signal.

This session presents current trends in PLLs that explore innovations in

all optical and high frequency PLLs. A common theme in all high frequency

PLLs to improve the locking range, gain, noise. Seven of the eight papers in this

session address this issue as follows:

1. This paper focused on locking range, noise, line width. The requirement

for narrow linewidth lasers or short - loop propagation delay makes the

realization of optical phase - lock loops using semiconductor lasers

difficult.

2. This paper focused on Gain, Optical Phase lock. This paper describes in-

line optical phase sensitive amplifier (PSA) with a pump laser whose

optical phase is locked to that of a randomly modulated signal by using

an optical phase - lock loop (OPLL).

3. This paper focused on SSB noise locking bandwidth. We report the first

experimental demonstration of millimeter - wave modulated optical

signal generation by an optical injection phase - lock loop.

4. This paper focused on Phase Noise analysis.


2


3/20


5. This paper will present an investigation into the phase detector of a 27

GHz phase - lock loop (PLL) clock multiplier using a 0.18 - m CMOS

process.

6. This paper focused SSB Noise density Locking range.

1.3 Organization of seminar report:-

This seminar report consists of Introduction, Literature survey, Review

of high frequency PLL, Comparison table, Conclusion.


3


4/20


Chapter 2

Literature Survey

2.1 Digital Phase - Locked Loops:-

The digital phase - locked loop, DPLL, is a circuit that is used frequently

in modern integrated circuit design. Consider the waveform and block diagram

of a communication system shown in Fig. 2.1 Digital data is loaded into the

shift register at the transmitting end. The data is shifted out sequentially to the

transmitter output driver. At the receiving end, where the data may be analog

(and, thus, without well - defined amplitudes) after passing through the

communication channel, the receiver amplifies and changes the data back into

digital logic levels. The next logical step in this sequence is to shift the data

back into a shift register at the receiver and process the received data. However,

the absence of a clock signal makes this difficult. The DPLL performs the

function of generating a clock signal which is locked or synchronized with the

incoming signal. The generated clock signal of the receiver clocks the shift

register and thus recovers the data. This application of a DPLL is often termed a

clock - recovery circuit or bit synchronization circuit.

Figure 2.1 Block diagram of a communication system using

A DPLL for the generation of a clock signal.

A more detailed picture of the incoming data and possible clock signals

out of the DPLL are shown in Fig. 2.2. The possible clock signals are labeled


4


5/20


XOR clock and PFD (phase frequency detector) clock, corresponding to the

type of phase detector (PD) used. For the XOR PD, the rising edge of the clock

occurs in the center of the data, while for the PFD, the resting edge occurs at the

beginning of the data. The phase of the clock signal is determined by the PD

used.

Figure 2.2 Data input to DPLL in lack and possible clock outputs using the

XOR phase detector and PFD.

A block diagram of a DPLL is shown in Fig. 2.3. The PD generates an

output signal proportional to the time difference between the Data in and the

divided down clock, dclock. This signal is filtered by a loop filter. The filtered

signal, V is connected to the input of a voltage - controlled oscillator (VCO).

Figure 2.3 Block diagram of a digital phase - locked loop.

2.2 Important Parameters:-

1. Lock Range - The lock range of the PLL is the range of loop frequency

about the central frequency for which the loop maintains lock.

Locking range is limited by phase comparison range.


5


6/20


2. Capture Range - The capture range is the range of input frequency for

which the initially unlocked loop will lock all an input signal. This is

always less than lock range.

2. Capture Range - The capture range is the range of input frequency for

which the initially unlocked loop will lock all an input signal. This is

always less than lock range.

3. jitter - In the most general sense, for clock - recovery and

synchronization circuits, can be defined as the amount of time the

regenerated clock varies once the loop is locked. Figure 2.4 shows the

idealized case when the clock doesn't jitter, while shows the actual

situation where the clock - rising edge moves in time (jitters). In these

figures, the oscilloscope is triggered by the rising edge of the data. In the

following discussion, we neglect power supply and oscillator noise, that

is, we assume that the oscillator frequency is an exact number that is

directly related to the VCO input voltage. In the section following this

one, we cover delay - locked loops and further discuss the limitations of

the VCO.

Figure 2.4 a) Idealized view of clock and data without Jitter and

b) with jitter.

4. Loop gain & Natural frequency - loop gain affects the phase errors

between the input signal and the VCO for a given frequency shift of


6


7/20


input signal. It also determines the lock range of the loop providing no

components of the loop go into limiting or saturation. This is because

the loop will remain in lock as long as phase errors e is less than +

900. The higher loop then, the further the input can change in frequency

before the 900 phase errors is reached.

5. Loop Bandwidth - The bandwidth of the loop is determined by the

filter components R1, R2 and C (in case of lag - lead filter), and the loop

gain. Since the loop gain is normally selected by the criteria as discussed

above, the filter components are used to select the bandwidth. The

selection of loop bandwidth may be governed by several things noise

bandwidth, modulation rates if the loop is to be used as an FM

demodulator, pull - in time and lock range.

Requirements that will have an effect on loop bandwidth:

i) Loop bandwidth must be as narrow as possible to minimize

output phase jitter due to external noise.

ii) The loop bandwidth should be made as large as possible to

minimize transient error due to signal modulation, output jitter

due to internal oscillator (VCO) noise, and to obtain best

tracking and capture or acquisition properties.

6. Noise - Since on of the main uses of PLL is to demodulate or track

signals in noise, it is helpful to look at how noise affects the operation of

the loop. Noise will show up in the input signal as both amplitude and

phase modulation. To obtain optimum performance, a limiter should be

used ahead of the phase detector. With the use of a limiter, amplitude

modulation of the input signal by noise is removed, and the noise

appears as phase modulation. The same result is obtained if the phase

detector itself is allowed tooperate in limiting. When designing the loop

filter components, enough bandwidth in the loop must be allowed for

instantaneous phase change due to input noise.


7


8/20


Chapter 3

Review of High Frequency PLL

In this session presents 7 papers that explore innovations in all - optical

and high frequency PLLs. A common theme in all high frequency PLLs is to

improve the locking range, gain, noise. These papers in this session address this

issue.

3.1)High-Performance Phase Locking of Wide Line width Semiconductor

Lasers by Combined Use of Optical Injection Locking and Optical Phase-

Lock Loop :

This paper focused on locking range, noise, line width. The requirement for

narrow linewidth lasers or short - loop propagation delay makes the realization

of optical phase - lock loops using semiconductor lasers difficult. Although

optical injection locking can provide low phase error variance for wide line

width lasers, the locking range is restricted by stability considerations.

Theoretical and experimental results for a system which combines both

techniques so as to overcome these limitations, the optical injection phase - lock

loop (OIPLL), are reported. Phase error variance values as low as 0.006 rad

(500 MHz bandwidth) and locking ranges exceeding 26 GHz were achieved in

homodyne OIPLL systems using DFB lasers of summed line width 36 MHz,

loop propagation delay of 15 ns and injection ratio less than - 30 dB. Phase

error variance values as low as 0.003 rad in bandwidth of 100 MHz, a mean

time to cycle slip of 3 x 1010 s and SSB noise density of - 94 dBc/Hz at 10 kHz

offset were obtained for the same lasers in an heterodyne OIPLL configuration

with loop propagation delay of 20 ns and injection ratio of 30 dB.[1]

3.2) In-Line Optical Phase-Sensitive Amplifier with Pump Light Source

Controlled by Optical Phase-Lock Loop: This paper focused on Gain,

OpticalPhase lock. This paper describes in-line optical phase sensitive

amplifier (PSA) with a pump laser whose optical phase is locked to that of a

randomly modulated signal by using an optical phase - lock loop (OPLL). The

OPLL is designed with the capability of optical phase locking at an arbitrary

relative phase. Experimental evaluation is presented of the OPLL employing a


8


9/20


newly developed external cavity semiconductor ring laser with a spectrum

linewidth of less than 20 kHz. Employing this pump laser with the OPLL in

conjunction with a 44 - km long nonlinear fiber Sagnac interferometer (NFSI)

yields optical phase-sensitive gain of up to11 dB, Arandomly modulated signal

is successfully amplified and confirmed offering a clear eye-opening[2].

3.3) Millimeter-Wave Modulated Optical Signal Generation with High

Spectral Purity and Wide-Locking Bandwidth Using a Fiber Integrated

Optical Injection Phase-Lock Loop :This paper focused on SSB noise

locking bandwidth. We report the first experimental demonstration of

millimeter - wave modulated optical signal generation by an optical injection

phase - lock loop. A 36 - GHz signal was generated by combining optical

sideband injection locking with optical phase - lock loop techniques for two

fibers - coupled DFB lasers. Single sideband noise spectral density of - 92

dBc/Hz at 10 kHz offset, and phase error variance lower than 0.005 rad2 in a

100 MHz bandwidth were measured. The locking bandwidth exceeded 30 GHz.

[3]

3.4) Discriminator-Aided Optical Phase-Lock Loop Incorporating a

Frequency Down-Conversion Module:This paper focused on Phase Noise

analysis. A new discriminator - aided optical phase - lock loop (OPLL)

incorporating a frequency down - conversion module to generate a low phase

noise, highly frequency - stable, and frequency - tunable microwave signal is

proposed and demonstrated. The inclusion of the frequency down - conversion

module allows the use of lower frequency components in the control circuits

with a reduced cost. In addition, the new design allows continuous frequency

tuning of the generated microwave signal. The down - conversion concept ispresented, along with a phase noise analysis detailing the contributions to the

phase noise from the reference sources. An OPLL based on the proposed

configuration is implemented. The phase noise performance, as well as the

frequency stability is experimentally studied. [4]

3.5) A 27 Ghz Phase-Lock Loop Phase Detector

This paper will present an investigation into the phase detector of a 27 GHz

phase - lock loop (PLL) clock multiplier using a 0.18 - m CMOS process.


9


10/20


The phase detector is one part of a multi faceted project involving the

development and verification of the various components composing the phase -

lock loop. A low multiplication factor has been selected that provides a benefit

in the multiplicative phase noisecontribution, requiring a high - speed

frequency divider and phase detector.

A study of the non - ideal performance (i.e.) non - 900 phase offset for a

0 V control voltage output in the phase detector) has been undertaken; the offset

may be lessened with an increase in the localoscillator switching core gate -

source voltage. Simulated and measured result for a Gilbert cell phasedetector

realized in the TSMC 0.18 m - CMOS process and operating at 6.75 GHz are

presented. [5]

3.6)High-Performance Heterodyne Optical Injection Phase-Lock Loop

Using Wide Line width Semiconductor Lasers :This paper focused SSB

Noise density Locking range. The requirements for narrow line width lasers or

short - loop propagation delay limit optical phase - lock reliability with

semiconductor lasers. Although optical injection locking can provide low -

phase - error variance, its locking range is limited by stability considerations.

The first experimental results for a heterodyne optical injection phase - lock

loop are reported. Phase - error variance as low as 0.003 rad2 in a bandwidth of

100 MHz, single - sideband (SSB) noise density of - 94 dBc / Hz at 10 - kHz

offset and mean time to cycle slip of 3 x 1010 s have been achieved using DFB

lasers of 36 - MHz summed line width, a loop propagation delay of 20 ns and an

injection ratio of - 30 Db[6].

3.7 ) A 3.5GHz Wideband ADPLL with Fractional Spur

Suppression Through TDC Dithering and Feed forward

Compensation :This paper focused jitters. The symbol synchronizer recoveries

the clock and after, with it, samples and retains the data. The objective is to

study the various synchronizers output jitter UIRMS (Unit Interval Root Mean

Squared as function of the input SNR (Single to Noise Ratio).[7]


10


11/20


Chapter 4

Comparison of High Frequency PLL

In this chapter we compare the different high frequency PLLs .

The work done by the author and work yet to be done is presented

in the tabular form as follows :

Table No. 4.1 Comparison of High Frequency PLLs with Different

Parameters.

Year of

publishing

Topic Author Work done Yet to be done

1) Feb. 99 High-Performance

Phase Locking of

Wide Line width

SemiconductorLasers by

Combined Use of

Optical

Injection Locking

and Optical Phase-

Lock Loop

A. C.

Bordonalli, C.

Walton, and

Alwyn J.Seeds,

Fellow, IEE

Describes optical

phase-lock loops

having:

1. Locking range2. Phase error

Variance very

low

3. Locking range

exceeds

4. Line width low

5. Low loop

propagation delay

6. Low injection

ratio

7. Low SSB noise

density

The amount of power

injected into the

Slave laser cavity

(injection ratios 40dB) to provide low

phase noise leads to

limitation in the stable

locking range of

Such systems.

2) April 99 In-Line Optical

Phase-Sensitive

Wataru

Imajuku and

This paper describes

an in-line optical

However, pump

leakage was


11


12/20


Amplifier with

Pump

Light Source

Controlled by

Optical Phase-

Lock Loop

Atsushi

Takada

phase sensitive

amplifier (PSA) with

a pump laser whose

optical phase is locked

to that of a randomly

modulatedsignal by

using an optical

phase-lock loop

(OPLL) Gain

Employing this pump

laser with the OPLL

in conjunction with a

4.4-km long nonlinear

fiber Signal

interferometer (NFSI)

yields optical phase-

sensitive gain of up to

11 dB.

considerable and

degraded the

extinction ratio of the

output signal.

3) June

2000

Millimeter-Wave

Modulated Optical

Signal

Generation with

High Spectral

Purity and Wide-

Locking

Bandwidth Using a

Fiber Integrated

Optical Injection

Phase-Lock Loop

,

L. A.

Johansson

and A. J.

Seeds

Report the first

experimental

demonstration of

millimeter-wave

modulated optical

signal generation by

an optical

injection phase-lock

loop SSB noise

density -92db at

10khZ offset Locking

bandwidth >30GHZ

Large locking range

Excellent locking

Loss of lock occurred

due to limitations of

the current tuning

range of

The slave laser and

changes in the

injection ratio, as the

slave laser output

power varied.


12


13/20


bandwidth Long term

stability

4) Nov 2006 Discriminator-

Aided Optical

Phase-Lock Loop

Incorporating a

Frequency Down-

Conversion

Module

Howard R.

Ride out, Joe

S. Seregelyi,

Stphane

Paquet, and

Jianping Yao,

Senior

Member,

IEEE

A new discriminator-

aided optical phase-

lock loop

(OPLL) incorporating

a frequency down-

conversion module

to generate a low

phase noise, highly

frequency-stable, and

frequency-tunable

microwave signal is

proposed and

demonstrated

The down-conversion

concept is presented,

along with a phasenoise analysis

detailing the

contributions to the

phase noise from

the reference sources

The histogram

plot of the stability

data an almost

Gaussian distribution

of the peak frequency

about the mean

During this period.

Further trials over

longer intervals are

required

to confirm this

distribution.

5) May

2006

A 27 Ghz Phase-

Lock Loop Phase

Detector

John P. Carr

Brian M.

Frank

This paper will

present an

investigation into the

phase detector of a 27

GHz phase-lock loop

(PLL) clock multiplier

using a 0.18m

CMOS process.

The majority of the

testing was carried out

using single-ended RF

and LO excitation

because of equipment

limitations.

It is possible to reduce

the zero voltage

crossing error by


13


14/20


increasing

the gate-source

voltage at the LO

switching core, at the

expense

of increased circuit

complexity and power

6) March

98

High-Performance

Heterodyne

Optical

Injection Phase-

Lock Loop Using

Wide Line width

Semiconductor

Lasers

C. Walton, A.

C. Bordonalli,

and A. J.

Seeds

Low phase error

variance

Locking range limited

by stability

considerations

SSB noise density

-94db/Hz The first

experimental results

for an heterodyne

optical injection

phase-lock loop arereported

Tracking capability of

the combined OIPLL

system is improved

Compared with the

equivalent OPLL and

OIL systems, as long

term fluctuations can

be compensated

electronically by the

OPLL path while fast

fluctuations can befollowed by the OIL

path.

7) Feb2010 A 3.5GHz

Wideband ADPLL

with Fractional

Spur

Suppression

Through TDC

Dithering and Feed

forward

Compensation

Colin Weltin-

Wu1,2,

Enrico

Temporiti3,

Daniele

Baldi3,

Marco

Cusmai2,

Francesco

Svelto2

We present a 3.5GHz

fractional-N ADPLL

with a 3.4MHz

bandwidth operating

from a 35MHz

reference. Using a

dithering algorithm

and

feed forward

compensation around

the TDC results in

spurious performance


14


15/20


better than -58dBc,

and in-band phase

noise of

-101dBc/Hz. The IC

with fully integrated

calibration logic

occupies 0.44mm2 in

65nm CMOS, and

consumes 8.7mW.

Low in phase noise

Low power supply

PLL range

2.8 GHz to 3.8 GHz

8]Feb2010 A 2.1-to-2.8GHz

All-Digital

Frequency

Synthesizer with a

Time-WindowedTDC

T. Tokairin,

NEC,

Kawasaki,

Japan

A 2.1-to-2.8GHz low-

power all-digital PLL

with a time-windowed

single-shot pulse-

controlling 2-stepTDC is presented. The

test-chip is

implemented in 90nm

CMOS and exhibits

in-band phase noise of

-105dBc/Hz with

500kHz loop-

bandwidth and out-of-

band noise of

-115dBc/Hz at 1MHz

offset. The chip draws

8.1mA from a 1.2V

supply

Low phase noise

Although there is no

spurious noise due to

modulator periodicity

of cycles, the

reference spur of40dBc spurs was

observed. This is

caused by insufficient

isolation between the

DCO and the digital

logic-gates driven by

the reference signal,

and can be

Improved in a re-

design.


15


16/20


Low power

consumption

In short, the DPLLperformance parameters are as follows:

Table No. 4.2 DPLL Performance Parameters

Parameter

s

Feb.99

[1]

April99

[2]

June2000

[3]

Nov2006

[4]

May2006

[5]

March98

[6]

Locking

Range

>26

GHz

NA >30 GHz NA NA >24GHz

Loop gain NA 11dB NA 3dB NA NA

Natural

Frequency

NA NA NA 11.2

GHz

6.75

GHz

NA

Loop

Bandwidth

36

MHz


17/20


digital logic-gates driven by the reference signal, and can be improved in a re-

design.

Table No. 4.3 DPLL Performance Parameters [7]


17


18/20


Table No. 4.4 DPLL Performance Parameters [8]

This table 4.4 describe the ADPLL Performance parameters.


18


19/20


Chapter 5

Conclusion

This review helps to study the Digital PLL. Noise, locking range, jitters

and delay are the parameters taking into consideration form the study of IEEE

papers and books. A common theme in all high frequency PLLs is to improve

the locking range, gain and noise. Future DPLLS will have much greater

performance as mention in Table no 4.1 and 4.3.


19


20/20


REFERENCES

1) Bordonalli, C. Walton, and Alwyn J. Seeds, Fellow, IEEE High-

Performance Phase Locking of Wide Linewidth Semiconductor Lasers by

Combined Use of Optical Injection Locking and Optical Phase-Lock Loop

Journal Of Lightwave Technology Vol. 17, No. 2, February 1999

2) Wataru Imajuku and Atsushi Takada "In-Line Optical Phase-Sensitive

Amplifier with Pump Light Source Controlled by Optical Phase-Lock Loop"

Journal Of Lightwave Technology, Vol. 17, No. 4, April 1999 637

3) L. A. Johansson and A. J. Seeds, Fellow, IEEE "Millimeter-Wave

Modulated Optical Signal Generation with High Spectral Purity and Wide-

Locking Bandwidth Using a Fiber-Integrated Optical Injection Phase-Lock

Loop" Ieee Photonics Technology Letters, Vol. 12, No. 6, June 2000.

4) Howard R. Rideout, Joe S. Seregelyi, Stphane Paquet, and Jianping

Yao, Senior Member, IEEE "Discriminator-Aided Optical Phase-Lock

Loop(Incorporating a Frequency Down-Conversion Module"

Ieee Photonics Technology Letters, Vol. 18, No. 22, November 15, 2006 5)

CMOS Circuit design, Layout, and Simulation

6) John P. Carr, Brian M. Frank, "A 27 Ghz Phase-Lock Loop Phase

Detector"IEEE Ccece/Ccgei, Ottawa, May 2006

7) Colin Weltin-Wu1, 2, Enrico Temporiti 3, Daniele Baldi 3, Marco

Cusmai 2, Francesco Svelto A 3.5 GHz Wideband ADPLL with Fractional

Spur Suppression . Through TDC Dithering and Feedforward Compensation

2010 IEEE International Solid State Circuits Conference.

8) Takashi Tokairin 1, Mitsuji Okada 2, Masaki Kitsunezuka 1, Tadashi

Maed 1,Muneo Fukaishi A 2.1 To -2.8 ghz All Digital Frequency

Synthesizer With A Time-Windowed TDC 2010 IEEE International Solid-

State Circuits Conference.

9) K.R. Botkar Integrated Circuits Khanna Publication,,Tenth Edition.

20

copy of seminar ii 2

Documents