coprocessor-1.ppt
TRANSCRIPT
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Multimicroprocessor systems
As we all know a single processor system has an upper limit of its
processing capability.
A system having two microprocessor will require only lesser time to
complete the task.
The study of a system, involving several connected microprocessors, usinga certain topology to further enhance the speed of operation is called
Multimicroprocessor Architecture.
Multimicroprocessor system consist of
CPU umeric !ata Processor " !P # Or / And
$nput % &utput processor " $&P #
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Numeric Data Processor :
$n(epen(ent Processing Unit.
Perform complicate( numeric calculation in comparatively less time.
)orks in coherence with the main processor.
Input / Output Processor :
*ake care of $%& activities of the system.
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Coprocessor
A computer processor use( to supplement the function of primary processor.
,irst seen on mainframe computers.
Accelerate the system performance.
&peration performe( -
,loating point arithmetic raphic / 0ignal processing. 0tring processing. ncryption
*hey are Unable to fetch the co(e from the memory so they work un(er thecontrol of main processor .
2oth microprocessor an( coprocessor can e3ecute their respectiveinstructions simultaneously an( concurrently.
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$ntel 56+57 CPU w % 56+58 Math Coprocessor
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Architecture of 8087
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Intel 8087
NumericProcessor.
Packe( in 0 pin ceramic DIP pac!a"e.
Available in # M$%: 5M;
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Architecture of 8087
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*wo ma=or sections-1# Control unit
'# umeric 3ecution unit
Control Unit -
Function :
It interface the coprocessor to the microprocessor
system data bus.
Monitors the instruction stream.
If the instruction is an ESape !coprocessor"
instruction, the coprocessor e#ecutes it$ if not the
microprocessor e#ecutes it.
It receives , decodes instructions, read and %rite
memory operands and e#ecutes the &'&( instruction.
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umeric 3ecution Unit"U#
Functions :
E#ecute all the numeric processor instructions.
It has & register !&' bit"stac) that holds the operands for arithmetic
instructions * the result.
Instruction either address data in specific stac) data register oruses push and pop mechanism to store and retrieve data.
+rogrammable shifter :
esponsible for shifting the operands during the e#ecution of
instruction li)e FM- and F/I0.
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Microco(e control unit -
It generates the control signals re1uired for the e#ecution ofinstruction.
The internal data bus is &2 bits %ide including 3& bit
fraction, 45 bit e#ponent and a sign bit.
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(tatus 'ord of 8087
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1# 2 ? busy bit Indicates the coprocessor is busy in e#ecuting a tas).
6" 78 ' !ondition code bits" Indicates the condition of the coprocessor.
7" T9+ ! Top8of8stac) !ST"" Indicates the current register addressed as the top8of8thestac) !ST". ormally register '.
2" ES error summary ;it is set if any unmas)ed error bit !+E,-E,9E,
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7# U ? Un(erflow rror Indicates a non =ero result that is too small to represent
%ith the current precision selected.
8# & ? &verflow rror Indicates a result is too large to be represented.
5#@ ? @ero rror
Indicates the divisor %as =ero %hile the dividend is a non8infinity or non =ero number.
># ! ? !enormali
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)ontrol *ord +e"ister of 8087
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Control register
,!C)? instruction which is use( to loa( a value into the
control register.
1# $C ? $nfinity Control
0elects either affine " allows positive an( negative infinity#or pro=ective "assumes infinity is unsigne(#
'# BC ? Boun(ing Control
!etermines the type of roun(ing.
6 6 roun( to nearest even.
61 roun( (own towar(s minus infinity.
16 roun( up towar(s plus infinity.
11 chop or truncate towar( @ero.
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+# PC ? Precision Control 0ets the precision of the result.
66 D 0ingle precision "short#
61 D Beserve(
16 D !ouble ? precision "long#
11 D 3ten(e( precision "temporary#
4# 3ception Masks !etermine whether the error in(icate( by the e3ception
affects the error bit in the status flag.
9# @ero !ivi(e
$f any non
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Tag Register
E *he ta" re"isterin(icates the contents of
each location in the coprocessor stack.
E *he tag in(icates whether a register is vali(F
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? a program views the tag register by storing the
coprocessor environment using ,0*G:
,0AG: or ,B0*&B
? each instruction stores the tag register along
with other coprocessor (ata
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0ignal !escription of 5658
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Pin Dia"ram of 8087
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'+
1# A!6 A!19 -
*hese are time multiple3e( a((ress % (ata lines.
ines carry a((ress (uring *1an( (ata (uring *'*+*w/*4
states.
'# A1>%07? A17%0+ -
*hese are time multiple3e( a((ress% status lines.
*hese function in a similar way to the correspon(ing pinsof 5657.
07:04 / 0+ are permanently high: while the 09 is
permanently low.
+# 2; % 08 -
!uring t1 the 2; % 08 pin is use( to enable (ata on to the
higher byte of the 5657 (ata bus.
!uring *' :*+: *w an( *4 this is a status line 08.
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4# Hs1 : Hs6 -
Hs1 : Hs6 are queue status input signals.
*hese enable 5658 to keep track of the instruction prefetch
queue status of the CPU: to maintain synchronism with it.
Hs1 Hs6 Hueue 0tatus
6 6 o operation.
6 1 ,irst byte of opco(e from queue
1 6 mpty Hueue
1 1 0ubsequent byte from queue.
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9# $*
Use( to in(icate that an unmaske( e3ception has been
receive( (uring e3ecution. *his is usually han(le( by 5'9>A.
7# 2U0I
$t will be set when 5658 is busy with the e3ecution of anallotte( instruction.
8# BA!I
Use( to inform the coprocessor that the a((ress (evice willcomplete the (ata transfer from its si(e an( the bus is likely to befree for the ne3t bus cycle.
Usually this is synchroni
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5# B0* Use( to aban(on the internal activities of the coprocessor
an( prepare it for further e3ecution.
># CJ
$t provi(e the basic timing for the processor operation.
16# GCC
A K9G supply
11# ! A return line for the power supply.
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s' 01 06 Hueue status
6 L L unuse(
1 6 6 Unuse(
1 6 1 Memory rea(
1 1 6 Memory write
1 1 1 passive
,- (-(,and (0*hese can be either be 5658 (riven "output# or
e3ternally (riven "input# by the CPU
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1+# BH % *6*he request % grant pin is use( to gain control of the bus from
the host "5657% 5655# for operan( transfer.
An active low pulse of one clock (uration is generate( by
5658 for the host to inform it that it wants to gain control of
the local bus either for itself or for other coprocessor
connecte( to BH% *1 pin of 5658.
*he 5658 waits for the grant pulse from the host.
)hen it is receive(: it either initiates a bus cycle if the
request is for itself or else: it passes the grant pulse toB%*1: if the request is for the other coprocessor.
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14# BH % *12i(irectionalpin
Use( by other bus masters to convey their nee( of the local
bus access to 5658.
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$nterconnections of 5658 with 5657% 5655
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$nterconnection of 5658 with CPU -
&'&( can be connected %ith &'&3 ?&'4&& only in their ma#imum
mode of operation, ie only %hen the M? M# pin of +- isgrounded.
In ma#imum mode all the control signals are derived using aseparate chip )no%n as a bus controller.
The busy pinof &'&( is connected %ith the TEST pin of the+-.
In &'&3?&'&& the @S' *@S4 lines may be directly connected tothe corresponding pins.
&65> 8 +rogrammable interrupt controller
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In case of &'&3 ? &'&& based system the BH% *6 of &'&( may be
connected to BH % *1 of &'&3? &'&&.
The cloc) pinof &'&( may be connected %ith the +- &'&3? &'&&
cloc) input.
The interrupt outputof &'&( is routed to &'&3?&'&& via a
programmable interrupt controller.
The pinsA/' A/45 ,ESET , A4>?S3 8 A43?S7, ;BE ? S( are
connected to the corresponding pin of &'&3?&'&&.
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$nstruction set of 5658
*he e3ecution of 5658 instruction is transparent to the
programmer.
*he instructions are fetche( by 5657 but are e3ecute( by
5658.
)henever the 5657 comes across 5658 instruction: it
e3ecutes the 0CAP instruction co(e to pass over the
instruction opco(e an( control of the local bus to 5658.
After e3ecution the result is referre( back.
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)ate"ori%ation of Instruction set
1. !ata transfer $nstructions.
'. Arithmetic $nstructions
+. Comparison $nstructions4. *ranscen(ental &perations
9. Constant &perations.
7. Coprocessor Control &perations
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1# !ata *ransfer $nstruction
!epen(ing on the (ata type han(le( these are further
groupe( intoThree - ,loating point !ata *ransfer
$nteger !ata *ransfer
2C! !ata *ransfer
,loating Point !ata *ransfer
1. ,! "oa( real to top of 0tack#
*his instruction loa(s a real operan( to the top of stack of
the 56 bit register.
,! 0* "8# F 0tack top Beg 8N
,! MM F 0tack *opMMN
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'# ,0* "0tore *op of the &peran( # *his instruction stores current content of the top of
stack register to the specifie( operan(.
,0* 0*"8# F 0tack top 0* "8# N
,0* MM F stack *opMMN
+# ,LC; "e3change with *op of 0tack# *his instruction e3changes the content of the top of
stack with the specifie( operan( register.
,LC; 0* "7# F stack top0* "7#
$nteger (ata transfer $nstruction -
1# ,$! "oa( integer to stack top# *his instruction loa(s the specifie( integer (ata
operan( to the top of stack.
,$! 0*"9# F stack *op0* "9#
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'# ,$0*%,$0*P
*he instruction work in e3act similar manner as ,0*%
,0*P e3cept the fact that the operan( are integer
operan(.
2C! !ata *ransfer $nstructions - ,2! / ,20*P
2oth work in an e3actly similar manner as ,! an( ,0*P e3ceptfor the operan( type 2C!
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Arithmetic $nstructions
1. ,A!!
'. ,0U2
+. MU4. ,!$G
9. ,0HB*
7. ,A20
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E ,in(s the suare rootof the top of thestack an( leaves the resultant square
root at the top of the stack.
? an invali( error occurs for the squareroot of a negative number
E *he $ bit of the status register shoul( be
teste( when an invali( result can occur.? test $ by loa(ing the status register to AL with
,0*0) AL: followe( by *0* AL:1 to test the bit
1(2+3
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46
E A((s the contents of 0*"1# "interprete( asan integer# to the e3ponent at the top of the
stack.
E 1()A45multiplies or (ivi(es rapi(ly bypowers of two.
? value in 0*"1# must be between '?19an( 'K19
1()A45
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E Performs modulo di6isionof 0* by 0*"1#.
E *he resultant remain(er is foun( in the top
of the stack an( has the same sign as the
original (ivi(en(.? a mo(ulo (ivision results in a remain(er
without a quotient
E ,PBM is supporte( for 5657 / 56'58? ,PBM1 shoul( be use( in newer coprocessors
1P+5M/1P+5M,
A ith ti R l t d O ti
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E Decomposesthe number at the top of the
stack into separate parts representing value
of the unbiase( e3ponent an( significan(.
E *he e3tracte( significan( is foun( at the top
of the stack an( the unbiase( e3ponent at
0*"1#.
? often use( to convert a floatingpoint to a form
that can be printe( as a mi3e( number
Arithmetic-Related Operations
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4+
E +oundsthe top of the stack to an integer.
1+NDIN3
1A(
E )han"es the si"nof the top of the stack topositive.
1)$(E )han"es the si"nfrom positive to negative
or negative to positive.
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3eststhe contents of the top of the stack against a
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*ranscen(ental $nstructions
*he operan( usually are 0*"6# an( 0*"1# or only 0*"6#
,P*A -
$nstruction calculates the tangent of an angle O&: where O&: mustbe in range from 6QR O& Q >66 S 0*%0*"1# T
*he value of O& must be store( at the stack top.
,PA*A -
$nstruction calculates the inverse tangent *he result is store( on the top of the stack.
*he content of 0* an( 0*"1# shoul( follow the inequality.
6QR0*"1# Q 0*Q infinity
,'LM$ - $nstruction calculates the e3pression "'3 1#
Galue of 3 is store( at the top of the stack.
Besult is store( back at the top of the stack.
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,I'L
$t calculate 0*"1# og' " 0*#
Besult is store( back at the top of stack.
0* must be in the range of 6 to Kinfinity.
0*"1# must be in the range of infinity toKinfinity.
,I'LP1
$t calculate 0*"1# log' "0*#K1 N
Besult is store( back on the stack top.
V0*V must lie between 6 an( "1 '1%' %'#.
Galue of 0*"1# must lie between?infinity an( K infinity
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Comparison $nstruction
All the comparison instructions compare the operan(s an( mo(ify the
con(ition co(e flags
Comparison C+ C6
0tack *op D 0ource
6 6
0tack *op Q 0ource 6 1
0tack *op R 0ource
1 6
ot Comparable 1 1
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1. ,C&M *he content of the top of stack is compare( either with the
content of a memory location or with the content of another
stack register.
'. ,$0* $nstruction test if the content of the stack top is @ero.
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Constant Beturning $nstruction
1. ,!@ oa( K6.6 to stack top
'. ,!P$ oa( pi"+.14# to stack top
+. ,!' oa( the constant og16 ' to the stack pointer.
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Coprocessor Control $nstruction
$. ,$$*$$. ,$
$$$. ,!$0$
$G. ,!C)G. ,0*0)
G$. ,CL
G$$. ,,BG$$$. ,&P
$L. ,)A$*