controlling substrate currents in junction isolated ics

1090 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 8, AUGUST 1991

Controlling Substrate Currents in Junction-Isolated ICs

Robert J. Widlar

V + Abstract -Certain bias conditions can result in sizable hole IF

and electron currents in the substrate of a junction-isolated IC. A v - These currents can cause excessive current flow, disrupt circuit operation, or even trigger parasitic SCRs across the supplies. Methods of optimizing layout to control substrate currents and their effects are discussed here. It is shown that these currents are strongly influenced by the properties of the die-attach interface. Fault conditions that can generate destructive hole and electron-current densities in the substrate are described; and IC clamp diodes, often required to control these fault conditions, are analyzed. An example gives an appreciation of what must be considered in the design of a practical IC along with the results that might he expected.

Fig. 1. When one tub is forward biased with respect to the substrate, electrons are injected into the Substrate and diffuse to adjacent reverse- biased tubs, where they are collected.

I . INTRODUCTION H E LATERAL p-n-p pass transistors in low-dropout T regulators [l] can cause troublesome hole currents in

the substrate with normal operation [2]. This is also the case when substrate p-n-p transistors [21 are used. Power switches using DMOS transistors can routinely run with outputs driven beyond the supplies [3]; this results in both hole and electron substrate currents. The latter is also true for a class-B amplifier that is subject to an inductive overload [4].

Substrate currents can cause a variety of difficulties ranging from improper operation to catastrophic failure. In many cases, it is not practical to eliminate them, and they must somehow be accommodated.

To this end, the effects of substrate currents are characterized and techniques are developed for avoiding problems. A design example is provided with a power op amp [4] that was redesigned to eliminate external diodes required to prevent failures with inductive overloads.

11. SUBSTRATE CURRENTS Electrons are injected into the substrate when an n-type

tub is forward biased into the p-type substrate. These electrons diffuse to the backside contact, recombine in the substrate, or diffuse laterally to be collected by other tubs that are reverse biased. The relevant structure is sectioned in Fig. 1.

Holes recombining with electrons injected into the substrate must be supplied from either topside contacts to

Manuscript received October 17, 1990; revised March 20, 1991. This work was performed under contract to National Semiconductor Corpo- ration, Santa Clara, CA.

The author, deceased, was an independent consultant. IEEE Log Number 9100624.

i

L e p l e t ion p - substrate

Fig. 2. When a p diffusion within a tub is forward biased, holes penetrate the subcollector and are swept across the depletion, raising substrate voltage above that at the backside contact (V- ). Should adjacent tubs become forward biased, a p-n-p-n structure is activated.

the isolation walls or the backside contact to the substrate at the die-attach interface. Minimizing the supply of holes will limit the electron concentration in the substrate and the lateral transfer of electrons to other tubs.

Holes are transported to the substrate when an isolated p region is forward biased into a tub that, in turn, is reverse biased with respect to the substrate. The structure is illustrated in Fig. 2. Although the n t subcollector and sinker inhibit the transport of holes, a fraction will penetrate these regions and be swept across the depletion zone into the substrate.

This hole current will cause the substrate potential to rise locally above the substrate bias voltage at the backside contact ( V - ). This can cause tubs that are biased at a potential near V- to become forward biased and inject electrons into the substrate. Should this happen, the resulting p-n-p-n structure could cause current localiza- tion with destructive current densities.

0018-92~0/91/08O~-IO90$O1.O0 01991 IEEE

WIDLAR: CONTROLLING SUBSTRATE CURRENTS IN JUNCTION-ISOLATED ICs 109 1

TJ = 25C

/-

20

,-. N

E 10 2 c P o n + z

U 3 -10

-20 1 I I I I -4 -2 0 2 4

VOLTAGE (V)

Fig. 3. Representative characteristics of the diode formed between an ohmic contact on top of a p-type substrate and the metal case to which the substrate is attached. Voltage reference is the metal case.

0 2 4 FORWARD VOLTAGE (V)

Fig. 4. Forward characteristics of tub-substrate diode when electron- recombination current is supplied only by holes generated in the Schottky barrier.

111. DIE-ATTACH INTERFACE

The silicon-metal contact established at the die-attach interface is not necessarily ohmic. Older IC wafers that were neither backlapped nor masked against the diffusion of impurities into the backside had a p-n junction located within a few micrometers of the back surface where the n+-emitter diffusion predominated.

Backlapped wafers with p-type substrates in the 5-15- R.cm range appear to form a Schottky junction at the die-attach interface. This has been observed with both gold-eutectic and soft-solder die attach.

Properties of the Schottky barrier can be inferred from the characteristics of the diode formed between a p + contact on the top of a p-type substrate and the metal case to which the substrate is attached. The results in Fig. 3 are representative of those obtained with 250-pm-thick, 6-Q .cm substrates. Forward dynamic resistance is about what would be expected from an ohmic (noninjecting) contact. Reverse dynamic resistance is several times the forward.

The forward characteristic of a tub-substrate diode, where substrate current is supplied solely through the die-attach interface (isolation wall floating), is shown in Fig. 4. The high dynamic resistance indicates that electron concentration in the substrate is limited by hole generation at the reverse-biased Schottky barrier which must

400

- N

L

c P 200

a -

0 I-

w U 3

0 0 1 2

FORWARD VOLTAGE (V)

Fig. 5. At a transition temperature above 150C, the conductance of the tub-isolation diode rises sharply as the Schottky barrier deteriorates.

supply electron-recombination losses. The forward drop is mainly across this barrier.

The reverse blocking characteristics of the interface barrier are observed to deteriorate at elevated temperatures somewhat above 150C. The forward conductance of the tub-substrate diode increases, as indicated by Fig. 5. This phenomenon is of limited practical interest because the Schottky barrier is at the temperature of the IC package, which is generally very much lower than the 200C peak temperatures allowed at the top surface of the die.

Electron injection near the die-attach interface has been known to cause SCR latching problems, especially with vertical p-n-p transistors. The effect is aggravated by increased current density and elevated temperatures.

Vertical p-n-ps manufactured with backlapped 5-15- R .cm p-type substrates showed no tendency to latch, even at current densities ten times higher than required to produce latch in identical transistors from nonback- lapped wafers.

Parasitic p-n-ps forming SCRs with the substrate are a recognized failure mode in ICs. Failures were reexam- ined for several types of power devices collected over a five-year period. With backlapped wafers, it was found that the SCR was not formed because of electron injection at the die-attach interface. Instead, the SCR was formed between the parasitic p-n-p and an adjacent tub biased near V, as illustrated in Fig. 2.

Attempts were made to measure backside injection using parasitic p-n-ps and by forward biasing the isolation wall of a tub into the backside contact while measur- ing electron drift back to the reverse-biased tub above. These methods were imprecise, but the backside injection was clearly insufficient to cause the h,, of a p-n-p to regenerate. Biasing an isolation wall 20 V above the backside contact gave an estimated 100-A/cm2 hole-current density for which an electron drift current of less than 5 A/cm2 reached the tub. It was not proven that this current was generated at the Schottky barrier.

IV. LATERAL EFFECTS

When a tub is forward biased into the substrate, electrons are injected. The electrons diffuse laterally and are

I 09 2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 8, AUGUST 1991

1

- F - U

0

z

p 0.1 2 Q 2 0 0 1 - a

0 001

\ \

0 1 2 DISTANCE RATIO (S i t )

Fig. 6. Lateral diffusion factor as a function of normalized distance between fonvard- and reverse-biased tubs. Two-dimensional current transfer is determined using (1).

collected by nearby tubs that are reverse biased. If the current in the isolation wall is presumed to be zero, two large tubs with dimensions much greater than the substrate thickness t will have a lateral transfer current I , given by

I , = ~ l t J , (1)

where I is the length of their common boundary, J , is the substrate current density in the absence of adjacent tubs (as given in Fig. 41, and 77 is a factor relating to tub separation s and electron diffusion length.

The situation was modeled using Teledeltos resistance paper. Conductive paint provided equipotential surfaces that represented the subcollector of the injecting tub separated by s from the depletion-zone edge of the collecting tub. The backside contact was modeled as an equipotential surface at a distance t below the other tubs. When the backside contact and the collecting tubs are of the same potential, the voltage gradient on the resistance paper represents the electron-diffusion gradient. Currents flowing in the various electrodes represent the diffusion currents.

Electron concentration can be assumed to be zero at the tub depletion. The same is true for the backside contact because of the Schottky barrier. Thus, the model is valid except that electron-recombination losses are not accounted for. If it is also assumed that the electron-diffusion length is large in comparison to the substrate thickness, the solutions for 77 plotted in Fig. 6 apply. In Fig. 6 it is assumed that the tubs are isolated individually. The region between isolations is either floating n - (un- guarded) or n + connected to V - (guarded) and the isolation walls are not hardwired to V-. The conse- quences of finite diffusion length are discussed in the Appendix.

When the p + isolation wall separating tubs is hardwired to V-, the current transfer is increased and can be measured. A 40-V linear process as in [2] with a down-dif- fused isolation having an acceptor concentration near 10 cmP3 is considered. Adjacent tubs with subcollectors separated by 50 pm will have a lateral transfer current approximately equal to the current flowing out of the

- 9 2 Q i

i L 0 a

1 0

0 8

06

0 4

0 2

-2 -1 0 1 2

DISTANCE RATIO (SI[)

(a)

1 0

0 8

0.6

0 4

0 2

0 -2 -1 0 1 2

DISTANCE RATIO (sit)

(b)

Fig. 7. Normalized substrate voltage rise on the surface as a function of normalized distance from edge of depletion transferring holes into substrate. (a) Isolation wall floating. (b) Isolation wall at V-.

common isolation wall in addition to the current pre- dicted by (1). If the tub size is not too great, this trans- lates into an h,, near unity for the lateral n-p-n formed by the tubs and substrate. This current gain falls off for current levels greater than 4 A/cm (10 mA/miI) of contacted mutual isolation.

If a third tub connected to V- separates two tubs where the isolation walls are hardwired to V-, current transfer between them is reduced [5]. For example, with 100 pm between the walls of the third tub, the lateral transfer current between the outside tubs will be roughly 0.04 times the current flowing into the proximate isolation wall of the injecting tub.

When a p-region within a tub is forward biased into the tub as shown in Fig. 2, holes will be transported through and around the subcollector to be collected by the substrate. The resulting substrate current will raise the substrate voltage above V-. Two-dimensional solutions for substrate voltage near the surface in the vicinity of such a tub are presented in Fig. 7. Assumptions made are that the current density .ID is constant in a planar depletion zone between subcollector and substrate, the current density in the substrate is sufficiently low to avoid velocity limiting [61, the injection of electrons at the backside contact is negligible, and the tub is biased at a voltage greater than the peak substrate voltage. The results in Fig. 7(a) ignore the effects of isolation walls while those in Fig. 703) presume that the isolation wall at the periphery

WIDLAR: CONTROLLING SUBSTRATE CURRENTS IN JUNCTION-ISOLATED ICs 1 01) 3

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20

5 - 2 5 9 O k 2 -20 3

-40

-60 0 5 10 15 20 25

6

4 - 5 L

+ -2 i?

3

- A

-6

V

Vour

TIME (ms)

Fig. 8. When safe-area protection activates with an inductive load, continuing load current causes the output to swing beyond supplies. Clamps are required to limit voltage.

Fig. 9. Partial schematic of an output stage for a power op amp. A substrate n-p-n, Q3, insures that Q , is turned off with VouT < I/-.

of the conducting tub is connected to V-. The voltage under the conducting tub is given for s / t < 0.

When the dimensions of the conducting tub are large in comparison to the substrate thickness t , the peak voltage rise under the tub is

V , = p t J ,

where p is the substrate resistivity. Depletion-zone current densities exceeding 50 A/cm2 are not unheard of in practical ICs. Worst case, the peak substrate voltage rise could be in the tens of volts. The data in Fig. 7 indicate that tubs clamped within a few volts of V - should be located at some distance from the source of substrate current even when the isolation walls are connected to v-.

Should the substrate voltage rise be so great that the conducting tub is no longer reverse biased (quasi-satura- tion of the parasitic p-n-p), the results in Fig. 7 are no longer valid (the lateral voltage rise is increased).

The discussion above indicates that contacting the isolation walls to V- significantly increases lateral effects with electron currents in the substrate while reducing them with hole currents. Further, while a lateral collec- tion tub connected to I/- (guard) can suppress electron diffusion between tubs, it can also result in a p-n-p-n structure being activated should there be sufficient hole currents in the substrate. That which mitigates one problem can aggravate another.

V. CLAMPING INDUCTIVE OVERLOADS Fig. 8 shows the output waveform of an op amp that

has an inductive overload. Inductor current continues to flow even though the output transistor cannot handle it, because of the power limiting. Consequently, the output must be clamped to the supplies to limit the voltage across the transistors. An output stage with clamp diodes is shown in Fig. 9.

An internal clamp diode for V,,, < V- can be formed simply by connecting the isolation wall of one output transistor (Q2 in Fig. 9) to V-. This can be augmented by

connecting p + diffusions within the output tub to I/-. The challenge lies in obtaining a low forward voltage drop and controlling lateral diffusion of electrons in the substrate.

In practical designs, diode current density can be well in excess of 10 kA/cm2. At such high current densities, significant conduction is restricted to those regions where p + diffusions contacted to V - metal abut n t diffusions contacted to output metal. Nonohmic voltage drop across the diode, measured internally, could be above 1.5 V. Drops in metallization, bond wires, and package could exceed 1 V. A total voltage drop above 3 V at high temperatures would not be out of the question. As the output swings below V-, internal tubs associated with the output or the base of Q , can become forward biased. Internal junction voltages are at a minimum because of heating in power limit. Forward-biased tubs can override power limit and cause conduction in Q , to increase to destructive levels.

A substrate n-p-n can be used to insure positive shutdown for Q, even with a clamp voltage greater then 2 V. This n-p-n is represented by Q3 in Fig. 9. The emitter of Q3 is the collector tub of Q2; the collector is an adjacent tub with emitter, sinker, and subcollector diffusions; the base is the substrate and isolation, with base contact being made to the isolation wall common to the emitter and collector tubs.

Monolithic diodes with high breakdown voltage can be fabricated to clamp the output to V+. The structure is shown in Fig. 2. It is important to block all diffusion paths between the parasitic p-n-p emitter and the depletion zone with heavily doped subcollector and sinker diffusions to control substrate current. A further reduction in substrate current can be obtained by reducing the injection efficiency of the parasitic p-n-p emitter. This can be done by diffusing n t within the p region and shorting the two together [7]. This structure can be viewed as the collector-base junction of an n-p-n where the base and emitter are shorted together.

The source-drain junction of an n-channel D-MOS transistor is fabricated in this manner. The devices are self-protecting in that they will clamp the voltage at a diode drop should the source try to rise above the drain.

1094 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 8, AUGUST 1991

With the IC version, substrate currents must be kept in hand [3].

A bipolar transistor will also serve as a clamp diode. If no external clamp diode is used for VouT > V+, Q, in Fig. 9 will break down in the reverse mode (BVEc0) and limit the output voltage rise above V+. Supplying the p-n-p emitter current through the n-p-n emitter-base junction in breakdown is effective in spoiling the emitter efficiency of the parasitic p-n-p. Disadvantages of the BV,,, clamp are relatively high clamp voltage ( > 7 VI and degradation of power transistor h,, for extended operation with the emitter-base junction in reverse breakdown [81.

The clamp voltage of a bipolar transistor can be reduced to a diode drop simply by putting a p diffusion connected to the output in the collector region of Q,. This works to a point. A situation can arise where the clamp is inadequate to handle large transients, but the forward voltage drop is low enough that an external general-purpose power diode cannot shunt the fault current around it.

A brief analysis of the V,,, > V+ clamp diode is given in the Appendix. It is shown why design techniques that can drastically reduce substrate currents become ineffec- tive at high current densities.

VI. DESIGN EXAMPLE An existing design for a power op amp [4] was modified

to reduce stress with inductive overloads. The IC is rated to deliver & 35 V at 10 A. Short-circuit current is 15 A. Power transistor tub size was 2.7 mmX 1.2 mm. The two power transistor tubs were separated by 300 p m along a 2.7-mm common boundary; the region between tubs was floating n- material. Detailed drawings and micropho- tographs of the composite transistor structure are avail- able in [4]. Only tub size, edge lengths, and boundary separations of the new design are relevant here.

The VoUT < V - clamp had an effective length of 2 mm (n+ contacted to V,,, separated by 50 p m from p + contacted to V - ) , This clamp was part of the tub of Q , along the edge remote from the common boundary with Q,. The layout gave relatively uniform conduction in the power array metalization, so ohmic drops in the metal were reduced. The forward characteristics of the diode are plotted in Fig. 10(a).

The isolation wall at the common boundary was not entirely floating because there were V- contacts to the isolation wall at a distance comparable to a diffusion length from the tub of Q2. These contacts were necessary to control substrate voltage rise with VoUT > V+. The cross-supply current that occurs with VoUT < V- is given in Fig. l o b ) . The increase in positive supply current is about 0.01 Z,,,.

Using the results of Fig. 10, a 15-A inductive overload with V,,, < V- will dissipate 30 W in the clamp diode and, with k40-V supplies, 12 W along the edge of Q , facing Q,. This severe case is within continuous power capabilities with a case temperature of 125C [41.

3. 1 Tc = 125C Vs = k40V

toN= 1ms L 1 1 1 2 z 5 9 4 4 ,' 0

0 0 5 10 15

CLAMP CURRENT (A)

(a)

0 3 - I 9 TC = 125OC

W n:

0

+ Vs = +40V t O N = 1ms

5 0.2 3 a

0 0 1 2 - m 2

0 5 10 15 CLAMP CURRENT (A)

(b)

Fig. 10. Characteristics of the V,,, < V - clamp at 125C. (a) Voltage drop. (b) Excess positive supply current from laterally diffusing electrons.

With V,,, > I/+, Q, was allowed to clamp in reverse breakdown. The characteristics of the clamp are given in Fig. 11. As expected, the clamp voltage is high. Substrate current is high, but that would be expected from the analysis in the Appendix. Current density is the problem. The entire power transistor is being used for the clamp, so significant reduction in substrate current would require a substantial increase in die area.

The power transistor has 540 emitters sized 50 p m X 20 p m distributed over an area of 0.03 cm2 and individually ballasted with an 8 0 4 polysilicon-film resistor. From Fig. 1l(b), this gives a substrate current density of 75 A/cm2 with a 15-A inductive overload (the 150 A/cm2 at the subcollector in Fig. 13 converts to 75 A/cm2 in the substrate because of lateral spreading). From (21, worst- case substrate voltage rise could exceed 40 V.

The V,,, > V+ clamp is of limited usefulness because of high dissipation (because the current is distributed evenly throughout the power transistor, normal peak- power ratings apply). In addition, the high clamp voltage could fail to protect the power transistor ( Q , in Fig. 9) when the IC is operating at maximum rated voltage. Within these limitations, results show that lateral effects of substrate voltage rise can be kept under control with proper layout. No latch-up tendencies have been observed, even at case temperatures of 150C. Degradation of h,, with clamp operation proved unimportant at the current densities involved. This type of operation for

WIDLAR: CONTROLLING SUBSTRATE CUKKENTS IN JUNCTION-ISOLATED ICs

Tc = 125C - d + Vs = +40V U foN= I m s w

15 I TC = 125C V, = i 4 0 V -

L toN= lms

5

= 5 4

; 10 > n.

0

0 0 5 10 15

CLAMP CURRENT (A)

( a )

high-voltage power switches has received some atten- tion [9].

As a final detail, positive output-stage shutdown was provided should the output go beyond either supply. With V,,, < V-, positive shutdown of Q, in Fig. 9 does not occur until Q3 has substantial conduction. Internal tubs can become forward biased before this happens. To avoid problems, auxiliary circuitry was provided to turn off Q, before any tubs can become forward biased as V,,, drops below V-. Similarly, Q2 is turned off when VoUT rises a diode drop above V+. Without some form of guaranteed, fast shutdown, the IC can be subject to obscure or transitory power-limit failures that are difficult to locate or characterize, especially when they cannot be made to recur because of device destruction. One such flaw, observed on a power op-amp design, was that output current could become uncontrolled if a supply lead was opened, even though the device was otherwise protected.

VII. CONCLUSIONS Substrate currents are strongly influenced by conditions

at the die-attach interface. Backlapped wafers with a p-type substrate resistivity of 5-15 R.cm exhibit a Schottky barrier at the interface with both gold-eutectic and soft-solder die attachment. This barrier has been characterized with sufficient accuracy to establish an upper limit for deleterious effects.

1095

The results of a simplified two-dimensional analysis describing lateral effects were reported. This, along with some empirical data, provides some appreciation of the magnitude of difficulties that can arise from substrate currents.

A design example that accommodates both hole and electron currents in the substrate was presented. Mea- sured results demonstrate that the effects of those currents can be controlled in spite of conflicting design requirements.

APPENDIX

In a two-dimensional system, when an n tub is forward biased into a p substrate, electrons will diffuse to the die-attach interface. If there is a Schottky barrier at the interface, total electron concentration in the substrate is limited by the hole-generation current in the barrier depletion that supplies recombination losses in the substrate.

It is assumed that the concentration of electrons and neutralizing holes in the substrate is much greater than the acceptor concentration ( n E p >> NAs). Further, it is assumed that the carrier concentration is at a minimum as the depletion zone is approached.

High-level diffusion is governed by the field-aided diffusion equations [10]-[12]

dn J,, - bJ, dx 2kTp, ( 3 ) _=-

and

(4)

where J , is the electron current, J , is the hole current supplying recombination losses, and b = p, /p , . The variation of J , and J , with distance from the tub to the depletion is sketched in Fig. 12.

The electron concentration gradient is also sketched in Fig. 12 for J, 0. This gradient was assumed in obtaining the solution for 7 in Fig. 6. When a hole current is required to supply appreciable recombination losses, the second curve applies for the same total current. From (3 ) and (4), the diffusion gradient is reduced for x > 0 and the electric field increases to support simultaneous hole and electron conduction. With the higher field, an equal current is supported with lower carrier concentration in the substrate. With n = NAs or n -K NAs, a similar situation applies. For a given current density, minority-carrier concentration in the substrate is reduced in the presence of recombination losses.

Under these conditions, 77 will be reduced, both because of reduced concentration under the injecting tub and because of recombination losses in diffusing to the collecting tub. Electron-diffusion length in the substrate is roughly equal to the substrate thickness (250 pm). This significantly reduces the value of r ] . Nonetheless, the results in Fig. 6 can be used to establish an upper limit for lateral diffusion.

J

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 2h, NO. 8, AUGUST

T 3

- 0 7 - Z

F < 2 U F Z w o Z

Q

8 I- o U 1 w

G, =~SXIO"V.S/C~~ J =670A/cm Jp =330A/cm2

SUBCOLLECTOR

1991

L'(I 6 0 I o 2 4 6 8 10

DISTANCE TO SUBCOLLECTOR (pm)

Fig. 13. Plasma concentration in the n - collector between the p base and n subcollector of the diode in Fig. 2. Effect of lowering Gummel number of p region is shown.

Combining (7), (8) gives, for the subcollector,

0 (9) kTP,: J,=-.

0 G,

Fig. 12. Sketches of current densities and carrier concentrations for holes and electrons as a function of distance from the injecting tub ( x = 0) to the die-attach interface ( x = xL) ) .

The characteristics of the VoUT > V c clamp diode can be determined from ( 3 ) and (4), when some properties of the base and subcollector are taken into account.

When a plasma of concentration p o faces an abrupt junction with a region having a donor concentration N,, >> p o , the hole concentration P , ~ in the n region near the interface can be obtained from

The electric field that keeps the electrons in the n region out of the plasma, keeps holes in the plasma out of the n region.

These holes will diffuse through the n region to a contact or depletion zone, giving a hole current of

Ps J p = k T p -. p' ws

where W, is the thickness of the n region. Combining ( 5 ) and (6):

The Gummel number is defined as [6]

( 7 )

Similarly, for the base

kTni J , = - .

GiJ

The Gummel number of a bipolar transistor emitter can be determined experimentally. The measured value takes into account bandgap narrowing and recombination losses, factors not considered here.

In the diode of Fig. 2, J , would be the electron current flowing from the p-n-p emitter to the subcollector (base); and J,, would be the hole current flowing from the p-n-p emitter through the subcollector (base) into the substrate (collector), assuming negligible recombination in the subcollector.

The Gummel number for the p-n-p emitter has been determined from transistor measurements, so no is obtained from (lo), Po is then obtained from (31, and G,, is obtained from (9).

The result was G, = 6 X 10"V.s/cm4. This is near the limit of what has been obtained for the emitter of an n-p-n transistor 10I2V.s/cm4, indicating that a major reduction in substrate current is not to be expected from increased subcollector doping.

Fig. 13 gives a plot of plasma concentration in the n - collector of the diode in Fig. 2, with and without injection-efficiency spoiling. The current density is equal to that in Fig. ll(b) for a 15-A clamp current. There is simultaneous conduction by both holes and electrons in a drift field where diffusion forces are relatively small.

If a lateral p-n-p collector were put along the side of the p-n-p emitter, conduction to this collector would be

WIDLAR: CONTROLLING SUBSTRATE CURRENTS IN JUNCTION-ISOLATED ICs 109 7

by diffusion of holes. With a lateral diffusion length of 10 pm, no = 2x 10 cmP3 from Fig. 13 give a lateral current density of 375 A/cm2. Vertical current density is 1000 A/cm2. There is not much to gain from using a lateral collector, but there could be a loss if vertical area were reduced.

A Schottky barrier could theoretically reduce the plasma concentration on the emitter side to zero. Under the conditions in Fig. 13, the substrate current density would be reduced to 110 A/cm2.

Simultaneous solution of (31, (9), and (10) will give substrate current as a function of clamp current. A closed-form solution was not found; solution by numerical methods gave a result that followed the curve plotted in Fig. l l (b) within 10%. This curve, incidentally, is well described by the empirical relation:

Isus = 0.04. I:;

where IcL is the clamp current.

ACKNOWLEDGMENT

The author would like to thank M.

(11)

Yamatake of Na- tional Semiconductor Corporation for assistance in gath- ering the experimental data used in preparing this paper.

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[3] M. Izadinia, P. Ueunten, D. Tam, D. Kinzer, and K. Wagers, A next generation high performance CMOS/bipolar/DMOS H- switch, Proc. Motor-Con, vol. 13, pp. 117-126, Oct. 1988.

[4] R. J. Widlar and M. Yamatake, A monolithic power op amp, IEEE J . Solid-state Circuits, vol. 23, pp. 527-535, Apr. 1988.

[SI T. M. Frederiksen and W. M. Howard, A single-chip monolithic

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[6] R. S. Muller and T. I. Kamins, Dwice Electronics for Integrated Circuitry. New York: Wiley, 1977.

[7] B. Murari, Power integrated circuits: Problems, tradeoffs and solutions, IEEE J . Solid-state Circuits, vol. SC-13, pp. 307-319, June 1978.

[8] J. F. Yenvey, On the mechanism of h,, degradation by emitter- base reverse current stress, in Microeiec1ronic.v and Reliability, vol. 9. New York: Pergamon, Sept. 1970, pp. 425-432.

[Y] B. Hartwig, Driving high-voltage bipolar transistors into reverse avalanche, Powertechnics Mag., pp. 18-25, Dec. 1988.

[ lo] R. J. Widlar, Turn-off processes in high-voltage n-p-v-n switches, IEEE Trans. Electron DeLices, vol. ED-34, pp. 2013-2022, Sept. 1987.

[ l l ] S. K. Ghandi, Semiconductor Power Deikes. New York: Wiley, 1977.

[12] B. J . Baliga and D. Y. Chen, Eds., Power Trunsistorst Dwice Design arid Applications. New York: IEEE, 1984.

Robert J. Widlar was born in Ohio on Novem- ber 30, 1937 and died February 27, 1991. He graduated from the University of Colorado, Boulder, in 1962 while working for Ball Broth- ers Research.

In 1963 he joined Fairchild Semiconductor where he headed linear IC development. In 1966 he formed the linear IC group at National Semiconductor, Santa Clara, CA, and was re- sponsible for new product design until 1970. Since 1974 he had been working as an Indepen-

dent Contractor, and had developed products for both National Semi- conductor and Linear Technology. Since 1963 he had specialized in the development, specification, and application of linear ICs. He designed the first industry-standard IC op amps, voltage comparators, and power voltage regulators, along with generations of improvements. Over two dozen of his products are still in volume production, some for over 20 years. He had pioneered such innovations as the bandgap voltage reference and the super-gain transistor as well as numerous design techniques that are widely used today. His most recent work includes micropower low-voltage ICs, bandgap curvature correction, advanced super-gain op amps, and improved class-B amplifiers and high-power techniques. Bob Widlar will always be remembered as a great innovator, linear circuit designer, and tenacious problem solver. He will be missed by many in the industry.

controlling substrate currents in junction isolated ics

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