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TRANSCRIPT
Young Won Lim4/30/16
Control & Status Registers
Young Won Lim4/30/16
Copyright (c) 2010-2016 Young W. Lim.
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CSR 3 Young Won Lim4/30/16
csrGen
Based on
Chuck Benz ASIC and FPGA Design
csrGen - generate verilog RTL code for processor memory maps in ASIC/FPGA designs
http://asics.chuckbenz.com/
CSR 4 Young Won Lim4/30/16
Module Interface
CSR 5 Young Won Lim4/30/16
Module Interface
clk reset_l
up_din up_addr
up_csl up_rwl
status1 stickybit1 stickybit2
up_dout up_dout_ENL control1 control2 repeatingfield0 repeatingfield1 morerepeat
example_lp
4
6
8
812
2
8
System BUS I/F
Status info from the peri-device
Control signal to the peri-device
CSR 6 Young Won Lim4/30/16
Module Interface
clk reset_l up_din
up_addr up_csl up_rwl
status1 stickybit1 stickybit2
up_dout; up_dout_ENL; control1; control2; repeatingfield0; repeatingfield1; morerepeat;
example_lp
4
6
8
812
2
8
ProcessorPeripheral Device
addr rdata wdata
address bus
data bus
CSR 7 Young Won Lim4/30/16
Control Registers and Status Registers
clk reset_l up_din
up_addr up_csl up_rwl
status1 stickybit1 stickybit2
up_dout; up_dout_ENL; control1; control2; repeatingfield0; repeatingfield1; morerepeat;
Peripheral Device
D Q
D Q
D Q
D Q
4
6
8
8
812
2
D Q
example_lp
Control Registers inside example_lp
Status Registersoutside example_lp
CSR 8 Young Won Lim4/30/16
Memory Access Operations
Memory CPU
WR
Memory CPU
RD
n-bit Data
k-bit Address
n-bit Data
k-bit Address
CSR 9
k-bit Address Bus
n-bit Data Bus
Memory CPU
WR
k-bit Address Bus
n-bit Data Bus
Memory CPU
RD
Memory Unit2k words
n-bit per word
Input n-bit word
Output n-bit word
k-bit address
Mem_En
RD/WR
Memory RD & WR Operations
CSR 10
Data Bus
Data Bus
Memory CPU
WR
Memory CPU
RD
Memory-mapped IO Operations
Address Bus
Address Bus
Peri-Device
Peri-Device
For I/O device
address
For normal memory address
CSR 11 Young Won Lim4/30/16
System Bus Interface
clk reset_l up_din
up_addr up_csl up_rwl
status1 stickybit1 stickybit2
up_dout; up_dout_ENL; control1; control2; repeatingfield0; repeatingfield1; morerepeat;
example_lp
4
6
8
812
2
8
address bus
data bus
control bus
CSR 12 Young Won Lim4/30/16
System Bus Registers
D Qup_din
D Qup_addr
D Qup_csl
D Qup_cslQ
up_dinQ
up_addrQ
up_cslQ
up_cslQQ
address bus
data bus
control bus
D Qup_rwl up_rwlQ
D Q
D Q
up_dout
up_dout_ENL
up_dout_D
up_cslQup_rwlQ
CSR 13 Young Won Lim4/30/16
System Bus Data Registers
D Qup_din
D QControl_Sig_D
up_dinQ
Control_Sig
address bus
data bus
control bus
D Q
up_dout
Status_Sig
up_dout_D
CSR 14 Young Won Lim4/30/16
Combinational Logic Block
default assignments
Sensitivity Lists
Control_Sig <= Control_Sig_D <= up_dinQ
up_dout <= up_dout_D <= Status_Sig
CSR 15 Young Won Lim4/30/16
Reg Signal
CSR 16 Young Won Lim4/30/16
Control register input signals
Control_Sig_D <= up_dinQ
D Qup_din
D QControl_Sig_Dup_dinQ Control_Sig
CSR 17 Young Won Lim4/30/16
Address Decoder
A0
A1
A2
A3
A4
A5
A6
A7
up_addrQ[2:0]
CSR 18 Young Won Lim4/30/16
From up_dinQ to control register input signals
control1_D[7:0]
control2_D[7:0]
control2_D[11:8]
stickybit1S_D
stickybit2S_D
repeatingfield0_D
morerepeat_D[0]
repeatingfield1_D
morerepeat_D[1]
if (IE & A0)
if (IE & A1) up_dinQ[7:0]
if (IE & A2) up_dinQ[7:0]
if (IE & A3) up_dinQ[3:0]
if (IE & A4)
if (IE & A5) up_dinQ[7]
if (IE & A5) ((stickybit2S_D & ~up_dinQ[6]) | stickybit2)
if (IE & A6) up_dinQ[7]
if (IE & A6) up_dinQ[6]
if (IE & A7) up_dinQ[7]
if (IE & A7) up_dinQ[6]
(up_cslQQ & !up_cslQ & !up_rwlQ) IE
CSR 19 Young Won Lim4/30/16
Control Register Input Condition
(up_cslQQ & !up_cslQ & !up_rwlQ) IEA0
A1
A2
A3
A4
A5
A6
A7
up_addrQ[2:0]
D Q D Qup_csl up_cslQ up_cslQQ
up_csl
up_cslQ
up_cslQQ
write
Chip Select
up_rwlQ
CSR 20 Young Won Lim4/30/16
Control Register Timing Diagram
up_csl
up_cslQ
up_cslQQ
write
Chip Select
up_rwlQ
up_addr
up_din
up_dinQ
Control_Sig
D Qup_din
D QControl_Sig_Dup_dinQ Control_Sig
CSR 21 Young Won Lim4/30/16
D FlipFlop with Enable
if (IE & A0) AA_D
D QD
EN
CK
D Q
EN
0
1IEA?
AA_D AA
AA
CSR 22 Young Won Lim4/30/16
Control Register Input from DinQ
if (IE & A0) AA_D
(up_cslQQ & !up_cslQ & !up_rwlQ) IE A0
A1
A2
A3
A4
A5
A6
A7
up_addrQ[2:0]
D Q
ENIEA?
AA_D AA
AA
up_cslQQup_cslQ up_rwlQ
IE
D Qup_din up_dinQ
AA Control Register
CSR 23 Young Won Lim4/30/16
Stickybit Registers
D Q
ENIEA5
stickybit1S_DD Q
up_din up_dinQ[7] stickybit1S
D Q
ENIEA5
stickybit2S_D
D Qup_din up_dinQ[6] stickybit2S
stickybit2
OEA5
CSR 24 Young Won Lim4/30/16
Stickybit Registers – Combinational Feedback Loop
stickybit2S_Dup_dinQ[6]
stickybit2
High stickybit2 from peri device turns on the feedback loop This H can only be turned off by H up_din[6]
0
1
1
1
0 1
1
0
1
0
0
00Stable Loop
Stuck-At-1
set_false_path STA command
H pulse turns on the loop
H pulse turns off the loop
CSR 25 Young Won Lim4/30/16
Stickybit Registers – related code segments
CSR 26 Young Won Lim4/30/16
RepeatingField Registers – related code segments
CSR 27 Young Won Lim4/30/16
Write Registers
control1
control2
stickybit1S
stickybit2S
repeatingfield0
repeatingfield1
morerepeat
8
12
2
control1_D
control2_D
stickybit1S_D
stickybit2S_D
repeatingfield0_D
repeatingfield1_D
morerepeat_D
8
12
2
control1
control2
stickybit1S
stickybit2S
repeatingfield0
repeatingfield1
morerepeat
clk reset_l up_din
up_addr up_csl up_rwl
status1 stickybit1 stickybit2
up_dout; up_dout_ENL; control1; control2; repeatingfield0; repeatingfield1; morerepeat;
example_lp
4
6
8
812
2
8
ProcessorPeripheral Device
addr data
CSR 28 Young Won Lim4/30/16
Output data register input signals
up_dout_D <= Status_Sig
D Q
up_dout
Status_Sig up_dout_D
CSR 29 Young Won Lim4/30/16
Input data to up_dout register
if (OE & A0) {deviceID, version}
if (OE & A1) control1
if (OE & A2) control2[7:0]
if (OE & A3) {4'b0000, control2[11:8]}
if (OE & A4) {2b00, status1}
if (OE & A5) {stickybit1S, stickybit2S, 6'b000000}
if (OE & A5) 0
if (OE & A6) {repeatingfield0, morerepeat[0], 6'b000000}
if (OE & A7) {repeatingfield1, morerepeat[1], 6'b000000};
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
stickybit1S_D
up_dout_D[7:0]
up_dout_D[7:0]
(up_cslQQ & !up_cslQ & up_rwlQ) OE
CSR 30 Young Won Lim4/30/16
Status Register Output Condition
(up_cslQQ & !up_cslQ & up_rwlQ) IEA0
A1
A2
A3
A4
A5
A6
A7
up_addrQ[2:0]
D Q D Qup_csl up_cslQ up_cslQQ
up_csl
up_cslQ
up_cslQQRead
Chip Select
CSR 31 Young Won Lim4/30/16
Output Data Register Timing Diagram
up_csl
up_cslQ
up_cslQQ
write
Chip Select
up_rwlQ
up_addr
up_din
up_dout
Status_Sig
D Q
up_dout
Status_Sig up_dout_D
up_dout_ENL
CSR 32 Young Won Lim4/30/16
From Status Signals to Dout
(up_cslQQ & !up_cslQ & !up_rwlQ) OEup_cslQQ
up_cslQ up_rwlQ
OE
up_addrQ[2:0]
up_dout_D[7:0]
D Q
ENOE
up_dout
{deviceID, version}
control1
control2[7:0]
{4'b0, control2[11:8]}
{2b0, status1}
{stickybit1S, stickybit2S, 6'b0}
0
{rptfd0, mrpt[0], 6'b0}
{rptfd1, mrpt[1], 6'b0};
CSR 33 Young Won Lim4/30/16
Read Status Registers
{deviceID, version}
control1
control2[7:0]
{4'b0, control2[11:8]}
{2b0, status1}
{stickybit1S, stickybit2S, 6'b0}
0
{rptfd0, mrpt[0], 6'b0}
{rptfd1, mrpt[1], 6'b0};
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
up_dout_D[7:0]
stickybit1S_D
up_dout_D[7:0]
up_dout_D[7:0]
clk reset_l up_din
up_addr up_csl up_rwl
status1 stickybit1 stickybit2
up_dout; up_dout_ENL; control1; control2; repeatingfield0; repeatingfield1; morerepeat;
example_lp
4
6
8
812
2
8
ProcessorPeripheral Device
addr data
CSR 34 Young Won Lim4/30/16
FF Inference
CSR 35 Young Won Lim4/30/16
Registers
up_dinQ
up_addrQ
up_cslQ
up_cslQQ
up_rwlQ
up_dout
up_dout_ENL
version
deviceID
control1
control2
stickybit1S
stickybit2S
repeatingfield0
repeatingfield1
morerepeat
8
8
12
2
up_din
up_addr
up_csl
up_cslQ
up_rwl
up_dout_D
(up_cslQ|up_rwlQ)
0
1
control1_D
control2_D
stickybit1S_D
stickybit2S_D
repeatingfield0_D
repeatingfield1_D
morerepeat_D
8
8
12
2
8
4
4
4
8
4
4
4
CSR 36 Young Won Lim4/30/16
Module Skeleton (1)
CSR 37 Young Won Lim4/30/16
Module Skeleton (2)
CSR 38 Young Won Lim4/30/16
CSR Documentation
CSR 39 Young Won Lim4/30/16
Properties of CSRs (1)
CSR 40 Young Won Lim4/30/16
Properties of CSRs (2)
CSR 41 Young Won Lim4/30/16
Properties of CSRs (3)
Young Won Lim4/30/16
References
[1] http://wiki.osdev.org/ARM_RaspberryPi_Tutorial_C[2] http://blog.bobuhiro11.net/2014/01-13-baremetal.html[3] http://www.valvers.com/open-software/raspberry-pi/[4] https://www.cl.cam.ac.uk/projects/raspberrypi/tutorials/os/downloads.html