contact engineering for nano-scale cmos

Phys. Status Solidi A, 1–6 (2012) / DOI 10.1002/pssa.201200343 p s sa

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Part of TopAdvanced Silicon Materials for Electronics and

applications and materials science

Contact engineering for nano-scaleCMOS

Muhammad Hussain*, Hossain Fahad, and Ramy Qaisi

Integrated Nanotechnology Lab, Electrical Engineering, King Abdullah University of Science and Technology, Thuwal, Saudi Arabia

Received 6 June 2012, revised 27 July 2012, accepted 30 July 2012

Published online 12 September 2012

Keywords contact resistance, field effect transistor, nano-devices, nanotube, nanowire

* Corresponding author: e-mail [email protected], Phone: þ966 544 700 072, Fax: þ1 888 908 5614

High performance computation with longer battery lifetime

is an essential component in our today’s digital electronics

oriented life. To achieve these goals, field effect transistors

based complementary metal oxide semiconductor play the key

role. One of the critical requirements of transistor structure and

fabrication is efficient contact engineering. To catch up with

high performance information processing, transistors are going

through continuous scaling process. However, it also imposes

new challenges to integrate good contact materials in a small

area. This can be counterproductive as smaller area results in

higher contact resistance thus reduced performance for the

transistor itself. At the same time, discovery of new one or

two-dimensional materials like nanowire, nanotube, or atomic

crystal structure materials, introduces new set of challenges

and opportunities. In this paper, we are reviewing them in a

synchronized fashion: fundamentals of contact engineering,

evolution into non-planar field effect transistors, opportunities

and challenges with one and two-dimensional materials and a

new opportunity of contact engineering from device architec-

ture perspective.

� 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction Today’s world has significant depen-dency on information technology and computation. Withgradual growth of communication technology, we haveembarked on a journey where digital logic continuouslyserves the mankind. Digital logic depends on formermicroelectronics and today’s nanoelectronics. With sub-100 nm gate length, semiconductor industry is on the path ofultimate scaling of its classical planar complementary-metal-oxide-semiconductor (CMOS) devices. Scaling pro-vides a direct benefit of achieving higher drive current, whichdirectly results in reduction of inverter delay. However, italso poses new set of challenge especially in the front ofpower management. Smaller devices are leaky enough toincrease the unwanted power consumption resulting inhotter device surface and reduced battery lifetime. This isone of the critical challenges for today’s portable electronicdevice oriented human life.

At the same time, scaling of the device does not happenonly laterally (example: gate length), it also happensvertically (example: gate dielectric). And as a result, weneed to scale the source/drain (S/D) junctions also.According to International Technology Roadmap forSemiconductor (ITRS) 2011 report, in near future, somemajor challenges with bulk planar CMOS transistors are

achieving doping profiles in the source/drain extensionregions to form ultra shallow junctions to counter short-channel effects (�10 nm), and at the same time, optimizingthe sheet resistance (�500 V/&) [1]. It is also equallyimportant to make low-resistance contact to shallow, highlydoped source/drain regions.

When we look carefully, we can see that while the gatelength is being reduced, depth of the source/drain junctionsis getting shallower while the contact sheet resistance isincreasing (Table 1). With scaling impact on parasiticresistance, it is increasing and it needs to be well addressed.Another major trend is increased impact of source-draincontact resistance. All these trends clearly indicate that goodand stable contact engineering is very important for classicalCMOS devices.

Typically the ratio of channel width to channel length(W/L) of devices remains same with scaling and hencethe device resistance remains the same too. However,since the contact hole size is decreasing, contact resistanceis increasing proportionately. As per ITRS 2011, non-equilibrium doping levels at the metal/semiconductor appearto be needed by 2010 when an interfacial contact resistivityof 5� 10�8 Vcm2 will be needed to meet device perform-ance objectives [1].


2 M. Hussain et al.: Contact engineering for nano-scale CMOSp

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Table 1 Scaling trend in modern CMOS devices [1].

critical feature 2011 2012 2013 2014 2015

physical gate length (nm) 24 22 20 18 17contact junction depth (nm) 29 26.7 24.7 22 19.8contact sheet resistance(V/&)

9.1 9.9 10.8 12.1 13.5

Figure 1 (online color at: www.pss-a.com) A classical planarmetal-oxide-semiconductor field-effect-transistor device. Variousparasitic resistances and capacitances are shown. Increasingly con-tact resistances (Rc) are dominating the parasitic resistance.

To control the issue of rising contact resistance (a)dopant concentration at the interface needs to be maximized,(b) a lower-barrier-height junction material such as silicon/germanium is required as the contact junction and/or c)low-barrier-height, dual metal (silicides) needs to be usedto contact nþ and pþ junctions. An alternative, yet to bepractically demonstrated, is to form Schottky barriers thatserve as junctions and contacts.

2 Fundamentals of contact engineering Contactengineering is a fundamental module for CMOS deviceprocessing. Figure 1 shows the various parasitic resistancesand the presence of contact resistances in the source/drain

Table 2 Various materials used to form silicide [2].

silicide thin filmresistivity

stable on siliconup to (8C)

nmcoof

PtSi 28–35 750 1.TiSi2 (C54) 13–16 900 2.CoSi2 14–20 950 3.NiSi 14–20 650 1.WSi2 30–70 1000 2.MoSi2 40–100 1000 2.TaSi2 35–55 1000 2.


areas. Historically salicidation of metal is preferred becauseof its process compatibility, reduced sheet resistance, andminimal electromigration. Varieties of metals have beenused for salicidation (Table 2). Typically a metal is depositedand then it goes through subsequent processes like thermalannealing or such to form alloys (silicide). As-depositedfilms are often amorphous or micro to nano-crystalline thustheir carrier mobility is low. Thermal annealing typicallyhelps increasing the grain sizes and to form a stable phaseof poly-crystalline alloys with reduced resistivity. Whenannealing can be advantageous, we also have to be cautiousabout the stress effects rise from the annealing as the stresscan alter the electrical properties of the junctions andchannels. Another important aspect is doping redistributionduring salicidation process as diffusivity in silicide is veryhigh. Out diffusion of dopant from source and drain areacan reduce the surface doping density and thus resultsinto higher contact resistance. In addition to this, dopantredistribution from poly silicon gate can cause Fermi levelchange impacting the work function and thus thresholdvoltage change. If threshold voltage increases, we face thechallenge with lower drive current and associated problemsto drive the device at higher voltage level than it is designedfor.

From contact material perspective, not all metals arescalable for contact engineering. As an example, typicallysputtering is used for metal deposition used for salicidation.However, previously widely used contact metals liketitanium or cobalt consume much larger amount of siliconto form their silicides. On the other hand, nickel is today themetal of choice for contact engineering as it consumes lesseramount of silicon.

Another important factor is line width scaling. From thatperspective, although TiSi2 had lower silicon consumptionratio than that of cobalt, achieving a stable phase for goodcontact engineering through TiSi2 is very difficult withreduced line width. To mitigate the higher silicon consump-tion ratio with cobalt an additional thin barrier layer oftitanium is used before cobalt deposition.

The most dramatic change happened when the industrymoved in favor of nickel silicide. Although nickel silicidehas poor stability issue at higher temperature, it was scalable.Interestingly, when the industry also moved towards low-k

of siliconnsumed per nmmetal

nm of resultingsilicide per nmof metal

barrier heightsto n-Si (eV)

12 1.97 0.8427 2.51 0.5864 3.52 0.6583 2.3453 2.58 0.6756 2.59 0.6421 2.41 0.59

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Figure 2 (online color at: www.pss-a.com) Hexagonal shapedepitaxial silicon is formed around the silicon fin (blue). If they areallowed to grow more, they can join with each other.

dielectric for interconnect and metallization level the highthermal budget requirements got reduced and nickel silicidemade its place as a good contact engineering metal in most oftoday’s advanced CMOS devices.

The conduction mechanism for metal/semiconductorcontacts is a function of barrier height and depletion width.Mainly three types of conduction are possible: (i) thermio-nic; (ii) thermionic-field emission; and (iii) field emission.Typically when a depletion width is large which in turnlowers the barrier height can help in thermionic emissionresulting in Schottky contact. On the other hand, when thedepletion width is low enough that charges can tunnelthrough it is generated from field emission and resultinginto Ohmic contact. From band alignment perspectivein Schottky contact metal, Fermi level energy resides inbetween semiconductor conduction and valence band. Incontrary, if the metal Fermi level is located below the valenceband or above the conduction band then it is the sign ofOhmic contact. It is to be noted that Ohmic contact is muchpreferred as it does not interrupt the charge injection. Sincedepletion width depends inversely on doping concentrationin the semiconductor thus it is a well-known practice toincrease the doping concentration in bulk silicon. Thusthe specific contact resistivity (the main figure of merit incontact engineering) depends on doping concentration in thesemiconductor, the metal semiconductor work function orthe barrier height and the effective mass of the carrier. Aseasily understood, the higher the barrier height, the lowerchance of thermionic emission as it requires more externalenergy typically in the form of thermal energy and voltage,and at the same time the more the effective mass, the heavierthe charges and lower their mobility resulting into increasedcontact resistivity. One point of concern is doping densitycannot be scaled below solid solubility. Thus to lower thebarrier height low band gap material such as silicon–germanium (SiGe) can be used and thus for nearly 5 yearssemiconductor industries are using elevated source/drainprofile with SiGe materials for p-channel FETs in CMOSdevices. In addition to this, SiGe source/drain helpsincreasing the hole mobility as lattice mismatch betweensilicon and SiGe compresses the channel area, thus exertingcompressive strain along the p-FET channel direction andreducing the series resistance, to let holes transport fastin p-channel MOSFETs. Dual silicide is also anotherinteresting option to meet the fast paced demand of contactengineering scaling. One report shows platinum silicide fora p-channel MOSFET and erbium silicide for n-channelMOSFET (fp, fn¼ 0.22 eV, 0.3 eV, respectively) [3].

One promising solution comes from the perspective thatthe interface properties rather than bulk properties in silicongoverns the Schottky barrier height (fB). There are two mainhypotheses behind this mechanism: (i) dipole formation dueto bond polarization at the metal-semiconductor interfaceand (ii) metal-induced gate states (MIGS). According to theMIGS theory, passivating the gap states of the underlyingsemiconductor will relieve the Fermi-level pinning effect,and hence recover the unity relation between fB and the

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metal work function. Mitigation of Fermi level pinningeffect by the insertion of an ultra-thin dielectric has beenexperimented successfully to achieve low barrier height of0.2 eV with Mg and Yb contacts to n-Si with interfacialsilicon nitride [4]. In another interesting approach, near bandedge Schottky barrier height has been achieved by usingtantalum nitride (TaN) with aluminium oxide (AlOx) andsilicon oxide interfacial layer or lanthanum oxide (LaOx) orsilicon oxide (SiO2) interfacial layers [5]. Both of these high-k dielectrics are well known for their dipole induced workfunctioning tuning capability. Their (high-k dielectrics)inclusion both passivates and modulates the Schottky barrierheight of tantalum nitride on n-type silicon by more than0.2 eV, resulting in nearly band-edge modulation with 2 nmof dielectrics. Although thicker dielectric may reduce thebarrier height but it can hinder the tunnelling probability.Since atomic layer deposition (ALD) is usable for bothof these high-k dielectrics, it is possible to use them fornon-planar CMOS devices.

3 Transitioning into non-classical CMOS Whilescaling is the major catalyst to continue the growth ofsemiconductor devices and its various applications, it alsointroduces new challenges like short-channel effects. Non-planar CMOS devices like multi-gate (MugFET) deviceshave been introduced to achieve tighter electrostatic controlover the channel area [6]. Although theoretically it soundslike a sound solution, implementation of such devicearchitecture is challenging. First the channels (fins) arevertically aligned and formed using reactive ion etching.Patterning sub-lithographic fin dimension (example finwidth is 20 nm or below) is a major challenge. Also, finsare patterned in arrays where the distance between adjacentfins are small too (50 nm or below). Fin height is alsorequired to be such so an acceptable aspect ratio ismaintained to achieve appreciable amount of current. Now,with the presence of multiple fins in arrays cause shadowingeffect hindering uniform doping profile in the channels. Thusto address all these challenges, fins go through the epitaxyprocess to add more lateral silicon to the existing fins so theytouch each other (Fig. 2). Now, typically fins are formed in40 or more in an array. To have an elevated or raised source



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Figure 3 (online color at: www.pss-a.com) Nickel silicide forma-tion around a fin, and with increased amount of nickel nearly thewhole silicon fin channel area is consumed.

and drain is comparatively easy [7] but the contact landingmay take a larger area defeating the purpose of increasingnumber of devices in a given area to increase functionalityin ultimate consumer electronics. Also, contact metaldeposition-using sputtering can damage the fin profile andduring contact hole etch the fins can be severely damaged.Therefore, individual contact landing has also been con-sidered for contact engineering in MugFET devices.

One interesting observation is during formation of metalsilicide silicon in the fins can be consumed in such a way thatthe effective channel area can be severely reduced to haveany appreciable amount of current (Fig. 3). Another criticalfactor to be noted is jointed fins may increase the spreadingof resistance from the silicide/silicon interface to the finsthrough source/drain region and under the spacer [8].

In addition to transitioning to non-planar CMOSdevices, semiconductor community is actively thinkingabout introducing alternate high mobility channel materialsto achieve higher drive current. The present trend suggestgermanium or a fraction of silicon germanium is preferredfor p-channel MOSFETs and III–V materials like indium-gallium-arsenide (InGaAs, InSb, and such) are materials ofinterest for n-channel MOSFETs. For p-channel MOSFETs,the most metals in contact with p-type germanium have theirwork function pinned to the valence band of germanium,making it easier to form Ohmic contacts to Ge. However, thisat the same time causes Fermi level pinning at the edge ofvalence band resulting in higher interfacial resistance. ForIII-V devices with increased doping density, we can lowerthe barrier height and it also introduces an interfacial dipole,which ultimately reduces the effective Schottky barrierheight more.

4 Contact engineering for one and two-dimensional nano-devices Over the last decade, excit-ing discovery in one and two-dimensional nanomaterials hasinstigated much interest about the vast promise of this genreof science [9, 10]. At the same time, while the contactengineering is getting tougher with bulk planar or non-planarCMOS devices, it brings new set of research opportunitiesfor both one and two-dimensional nanomaterials baseddevices. There are two ways to form contact in this kind ofdevices: one is to form a contact with self-assemblednanowire or nanotube structured devices (two dimensionalnanomaterials) which ends abruptly generating end bonded


contact and in the other variation metal pads are landeddirectly on top of the one and two dimensional nanomaterials[11]. The later is known as side-bonded contacts.

One of the important features of these two specificcontacts is for an end bonded contact where the nanowire orthe nanotube is connected to a metal at the edge has longerarea for the band to be bent as that happens across the lengthof the nanowire or the nanotube. However, this becomes amajor challenge for side-bonded contact where there is notenough area within the diameter of the nanowire or nanotube.

Typically in bulk semiconductor devices, heavy dopinghelps in reducing the depletion width. However, in a twodimensional nanowire or nanotube devices doping can takesignificant amount of area thus to reduce the effectivediameter of the device. Also, maintaining uniform dopingprofile is a significant challenge, which is associated withabsence of a definitive metrology method to profile thedoping distribution in such materials. For silicon-basednanomaterials oxidation can also play important andderogatory role.

One key example of silicon-based nanowire contactformation is with nickel salicidation, which is widely used inbulk CMOS devices [12, 13]. For nanomaterials, the reactionmechanism varies significantly. Crystallographic orientationof the silicon nanowires in conjunction with stress build updue to salicidation can significantly impact the stability of thecontact. When a thin nickel film is deposited and annealed,the orthorhombic d-Ni2Si is formed first which is followedby NiSi and finally NiSi2. Although NiSi is the preferredphase, for a Si (112) nanowire, the u-Ni2Si is formed at300 8C, which does not show up in bulk silicon at such alow temperature. This phase remains stabilized till 600 8Cand then at 700 8C the silicide forms whiskas. For a Si (111)nanowire, epitaxial NiSi2 is formed first and remains stabletill 700 8C when the low resistivity NiSi is formedtemporarily before it turns into NiSi2 at higher temperature.

In case of germanium nanowire, nickel contact padsreact to form axial nickel-germanide at low temperature(�350 8C). At a slightly higher temperature of �450 8Cfracture starts to happen due to stress issue. However, bylimiting the temperature and increasing the annealing time itis possible to grow long nickel germanide segments [14].

Carbon nanotube, which has excellent mobility suffersfrom presence of Schottky barrier at the nanotube/metalinterface [15]. The low dimensionality of the nanotube isprobably the root cause of this. This phenomenon isamplified by non-uniformity in dimensionality. TheSchottky barrier between metal contacts and the semicon-ducting carbon nanotube can be tuned by modifying theelectrodes’ work function by hydrogen treatment), vacuumanneal, and post-contact deposition anneal to desorb oxygen;all can help achieve a smaller barrier [16–19].

Interesting possibilities exist with gallium nitridenanowires. Titanium/gold conatct in such nanowire devicesshow non-linear behavior [20]. However, with UV illumina-tion it shows linear Ohmic conatct type behavior. ProbablyUV illumination produces excess electroncs to move to a

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Table 3 various materials used to form silicide.

graphene formationprocess

contact metal contact resistivityor resistance

epitaxy on siliconcarbide [24]

Ti/Au 7.5� 10�8 Vcm2

solution processed [25] Ti �0.1 kVmm2

graphene oxidereduction [26]

Al no contactresistance value,but high outputcurrent

chemical vapordeposition-basedgrowth on nickel [27]

Ni/AuTi/Pd/Au 7500 Vmm750 Vmm

epitaxy on SiC(4H-SiC) [28]

Cr/AuTi/Au 5 mVcm2

60 mVcm2

chemical vapordeposition-basedgrowth on copperfoil [29]

Au 340 Vmm

Figure 4 (online color at: www.pss-a.com) Nanotube field effecttransistor with core-shell gate stacks. When the nanotube channelthickness is below 10 nm, full volume inversion takes place and thedevice generates higher Ion.

different energy state resulting into narrower depeletionregion and higher tunneling probability. For zinc oxide-based nanowires, a titanium/gold conatct forms Ohmicconatct whereas platinum-based conatct forms Schottkyconatct [21].

Moving towards two-dimensional atomic crystal struc-tures like graphene, MoS2, etc. – exiciting as well asintriguing properties of these materials make them promisingfor further exploration in transistors. There remain, however,several challenges in constructing graphene devices withhigher performance. One critical challenges of makingthese materials compatible for transistor applications is tohave well control over the metal-material contact resistance.Theoretical studies suggest charge injection from the metalmay change the properties of graphene adjacent to thecontact and that can result into p–n, p–p, or n–n junctionformations [22, 23]. We have tried to capture a synopticunderstanding of the research trend in contact engineeringfor graphene (Table 3).

The table suggests that there is no clear winner. A recentstudy indicates that the electronic structure, electron phononcoupling, and the doping level in gold plated graphene aremostly retained [29]. In some reports, oxygen plasma hasbeen used to enhance adhesion between the metal and thegraphene to form good Ohmic contacts to graphene [24, 30].It is to be noted, upto the best of our knowledge no conatctengineering study is reported on MoS2.

5 Contact engineering from device architectureperspective Recently, we have demonstrated that nano-tube architectures with core-shell gate stacks are moreadvantageous than nanowire architectures for field-effect-transistors applications. With conventional channelmaterials like silicon and silicon germanium (SiGe), wehave shown that a nanotube architecture transistor iscapable of generating high drive current resulting into high

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performance information processing capability, lower leak-age potentially transformative for longer battery lifetimeand area efficiency indicates more functionalities per chip[31, 32]. A nanotube field effect transistor operates near thefull volume inversion and capable to leverage the presenceof all the density of states for higher current generation.Two gates (core–shell: inside–outside) help mitigatingshort-channel effects in a thin nanotube channel of 15 nmor below. Now, from a contact engineering perspective of a15 nm node compatible CMOS design and process rulesuggests that to match the current generated per siliconnanotube transistor, ten to fifteen nanowire transistors arerequired. Thus, the corresponding contact area results into85% more area requirement by nanowire transistors thanthat of a single nanotube transistor to be competitive fromperformance perspective. This is an excellent opportunity tolook at the contact engineering from a different perspectiveas contact engineering is not only to scale the material andits electrical properties but to ensure that we are maintain-ing the area efficiency – a direct benefit of device scaling(Fig. 4).

6 Conclusion In this review on contact engineeringfor nanoscale transistors, we have described the trend ofcontact engineering in classical CMOS devices, their roleson performance and area efficiency. We have also extendedthe discussion to their evolution during the transition ofclassical planar CMOS devices to non-classical non-planarCMOS architectures. Next, we have portrayed the challengesand opportunities of contact engineering for one and two-dimensional materials. And finally, we have reported a newperspective about contact engineering in context of devicearchitecture. All these discussions seriously point out thenecessity of scaled and stable contact materials with lowcontact resistance.

Acknowledgements We deeply appreciate the generousresearch grants provided by King Abdullah University of Scienceand Technology.



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contact engineering for nano-scale cmos

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