Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell

Placement

Saurabh AdyaIgor Markov

(University of Michigan)

Outline

• Motivations for mixed-mode placement• Previous Work• Components of our flow

– Fixed-outline floorplanning– Standard-Cell placement

• Mixed-mode placement flow• New Benchmarks• Results• Conclusions

Motivation

• IP reuse : PD with large rectangular blocks• Integrated partitioning, FP & placement

– Older flows apply separate optimizations– New generation of fast (min-cut) placers

enable an integrated approach• Partitioner is part of the placer• Shifted cutlines perform floorplanning

• However handling large macros by RB is difficult– Small macros can be handled by RB (not in our work)

• Capo, Dragon, Feng Shui, etc.– can’t place large macros w/o overlaps

Previous Work• Continuous optimization techniques

– Force directed approaches• [Eisenmann, Johannes, DAC ‘98] : mixed-mode• [Mo et. al, ICCAD ‘00] : macros only + congestion

– Are good with a lot of white-space in design– Otherwise, designer must remove overlaps

• Combinatorial optimization techniques– Particularly promising on constrained

designs– [Nag et. al, DATE ‘98]: macros only – This work: mixed-mode

Cadence-recommended Mixed-Mode Flow for SEDSM1. SEDSM places blocks at the periphery2. Designer manually removes overlaps3. From now on, blocks are considered fixed4. QPlace is called to place standard-cells• Otherwise, as our experiments show,

– Handling many large cells is not ideal in QPlace

• Next-gen Cadence mixed-mode layout tool– In -testing – Preliminary results are good

SEDSM Output (not new gen!)

Our Proposed Flow (Outline)

1. Generate initial placement using an arbitrary, min-WL standard-cell placer

2. Generate a fixed-outline floorplanning instance by “physical clustering”

3. Remove overlaps and generate valid macro locations using a fixed-outline floorplanner

4. Place small cells using standard-cell placer with macros considered fixed

(details – later)

Component : 1• Fast min-cut std-cell placer (Capo)

– [Caldwell, Kahng and Markov, DAC 2000]

• Algorithms used– Min-cut bisection, optimal end-case placers– Multi-level FM partitioning– Cut-lines allowed to move, adaptive part. toler.

• Yet, Capo does not handle large macros

So on

Component : 2• Fixed-outline floorplanner (Parquet)

– [Adya and Markov, ICCD 2001]

• Solves a constraint satisfaction problemwhile minimizing wirelength

• Uses enhanced local search during annealingto satisfy outline constraints

y-sp

an

x-span

Floorplan “Slack”• Slack for block A in x- or y- dimension

– The distance that A can be moved in x- or y- dimension without increasing the x- or y- span

• “Critical” blocks have zero slack• Critical blocks lie on critical paths: analogy w STA• We want to move critical blocks to improve fplan

FE

D

A

B C

Left Packing Right Packing

x-slack for block A =

x(Aright) – x(Aleft)A

CB

DE

Fcritical blocks

Fixed-outline FP’er Parquet(based on Simulated Annealing)

S.A.

x-violation

y-violation

current outline

required outline

Restart

S.A.

S.A.

In This Work:

Improvements to Parquet• HPWL minimization

– Local annealing objective = linear combination of area and wirelength

– Additional moves designed to improve HPWL

• Handling soft blocks– X/Y slacks suggest changes to AR of a block– At regular intervals during annealing

• Sort blocks according to slacks• Shape blocks as suggested by the slacks• Try to greedily reshape every soft blocks

Mixed-mode Placement Flow (1)

• Find a tentative placement of macros– Shred macros into fake standard-cells– Connect sub-cells with fake wires (pics

follow)– Place “shredded netlist’’ using Capo– Compute locs of macros as average locs of

sub-cells

• (continued later)

Shredding Macro Cells

0 1 2

1

2

3

0

• Shred all macros into smaller sub-cells

• Determine location of macros by averaging locations of sub-cells

• Determine the prevailing orientation of each macro

(Should work with many min-WL placers)

Va

Vr

Case: Orient Va Vr : N Va Vr : S Va Vr : W Va Vr : E

…etc(4 more cases)End Case;

Shredding Macro Cells (cont)

• Some macros may have fixed orientation– We tie the corner sub-cells to the corners of layout– (fake wires tying shredded pieces must be stronger)

• Lemma: this works for min-HPWL placers– This does not work for quadratic placers (!)

Orient = N Orient = N Orient = W

Initial Placement

Mixed-mode Placement Flow (2)

• Find a tentative placement of macros– Shred macros into fake standard-cells– Connect sub-cells with fake wires – Place “shredded netlist’’ using Capo– Compute locs of macros as average locs of sub-

cells

• Generate a FP instance with soft & hard blocks– Cluster neighboring standard cells into soft

blocks

• (continued later)

Physical Clustering

Mixed-mode Placement Flow (3)

• Find a tentative placement of macros– Shred macros into fake standard-cells– Connect sub-cells with fake wires – Place “shredded netlist’’ using Capo– Compute locs of macros as average locs of sub-

cells

• Generate a FP instance with soft & hard blocks– Cluster neighboring standard cells into soft blocks

• Remove overlaps by fixed-outline floorplanning (Parquet)

• (continued later)

Floorplanned Design

Mixed-mode Placement Flow

• Find a tentative placement of macros– Shred macros into fake standard-cells– Place “shredded netlist’’ using Capo– Connect sub-cells with fake wires – Compute locs of macros as average locs of sub-cells

• Generate a FP instance with soft & hard blocks– Cluster neighboring standard cells into soft blocks

• Remove overlaps by fixed-outline FP (Parquet)• Place std. cells consistently with the

macros– Fix macros at current locations– Replace all standard cells using Capo

Final Placement

New Benchmarks

• Derived from ISPD-98 (IBM) circuits– Original specs give cell areas, but not dimensions

• We assumed rowheight = 16 for standard cells– Large cells macros with AR=1 (cf. Dragon BMs)

• Whitespace for each design is 15 %• Fixed pads placed randomly (cf. Dragon BMs)• Available at :

– http://vlsicad.eecs.umich.edu/BK/ISPD02benchand through http://www.gigascale.org/bookshelf

Circuit Cells Nets Macros Largest QPlace Capo + Parquet Macro HPWL Time HPWL Time

x1e6 limit=24h x1e6ibm01 12752 14111 246 6.37% 4.01 6m 3.96 18mibm02 19601 19584 280 11.36% 16.64 1hr19m 8.37 31mibm03 23136 27401 290 10.75% time-out time-out 12.16 42mibm04 27507 31970 608 9.15% time-out time-out 13.48 47mibm05 29347 28446 0 0 11.7 7m 11.51 8mibm06 32498 34826 178 3.95% 18 2hr4m 10.25 56mibm07 45926 48117 507 4.75% 28.1 1hr45m 15.75 58mibm08 51309 50513 309 12.10% 26.62 3hr47m 21.18 1hr34mibm09 53395 60902 253 5.42% time-out time-out 19.59 1hr6mibm10 69429 75196 786 4.79% time-out time-out 60.72 3hr49mibm11 70558 81454 372 4.47% time-out time-out 28.49 1hr46mibm12 71076 77240 651 6.42% time-out time-out 51.74 11hr15mibm13 84199 99666 424 4.22% time-out time-out 39.39 2hr31mibm14 147605 152772 614 1.98% time-out time-out 56.19 4hr46mibm15 161570 186608 393 10.99% time-out time-out 70.48 3hr57mibm16 183484 190048 458 1.89% time-out time-out 79.59 3hr13mibm17 185495 189581 760 0.94% 89.34 2hr24m 92.38 7hr23mibm18 210613 201920 285 0.96% 56.43 1hr29m 54.9 5hr78m

Conclusions• Mixed-mode placement increasingly important• Our flow combines techniques from

std-cell placement & fixed-outline floorplanning

• Results: commercial tools can be improved• Source code publicly available through:

– http://www.vlsicad.eecs.umich.edu/BK/– http://www.gigascale.org/bookshelf

• Ongoing work– Congestion analysis– Multilevel hierarchical floorplanning

Acknowledgements

• Financial support from – Gigascale Silicon Research Center– IBM

• Technical support from