conference program - iccad.comphysical verification and dfm for large digital designs. in 2015 he...

C O N F E R E N C E P R O G R A M

NOVEMBER 4 – 7, 2019The Westin Wesminster, Westminster, Colorado

ICCAD.COMIn cooperation with:

special interest group on

design automation

WELCOME TO THE 38TH ICCAD

FROM DAVID PANICCAD GENERAL CHAIRWelcome to the 38th International Conference on Computer-Aided Design! For the first time, ICCAD is being held in the Denver area. As ICCAD has been moving around from its birthplace in Silicon Valley, to Silicon Hills (Austin), to Southern California, and this year to Rocky Mountains, we hope you enjoy these different locations, get to know local related industry, and of course the ICCAD conference itself.

Jointly sponsored by IEEE and ACM, ICCAD has been the premier forum to explore emerging technology challenges in electronic design automation, present leading-edge R&D solutions, and identify future research directions. The ICCAD scope has also been adapted and expanded to address emerging technology, design, and automation challenges including those in AI, IoT, security, among others.

This is yet another strong year for ICCAD in terms of regular paper submissions. The total 394 final submissions were organized into 14 tracks and reviewed by 135 outstanding TPC members from both academia and industry around the world. Our rigorous double-blind review process culminated with a full-day in-person meeting in June, where 94 regular papers were accepted and formed into 28 regular sessions. This marks a competitive 23.9% acceptance rate. We also had a high number of special session and tutorial proposals submitted to ICCAD. In the end, 11 special sessions and 1 embedded tutorial were formed on topics that complement the regular sessions.

We are delighted to host several distinguished keynote speakers: the Monday morning keynote on “Beyond CMOS Technologies for Computing: Prospects and Best Bets” will be given by Dr. Ian Young, Intel Senior Fellow. On Wednesday morning, Dr. Wolfram Burgard, VP for Automated Driving Technology at the Toyota Research Institute, will present the keynote on “Probabilistic and Machine Learning Approaches for Autonomous Robots and Automated Driving”. On Tuesday, IEEE CEDA will host its annual ICCAD Luncheon Distinguished Lecture. We hope you find these keynotes informative and inspiring.

On Thursday, we have seven stimulating workshops on a variety of trending topics, including: Hands-on Workshop on Machine Learning, Deep Learning and Reinforcement Learning for EDA Developers; 3rd International Workshop on Quantum Compilation; Top Picks in Hardware and Embedded Security; Second Workshop on Open-Source EDA Technology (WOSET); International Workshop on Design Automation for Analog and Mixed-Signal Circuits; and 1st Workshop on Accelerator Computer-Aided Design. They all have exciting programs themselves, so we hope that many of you will take advantage of them and stay an extra day.

Following its long tradition, ICCAD continues to be the home to strong student-oriented activities: the SIGDA CADathlon, the ACM Student Research Competition, and the ICCAD CAD Contests. In addition, on Wednesday night, for the first time, ICCAD will host a “Career & Diversity” event where recruiters from industry will share their views on what companies are looking for and young graduates who recently joined industry will share their experiences and tips, and why diversity is important at work.

Once again ICCAD promises to be an ultimate destination for those working on the cutting-edge EDA research. We do hope you will be able to join us. Finally, we are grateful to our ICCAD 2019 sponsors, supporters, and volunteers for making this year’s conference another great success.

Enjoy ICCAD and Rocky Mountains!

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TABLE OF CONTENTS

Welcome Message 2

General Information 4

CADathlon at ICCAD 6

Best Paper Candidates & Committees 9

Monday Schedule 10

Opening Session & Award Presentations 12

Monday Keynote Address 13

Monday Session Details 14

ACM Student Research Competition Poster Session 18

ACM Student Research Competition Technical Presentations 27

Tuesday Schedule 28

Tuesday Session Details 30

Tuesday Invited Keynote Luncheon 36

ACM/SIGDA Membership Meeting 45

Wednesday Schedule 46

Wednesday Keynote Address 48

Wednesday Session Details 49

Thursday Schedule 60

Thursday Workshop Details 61

Executive Committee 67

Technical Program Committee 68

Conference Sponsors 70

The Westin Westminster Map 73

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GENERAL INFORMATION

Registration Hours & Location

Location: Terrazza FoyerMonday, November 4 7:00am – 6:00pm Tuesday, November 5 7:30am – 6:00pm Wednesday, November 6 7:30am – 6:00pm Thursday, November 7 7:00am – 4:00pm

ICCAD 2019 Mobile App Review the program, save sessions to your personalized conference schedule, read speakers abstracts, and connect with other attendees using the ICCAD 2019 mobile app provided by Whova, available for download today. Download Whova and search for ICCAD 2019.

Proceedings ICCAD Conference Papers will be delivered electronically online via a username and password. To access: http://proceedings.iccad.com Badge ID = Registration ID (on your badge)Your Email = Email address Please refer to your registration receipt to access the files you are eligible to view.

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GENERAL INFORMATION

For Speakers & Presenters SPEAKERS’ BREAKFASTPlease attend the day of your presentation! Location: Legacy BallroomMonday, November 4 7:30 - 8:15amTuesday, November 5 7:30 - 8:15amWednesday, November 6 7:30 - 8:15am

NEED PRACTICE?An AV Practice Room will be available in Sage Board Room, set up with a computer, LCD projector, and screen for you to practice/view your slides before your session.Location: Sage Board RoomMonday, November 4 7:00am - 6:00pm Tuesday, November 5 7:00am - 6:00pm Wednesday, November 6 7:00am - 6:00pm

ICCAD Social Media Connect with ICCAD through Twitter @ICCAD.

Stay Connected during the Conference ICCAD 2019 is offering internet access in the meeting rooms for attendees. The Wi-Fi connection is Westin Westminster, user name: iccad2019 password: iccad2019.

Conference Management Our mission is to facilitate networking, education and marketing with efficiency and precision in order to maximize customer experiences, and client profitability and recognition. We accomplish this by having a committed staff of trade show production organizers with

the training, technology tools, processes and experience to offer the best service in the industry. Visit mpassociates.com for more information.

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BEST PAPER CANDIDATES

IEEE/ACM William J. McCalla ICCAD Best Paper Award CandidatesMONDAY, NOVEMBER 41B.1* PowerGridFixingforElectromigration-InducedVoltageFailures Zahi Moudallal - Univ. of Toronto Valeriy Sukharev - Mentor, A Siemens Business Farid N. Najm - Univ. of Toronto

TUESDAY, NOVEMBER 54A.1* HowtoEfficientlyHandleComplexValues?ImplementingDecisionDiagramsforQuantumComputing Stefan Hillmich - Johannes Kepler Univ. Linz Alwin Zulehner - Johannes Kepler Univ. Linz Robert Wille - Johannes Kepler Univ. Linz

4B.1* AnalyzingandModelingIn-StorageComputingWorkloadsOnEISC—AnFPGA-BasedSystem-LevelEmulationPlatform Zhenyuan Ruan - Univ. of California, Los Angeles Tong He - Univ. of California, Los Angeles Jason Cong - Univ. of California, Los Angeles

6B.4* GenUnlock:AnAutomatedGeneticAlgorithmFrameworkforUnlockingLogicEncryption Huili Chen - Univ. of California, San Diego Cheng Fu - Univ. of California, San Diego Jishen Zhao - Univ. of California, San Diego Farinaz Koushanfar - Univ. of California, San Diego

WEDNESDAY, NOVEMBER 69A.3* SecurityandComplexityAnalysisofLUT-basedObfuscation:FromBlueprinttoReality Gaurav Kolhe - Univ. of California, Davis Hadi Mardani Kamali - George Mason Univ. Miklesh Naicker - San Francisco State Univ. Tyler David Sheaves - San Francisco State Univ. Hamid Mahmoodi - San Francisco State Univ. Sai Manoj Pudukotai Dinakarrao - George Mason Univ. Houman Homayoun - Univ. of California, Davis SetarehRafatirad-George Mason Univ. Avesta Sasan - George Mason Univ.

10B.3*NanoTherm:AnAnalyticalFourier-BoltzmannFrameworkforFullChipThermalSimulations SmrutiR.Sarangi-Indian Institute of Technology Delhi Shashank Varshney - Indian Institute of Technology Delhi Hameedah Sultan - Indian Institute of Technology Delhi Palkesh Jain - Qualcomm Technologies, Inc.

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IEEE/ACM William J. McCalla ICCAD Best Paper Award Selection Committee

JoergHenkel(Chair)- Karlsruhe Institute of TechnologyYier Jin - Univ. of FloridaFrankLiu- IBM, Corp.ParthaPande- Univ. of WashingtonChia-LinYang- National Taiwan Univ.

Ten-Year Retrospective Most Influential Paper Award Selection Committee

RobertWille(Chair) - Univ. of Linz.NirajK.Jha - Princeton Univ.Hai(Helen)Li - Duke Univ.SachinSapatnekar - Univ. of MinnesotaPingqiangZhou- ShanghaiTech Univ.

TulikaMitra(Chair)-National Univ. of SingaporeDemingChen - Univ. of Illinois at Urbana-ChampaignSiddharthGarg - New York Univ.TonyGivargis - Univ. of California, IrvineIrisHui-RuJiang - National Taiwan Univ.Hai(Helen)Li - Duke Univ.YuWang - Tsinghua Univ.RobertWillie - Univ. Linz

BEST PAPER AWARD COMMITTEES

TUTORIAL/SPECIAL SESSION COMMITTEE

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ACM SIGDA CADATHLON 2019 AT ICCAD

ACM SIGDA CADathlon 2019 at ICCADSunday, November 3Time: 8:00am - 5:00pm | Room: Cotton CreekIn the spirit of the long-running ACM programming contest, the CADathlon is a challenging, all-day,programmingcompetitionfocusingonpracticalproblemsattheforefrontofComputer-AidedDesign,andElectronicDesignAutomationinparticular.ThecontestemphasizestheknowledgeofalgorithmictechniquesforCADapplications,problem-solvingandprogrammingskills,aswellasteamwork.

As the “Olympic games of EDA,” the contest brings together the best and the brightest of the nextgenerationofCADprofessionals.Itgivesacademiaandtheindustryauniqueperspectiveonchallengingproblemsandrisingstars,anditalsohelpsattracttopgraduatestudentstotheEDAfield.

The contest is open to two-person teams of graduate students specializing in CAD and currently full-timeenrolledinaPh.D.grantinginstitutioninanycountry.Studentsareselectedbasedontheiracademic backgrounds and their relevant EDA programming experiences. Travel grants are provided toqualifyingstudents.TheCADathloncompetitionconsistsofsixproblemsinthefollowingareas:

(1) Circuit design and analysis (2) Physical design and design for manufacturability(3) Logic and high-level synthesis (4) System design and analysis (5)Verificationandtesting(6) Future technologies (Bio-EDA, Security, AI, etc.)

MorespecificinformationabouttheproblemsandrelevantresearchpaperswillbereleasedontheInternetoneweekpriortothecompetition.Thewritersandjudgesthatconstructandreviewthe problems are experts in EDA from both academia and industry. At the contest, students will be given the problem statements and example test data, but they will not have the judges’ test data. Solutionswillbejudgedoncorrectnessandefficiency.Whereappropriate,partialcreditmightbegiven.Theteamthatearnsthehighestscoreisdeclaredthewinner.Inadditiontohandsometrophies,thefirstandsecondplaceteamswillreceivecashaward.

Contest winners will be announced at the ICCAD Opening Session on Monday morning and celebratedattheACM/SIGDADinnerandMemberMeeting.

TheCADathloncompetitionissponsoredbyACM/SIGDAandseveralComputerandEDAcompanies.Fordetailedcontestinformationandsampleproblemsfromlastyear’scompetition,pleasevisittheACM/SIGDAwebsiteat:https://www.sigda.org/sigda-events/cadathlon/

Forallinquiries,pleasesendemailsto:[email protected]

ORGANIZINGCOMMITTEE:

Chair:Tsung-WeiHuang,Univ. of Utah, UT, USAViceChair:Yu-GuangChen,National Central Univ., TaiwanViceChair:Pei-YuLee,Maxeda Technology, Taiwan

Sponsored by: special interest group on

design automation

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MONDAY SCHEDULE

8:30 - 9:00amOpening Session & Awards Location: Westminster IV

9:00 - 10:00amKeynote: Beyond CMOS Technologies for Computing: Prospects and Best Bets Ian A. Young - Intel Corp. | Location: Westminster IV

10:00 - 10:30amCoffee Break Location: Westminster Foyer

10:30am - 12:30pm Session 1A: Random Ski: PUF and Random Number Generators Location: Westminster IV

Session 1B: New Perspectives of Timing, Power and IR Drops Location: Westminster I

Session 1C: Optimization Attacks Routing Challenges Location: Westminster II

Special Session 1D: Design Automation and DNN for FPGAs Location: Westminster III

11:30am - 1:30pmACM Student Research Competition Poster Session Location: Westminster Foyer

12:30 - 1:30pmLunch Location: Legacy Ballroom

Sponsored by:

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MONDAY SCHEDULE

1:45 - 3:45pmSession 2A: Accelerating Neural Networks Location: Westminster IV

Session 2B: Emerging Applications in Synthesis Location: Westminster I

Session 2C: Approximation in Behavioral Specifications, Neural Network Design, and Stochastic Computing Location: Westminster II

Special Session 2D: 2019 CAD Contest at ICCAD Location: Westminster III

3:45 - 4:15pmCoffee Break Location: Westminster Foyer

4:15 - 5:45pmSession 3A: Processing in Memory and Secure Memory Design Location: Westminster IV

Session 3B: Efficient and Reliable Design Location: Westminster I

Session 3C: Emerging Technologies for Computing and Networks Location: Westminster II

Special Session 3D: Design Automation for Power Electronics Location: Westminster III

5:45 - 6:15pmAI / Machine Learning at Cadence Location: Westminster I

6:00 - 10:00Second Working Group Meeting on Logic Locking and Anti-Trojan Solutions Location: Westminster II & Westminster III

6:15 - 6:45pmNetworking Reception Location: Westminster Foyer

6:45 - 8:15pmACM Student Research Competition Technical Presentations Location: Westminster I

Sponsored by:

Sponsored by:

Sponsored by:

MONDAY, NOVEMBER 4

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StartofftheconferencewithopeningremarksfromtheICCADExecutiveCommitteemembersandhear the highlights of the conference. The IEEE/ACM William J. McCalla ICCAD Best Paper award willbeannouncedalongwithotherawardpresentationsfromIEEECEDAandACM..

Opening Session and AwardsTime: 8:30am - 9:00am | Room: Westminster IV

IEEE/ACM WILLIAM J. MCCALLA ICCAD BEST PAPER AWARDThisawardisgiveninmemoryofWilliamJ.McCallaforhiscontributionstoICCADandhisCADtechnical work throughout his career. Front-End Award:4B.1 AnalyzingandModelingIn-StorageComputingWorkloadsOnEISC—AnFPGA-BasedSystem-LevelEmulationPlatform Zhenyuan Ruan - Univ. of California, Los Angeles Tong He - Univ. of California, Los Angeles Jason Cong - Univ. of California, Los AngelesBack-End Award: 1B.1PowerGridFixingforElectromigration-InducedVoltageFailures Zahi Moudallal - Univ. of Toronto Valeriy Sukharev - Mentor, A Siemens Business Farid N. Najm - Univ. of Toronto

TEN YEAR RETROSPECTIVE MOST INFLUENTIAL PAPER AWARDThisawardisbeinggiventothepaperjudgedtobethemostinfluentialonresearchandindustrialpracticeincomputer-aideddesignoverthetenyearssinceitsoriginalappearanceatICCAD.

2009PaperTitled:NonvolatileMemristorMemory:DeviceCharacteristicsandDesignImplicationsYenpoHo,GarngM.Huang,PengLi;Texas A&M Univ.ICCAD 2009, pp. 485-490

IEEE FELLOWFarinaz Koushanfar, Univ. of California, San Diego Forcontributionstohardwareandembeddedsystemssecurityandtoprivacy-preservingcomputing.

IEEE CEDA OUTSTANDING SERVICE RECOGNITIONIris Bahar - Brown Univ. For outstanding service to the EDA community as ICCAD General Chair in 2018.

IEEE CEDA ERNEST S. KUH EARLY CAREER AWARDPierre-Emmanuel Gaillardon - Univ. of Utah ForcontributionstoElectronicDesignAutomationtargetingemerginglogicandmemorytechnologies.

ACM/SIGDA CADATHALONIntroductionofthe2019winners.

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KEYNOTE ADDRESS

Speaker:IanA.Young - Senior Fellow and Director of Exploratory Integrated Circuits, Components Research, Technology and Manufacturing Group,Intel Corporation, Hillsboro, Oregon

CMOSintegratedcircuittechnologyforcomputationisataninflexionpoint.Althoughthisisthetechnology which has enabled the semiconductor industry to make vast progress over the past 30-plusyears,itisexpectedtoseechallengesgoingbeyondthetenyearhorizon,particularlyfromanenergyefficiencypointofview.Thusitisextremelyimportantforthesemiconductorindustryto discover a new integrated circuit technology which can carry us to the beyond CMOS era, sothatthepower-performanceofcomputingcancontinuetoimprove.Currently,researchersareexploringnoveldeviceconceptsandnewinformationtokensasanalternativeforCMOStechnology.Examplesofareasbeingactivelyresearchedare;quantumelectronicdevices,suchasthetunnelingfield-effecttransistor(TFET),anddevicesbasedonelectronspinandnano-magnetics(spintronics).Itisclearthatchoiceswillneedtobemadeinthenext10yearstoidentifyviableenergyefficientalternativestoaugmentCMOSforcomputation.Toprioritizeandguidetheresearchexplorationinmaterials,devicesandcircuits,benchmarkingmethodologyandmetricsarebeing used.

In this talk research in quantum materials for beyond CMOS devices (nanoelectronic and/or nanomagnetic)ispresented.Somedeviceproposalsanddemonstrationsarereviewedandthetrendsinthisfieldareidentified.Considerationsguidingdevelopmentofcompetitivecomputingtechnologies are described. Results of beyond-CMOS circuit benchmarking are reviewed.

Biography:IanYoungisaSeniorFellowanddirectorofExploratoryIntegratedCircuitsintheTechnologyandManufacturingGroupofIntelCorporation.HejoinedIntelin1983andhistechnicalcontributionshavebeeninthedesignofDRAMs,SRAMs,microprocessorcircuitdesign,Phase Locked Loops and microprocessor clocking, mixed-signal circuits for microprocessor high speedI/Olinks,RFCMOScircuitsforwirelesstransceivers,andresearchforchiptochipopticalI/O.HehasalsocontributedtothedefinitionanddevelopmentofIntel’sprocesstechnologies.HenowleadsaresearchgroupexploringthefutureoptionsfortheintegratedcircuitinthebeyondCMOSera.IanYoungreceivedtheBachelorofElectricalEngineeringandtheMasterEng.Science,from the Univ. of Melbourne, Australia. He received the PhD in Electrical Engineering from the Univ.ofCalifornia,Berkeley.Heistherecipientofthe2009InternationalSolid-StateCircuitsConference’sJackRaperAwardforOutstandingTechnologyDirectionspaper.Hereceivedthe2018 IEEE Frederik Philips Award “for leadership in research and development on circuits and processesfortheevolutionofmicroprocessors”.IanYoungisaFellowoftheIEEE.

Keynote: Beyond CMOS Technologies for Computing: Prospects and Best BetsTime: 9:00 - 10:00am | Location: Westminster IV

MONDAY, NOVEMBER 4

All speakers are denoted in bold | * denotes Best Paper Candidate

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Session 1A - Random Ski: PUF and Random Number GeneratorsTime: 10:30am - 12:30pm | Room: Westminster IVModerator:

WeizeYu - Old Dominion Univ.

PUFs and random number generators are fundamental building blocks for many hardware and systemsecuritytechniques.However,therearemanypracticalchallengesinensuringtheirperformance, reliability, and security. This session is comprised of three papers addressing these challenges.Thefirstpaperdevelopsanewtwo-layerPUFcompositiontodefendagainstmodelingattacks.Thesecondpaperproposesandimplementsanall-digitalTRNGdesignbasedonachaoticcellular automata topology. The third paper presents a quantum random number generator resilient againstsidechannelattacks.

1A.1 AnAll-DigitalTrueRandomNumberGeneratorBasedonChaoticCellularAutomata Topology

ScottBest - Rambus Inc.XiaolinXu - Univ. of Illinois at Chicago

1A.2 SCR-QRNG:Side-ChannelResistantDesignusingQuantumRandomNumberGeneratorJungminPark - Univ. of FloridaSeongjoon Cho, Taejin Lim - EYL PartnersSwarup Bhunia, Mark Tehranipoor - Univ. of Florida

1A.3 StrengtheningPUFsusingCompositionZhuanhaoWu, Hiren Patel, Manoj Sachdev, Mahesh Tripunitara - Univ. of Waterloo

Coffee BreakTime: 10:00am - 10:30am | Room: Westminster Foyer

MONDAY, NOVEMBER 4


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Session 1B - New Perspectives of Timing, Power and IR DropsTime: 10:30am - 12:30pm | Room: Westminster IModerator:

Tsung-Wei Huang - Univ. of Utah

Thissessioncoversthestate-of-the-artadvancesintiming,power,andIRdropanalysis.Itfocusesonthepowergridoptimizationforelectromigration,machine-learningbasedIRdropestimation,advancedwake-updelayminimization,andnewclockgatingtechniques.

*1B.1 PowerGridFixingforElectromigration-InducedVoltageFailuresZahiMoudallal - Univ. of TorontoValeriy Sukharev - Mentor, A Siemens BusinessFarid N. Najm - Univ. of Toronto

1B.2 “IncPIRD’’:FastLearning-BasedPredictionofIncrementalIRDropChia-TungHo, Andrew Kahng - Univ. of California, San Diego

1B.3 AllocationofStateRetentionRegistersBoostingPracticalApplicabilitytoPowerGated Circuits

GyounghwanHyun, Taewhan Kim - Seoul National Univ.

1B.4 Flip-FlopStateDrivenClockGating:Concept,Design,andMethodologyGyounghwanHyun, Taewhan Kim - Seoul National Univ.

MONDAY, NOVEMBER 4


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Session 1C - Optimization Attacks Routing Challenges Time: 10:30am - 12:30pm | Room: Westminster IIModerator:

BeiYu-Chinese Univ. of Hong Kong.

Optimizationisneededinallareas.ThissessionintroducesnewoptimizationmethodsinClockNetworkSynthesis,inter-andintra-chiprouting,andFPGAs.Thefirstpaperdiscussesmachinelearningbasedoptimizationforclocktreesynthesis.Thenextpaperpresentslinearprogrammingandgraphbasedglobalinter-chiprouting.Thethirdpaperproposesinterconnectoptimizationmethod while considering key designs constraints. Finally, the last paper is on using Lagrangian relaxationbasedtimedivisionmultiplexingoptimizationformulti-FPGAsystems.

1C.1 GAN-CTS:AGenerativeAdversarialFrameworkforClockTreePredictionand Optimization

Yi-ChenLu, Jeehyun Lee, Anthony Agnesina - Georgia Institute of TechnologyKambiz Samadi - Qualcomm Technologies, Inc.Sung Kyu Lim - Georgia Institute of Technology

1C.2 Obstacle-AwareGroup-BasedLength-MatchingRoutingforPre-AssignmentArea-I/O Flip-ChipDesigns

Yu-HsuanChang,Hsiang-TingWen,Yao-WenChang - National Taiwan Univ.

1C.3 GlobalInterconnectOptimizationSiadDaboul, Stephan Held - Univ. of BonnBento Natura - London School of Economics and Political ScienceDanielRotter - Univ. of Bonn

1C.4 LagrangianRelaxation-BasedTime-DivisionMultiplexingOptimizationforMulti-FPGA Systems

Chak-WaPui,EvangelineYoung - Chinese Univ. of Hong Kong

MONDAY, NOVEMBER 4


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Organizer:Wei Zhang - Hong Kong Univ. of Science and Technology YunLiang - Peking Univ.

Field-Programmable Gate Arrays (FPGAs) are increasingly used as hardware accelerators to implement varioustasksduetotheiradvantagesoflowpowerandmassiveparallelism.However,conventionalmanualimplementationofRTLcodesonFPGAsrequiresdeepcomprehensionofthehardwarearchitectureandgreatefforts.Inordertolowertheprogrammingbarrierandimprovethedesignefficiency,itiscrucialtodevelopthehigh-leveldesignautomationframeworkfortheFPGAbaseddesign,suchashigh-levelsynthesis,automaticdesignoptimizationframework,etc.However,italsobringsnewchallengestothemappingflowandtoolsupportfortheFPGAimplementation.Atthesametime,themachinelearningworkloads,especiallythedeepneuralnetworks(DNNs)areincreasinglydeployedonFPGAforacceleration,whereDNN’sdeepernetworkanddiversebranchstructuresposegreatchallengesforanefficientFPGAimplementation.Thissessionpresentssixtalksandaddressestheabovechallengesfromdifferentperspectives.Ononehand,ithighlightsnewapproachesfortheautomaticcodegeneration,andsynthesisflowsfortheefficientmappingofhigh-leveldesignsonFPGA.Ontheotherhand,itpresentsseveralDNNacceleratordesignsonFPGAwithnoveldesignoptimizationtechniques.

1D.1 Zac:TowardsAutomaticOptimizationandDeploymentofQuantizedDeepNeural NetworksonEmbeddedDevices

Qingcheng Xiao, YunLiang - Peking Univ.

1D.2 Energy-DrivenDataflowOptimizationforDNNonFPGAQi Sun, Tinghuan Chen - Chinese Univ. of Hong KongJin Miao - Cadence Design System, Inc.BeiYu - Chinese Univ. of Hong Kong

1D.3 TowardsIn-CircuitTuningofDeepLearningDesignsZhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J.E. Wilton, WayneLuk - Imperial College

1D.4 NAIS:NeuralArchitectureandImplementationSearchanditsApplicationsin AutonomousDriving

Cong Hao - Univ. of Illinois at Urbana-ChampaignYaoChen - Advanced Digital Sciences CenterDemingChen - Univ. of Illinois at Urbana-ChampaignAtifSarwari,DarylSew - XMotors.aiAshutosh Dhar - Univ. of Illinois at Urbana-ChampaignDongdong Fu - XMotors.aiJinjun Xiong - IBM Corp.Wen-mei Hwu - Univ. of Illinois at Urbana-ChampaignJunli Gu - XMotors.ai

1D.5 WhatYouSimulateIsWhatYouSynthesize:DesigningaProcessorCorefromC++ Specifications

Simon Rokicki, Joseph Paturel - Univ Rennes, InriaDavide Pala, OlivierSentieys - Univ. of Rennes 1

1D.6 Hi-ClockFlow:Multi-ClockDataflowAutomationandThroughputOptimizationinHigh- LevelSynthesis

Tingyuan Liang, Jieru Zhao, Liang Feng - Hong Kong Univ. of Science and TechnologySharad Sinha - Indian Institute of Technology, GoaWeiZhang - Hong Kong Univ. of Science and Technology

Special Session 1D - Design Automation and DNN for FPGAsTime: 10:30am - 12:30pm | Room: Westminster III

MONDAY, NOVEMBER 4


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Additional Meeting - ACM Student Research Competition Poster SessionTime: 11:30am - 1:30pm | Room: Westminster FoyerSponsoredbyMicrosoftResearch,theACMStudentResearchCompetitionisaninternationallyrecognizedvenueenablingundergraduateandgraduatestudentswhoareACMmembersto:

•Experiencetheresearchworld—formanyundergraduatesthisisafirst!

• Share research results and exchange ideas with other students, judges, and conference attendees

• Rub shoulders with academic and industry luminaries

•Understandthepracticalapplicationsoftheirresearch

•Perfecttheircommunicationskills

•ReceiveprizesandgainrecognitionfromACMandthegreatercomputingcommunity.

TheACMSpecialInterestGrouponDesignAutomation(ACMSIGDA)isorganizingsuchaneventinconjunctionwiththeInternationalConferenceonComputerAidedDesign(ICCAD).Authorsofacceptedsubmissionswillgettravelgrantsupto$500fromACM/MicrosoftandICCADregistrationfeesupportfromSIGDA.Theeventconsistsofseveralrounds,asdescribedathttp://src.acm.org/andhttp://www.acm.org/student-research-competition,whereyoucanalsofindmoredetailsonstudenteligibilityandtimeline.

Sponsored by:

MONDAY, NOVEMBER 4


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Lunch Time: 12:30pm - 1:30pm | Room: Legacy BallroomJoinfellowattendeesforlunchinLegacyBallroom.

Session 2A - Accelerating Neural NetworksTime: 1:45pm - 3:45pm | Room: Westminster IVModerator:

Hai Helen Li - Duke Univ.

Thissessionincludesfourpapersondesigningneuralnetworkaccelerators.ThefirstpaperproposesamodularDNNacceleratorgeneratorwithconfigurabledataflowandanNN-to-architecturemappertogenerateenergy-efficientdesigns.Thesecondpaperpresentsanacceleratorfortheinstancenormalizationlayeringenerativeneuralnetworks.ThethirdpaperdesignsaCNNacceleratorframeworkthatcanreduceoff-chipmemoryaccessesforsuper-resolutiontaskswithlargefeaturemaps.ThelastpaperdevelopsanFPGA-basedacceleratorforauto-regressiveconvolutionalneuralnetworkstoaccelerateaudiosynthesis.

2A.1 MAGNet:AModularAcceleratorGeneratorforNeuralNetworksRangharajanVenkatesan,YakunSophiaShao - NVIDIA Corp.Miaorong Wang - Massachusetts Institute of TechnologyJasonClemons,SteveDai,MatthewFojtik,BenKeller,AliciaKlinefelter, Nathaniel Pinckney - NVIDIA Corp.Priyanka Raina - Stanford Univ.YanqingZhang,BrianZimmer,WilliamJ.Dally,JoelEmer,StephenW.Keckler,BrucekKhailany - NVIDIA Corp.

2A.2 ACG-Engine:AnInferenceAcceleratorforContentGenerativeNeuralNetworksHaoboXu - Institute of Computing Technology, Chinese Academy of Sciences YingWang,YujieWang,JiajunLi,BoshengLiu,YinheHan - Institute of Computing Technology, Chinese Academy of Sciences

2A.3 eSRCNN:AFrameworkforOptimizingSuper-ResolutionTasksonDiverseEmbedded CNNAccelerators

YoungbeomJung,YeongjaeChoi,JaehyeongSim,Lee-SupKim - Korea Advanced Institute of Science and Technology

2A.4 FastWave:AcceleratingAutoregressiveConvolutionalNeuralNetworksonFPGAShehzeenS.Hussain, Mojan Javaheripi, Paarth Neekhara, Ryan Kastner, Farinaz Koushanfar - Univ. of California, San Diego

MONDAY, NOVEMBER 4


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Session 2B - Emerging Applications in SynthesisTime: 1:45pm - 3:45pm | Room: Westminster IModerator:

Alexandre Levisse - Swiss Federal Institute of Technology

Thissessionshowsnew,emerging,applicationsinsynthesis.Thefirstpaperpresentsapathbalancingmappingalgorithmforsuperconductingelectronics.Thesecondpaperbuildsagenericsynthesis framework using a large set of memristor-based Boolean operators. The third paper studiestheconditionsforasetofthresholdfunctionstoberealizedwithacommonweightvector,enablingahighercompressionratioforlibrariesofthresholdfunctions.

2B.1 ADynamicProgramming-Based,PathBalancingTechnologyMappingAlgorithm TargetingAreaMinimization

GhasemPasandi, Massoud Pedram - Univ. of Southern California

2B.2 AGeneralLogicSynthesisFrameworkforMemristor-BasedLogicDesignZhenhuaZhu, Mingyuan Ma, Jialong Liu - Tsinghua Univ.Liying Xu - Peking Univ.Xiaoming Chen - Chinese Academy of SciencesYuchaoYang - Peking Univ.YuWang,HuazhongYang - Tsinghua Univ.

2B.3 SearchingParallelSeparatingHyperplanesforEffectiveCompressionofThresholdLogic Networks

Siang-YunLee, Nian-Ze Lee, Jie-Hong Roland Jiang - National Taiwan Univ.

MONDAY, NOVEMBER 4


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Session 2C - Approximation in Behavioral Specifications, Neural Network Design, and Stochastic ComputingTime: 1:45pm - 3:45pm | Room: Westminster IIModerator:

Hai Zhou - Northwestern Univ.

Approximationasameansforoptimizingpower,energy,andsecurityinsystemsisaddressedinthepapersinthissession.Thefirstpaperintroducesthenotionofapproximationwithinthehigh-levelsynthesisflow.Thesecondpaperproposesamethodforincrementaltrainingofneuralnetworksusingapproximatemultipliers.Thethirdpaperpresentsatechniquefordesignspaceexplorationfor approximate neural networks without expensive retraining. Finally, the last paper of the session introducesamethodforleveragingrandomnessindesigningsecurestochasticsystems.

2C.1 ApproximatingBehavioralHWAcceleratorsThroughSelectivePartialExtractionsOnto SynthesizablePredictiveModels

SiyuanXu, Benjamin Carrion Schaefer - Univ. of Texas at Dallas

2C.2 INA:IncrementalNetworkApproximationMethodforLimitedPrecisionDeepNeural Networks

ZheyuLiu, Kaige Jia - Tsinghua Univ.Weiqiang Liu - Nanjing Univ. of Aeronautics and AstronauticsQiWei,FeiQiao,HuazhongYang - Tsinghua Univ.

2C.3 ALWANN:AutomaticLayer-WiseApproximationofDeepNeuralNetworkAccelerators withoutRetraining

VojtechMrazek, Zdenek Vasicek, Lukas Sekanina - Brno Univ. of TechnologyMuhammadAbdullahHanif,MuhammadShafique - Vienna Univ. of Technology

2C.4 ExploitingRandomnessinStochasticComputingPaishun Ting, JohnHayes - Univ. of Michigan

MONDAY, NOVEMBER 4


21

Special Session 2D - 2019 CAD Contest at ICCADTime: 1:45pm - 3:45pm | Room: Westminster IIIModerator:

Mark Po-Hung Lin - National Chiao Tung Univ.

Organizers:Ulf Schlichtmann - Tech. Univ. of MunichSabya Das - Synopsys, Inc.Ing-Chao Lin - National Cheng Kung Univ.Mark Po-Hung Lin - National Chiao Tung Univ.

TheCADContestatICCAD(https://iccad-contest.org/)isachallenging,multi-month,research&developmentcompetition,focusingonadvanced,real-worldproblemsinthefieldofElectronicDesignAutomation(EDA).ContestantscanparticipateinoneormoreproblemsprovidedbyEDA/IC industry. The winners will be awarded at an ICCAD special session dedicated to this contest. Since2012,theCADContestatICCADhasbeenattractingmorethanahundredteamsperyear,fosteringproductiveindustry-academiacollaborations,andleadingtohundredsofpublicationsintop-tierconferencesandjournals.ThecontestkeepsenhancingitsimpactandboostsEDAresearch.This session will give an overview of the CAD Contest at ICCAD, present the three contest problems of 2019 CAD Contest to the EDA community, announce the contest results, and introduceaverifiedrobustacademicdesignflowfromlogicsynthesistophysicaldesign.Thesessionwillcontainfivepresentations:Thecontestchairwillfirstgiveabriefintroductiontothecontest.Afterwards,threetopicchairswillintroduceeachofthecontestproblemsandbenchmarksuites, announce the contest results, and present awards to the winners. The topic chairs will also play some video clips provided by Top-X teams which present key ideas and algorithms of their solutionstothecontestproblems.Finally,theDesignAutomationTechnicalCommittee(DATC)ofIEEECEDAwillintroduceareferencedesignflowinacademia.

2D.1 Overviewof2019CADcontestatICCADUlfSchlichtmann - Tech. Univ. of MunichSabya Das - Synopsys, Inc.Ing-Chao Lin - National Cheng Kung Univ.Mark Po-Hung Lin - National Chiao Tung Univ.

2D.2 2019CADContest:LogicRegressiononHighDimensionalBooleanSpaceChing-YiHuang,Chi-An(Rocky)Wu,Tung-YuanLee,Chih-Jen(Jacky)Hsu,Kei-YongKhoo - Cadence Design Systems, Inc.

2D.3 2019CADContest:System-LevelFPGARoutingwithTimingDivisionMultiplexing Technique

Yu-HsuanSu - Synopsys Taiwan Co., Ltd.Richard Sun, Pei-Hsin Ho - Synopsys, Inc.

2D.4 ICCAD2019LEF/DEFBasedGlobalRoutingContestAlexander Volkov, Sergei Dolgov - Mentor, A Siemens BusinessLutong Wang, BangqiXu - Univ. of California, San Diego

2D.5 DATCRDF-2019:TowardsaCompleteAcademicReferenceDesignFlowJianli Chen - Fuzhou Univ.Iris Hui-Ru Jiang - National Taiwan Univ.JinwookJung - IBM T. J. Watson Research CenterAndrew B. Kahng - Univ. of California, San DiegoVictor N. Kravets - IBM T. J. Watson Research CenterYih-LangLi,Shih-TingLin - National Chiao Tung Univ.Mingyu Woo - Univ. of California, San Diego

MONDAY, NOVEMBER 4


22

Coffee BreakTime: 3:45pm - 4:15pm | Room: Westminster Foyer

Moderator:Deliang Fan - Univ. of Central Florida

Thissessionisdevotedtothecomputingandsecurityapplicationsofmemorydevices.Thefirstpaper focuses on a novel design for bit-wise data processing in dynamic random memory (DRAM) thatexploitsahybridsense-ampdesigntoextendtherangeoffunctionsthatcanbeexecutedin one clock cycle in memory. The second paper proposes a neuromorphic inference accelerator basedonresistiveswitchingmemoriesthatcanefficientlyrunmodelswithvariableweightprecision.Thelastpaperinthesessionproposesanovelwaytosanitizeflashmemorieswithouttheneedforexpliciterasecyclesorencryption,thusleadingtoreducedoverheadandimprovedendurance.

3A.1 ReDRAM:AReconfigurableProcessing-in-DRAMPlatformforAcceleratingBulk Bit-WiseOperations

Shaahin Angizi, DeliangFan - Univ. of Central Florida

3A.2 AnAgilePrecision-TunableCNNAcceleratorBasedonReRAMYintao He,YingWang,YongchenWang,HuaweiLi,XiaoweiLi - Chinese Academy of Sciences

3A.3 TowardInstantaneousSanitizationthroughDisturbance-InducedErrorsandRecycling ProgrammingOver3DFlashMemory

Wei-Chen Wang - Macronix International Co., Ltd. & National Taiwan Univ.Ping-Hsien Lin, Yung-ChunLi - Macronix International Co., Ltd.Chien-Chung Ho - National Chung Cheng Univ.Yu-MingChang - National Taiwan Univ.Yuan-HaoChang - Academia Sinica

Session 3A - Processing in Memory and Secure Memory DesignTime: 4:15pm - 5:45pm | Room: Westminster IV

MONDAY, NOVEMBER 4


23

Session 3B - Efficient and Reliable DesignTime: 4:15pm - 5:45pm | Room: Westminster IModerator:

SebastianHuhn - Univ. of Bremen

Inmodernimplementationtechnologies,acrossalldesigncomponentsandcircuitfamilies,variation,aging,andotheranaloganddesign-timeuncertainpropertiesincreasinglyaffectourabilitytoquicklydesignreliablelogicandmemorycircuits.Thissessionpresentspaperscoveringefficientdesignmethodologiesforevaluatingtheimpactofcontinuousvariationsondiscretearchitecturalvalues,improvingthereliabilityofPCMmemories,andoptimizingthelayoutofanalogcircuits.

3B.1 EfficientUncertaintyModelingforSystemDesignviaMixedIntegerProgrammingZichangHe, Weilong Cui, Chunfeng Cui, Timothy Sherwood, Zheng Zhang - Univ. of California, Santa Barbara

3B.2 BagNet:BerkeleyAnalogGeneratorwithLayoutOptimizerBoostedwithDeepNeural Networks

KouroshHakhamaneshi,NickWerblun,PieterAbbeel,VladimirStojanović - Univ. of California, Berkeley

3B.3 Flipcy:EfficientPatternRedistributionforEnhancingMLCPCMReliabilityandStorage Density

MuhammadImran, Taehyun Kwon - Sungkyunkwan Univ. & Samsung Electronics Co., Ltd.JungMinYou,Joon-SungYang - Sungkyunkwan Univ.

MONDAY, NOVEMBER 4


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Session 3C - Emerging Technologies for Computing and NetworksTime: 4:15pm - 5:45pm | Room: Westminster IIModerator:

YanzhiWang - Northeastern Univ.

Thissessionfocusesonemergingconceptsandtechnologiesformulti-levelmemories,microfluidicbio-chips,andhybridNoCs.Thefirstpaperconsidersextendingtheenduranceofmulti-layerPCMsby reducing the number of RESET steps. The second paper aims to bridge the gap between the system-levelandphysicallayoutdesigninmicro-chipsbyintroducingasimulation-basedapproachforsynthesizingchannel-levelpressurizationprotocols.Thethirdpaperintroducesanenergy-delayoptimizationforthelasersourceofoptic-electronichybridNoCsviatask-mappingsourcegating.Together,thesenoveldirectionsshowenergyconsumptionreductionsaswellasdesignandhardwarespeed-upsfornext-generationcomputesystems.

3C.1 EnduranceEnhancementofMulti-LevelCellPhaseChangeMemoryCheongwonLee,YoungsooSong,YoungsooShin - Korea Advanced Institute of Science and Technology

3C.2 VOM:Flow-PathValidationandControl-SequenceOptimizationforMultilayered Continuous-FlowMicrofluidicBiochips

MengchuLi,Tsun-MingTseng,YanluMa - Technische Univ. MünchenTsung-YiHo - National Tsing Hua Univ.Ulf Schlichtmann - Technische Univ. München

3C.3 TaskMapping-AssistedLaserPowerScalingforOpticalNetwork-on-ChipsYuyangWang - Univ. of California, Santa BarbaraKwang-Ting Cheng - Hong Kong Univ. of Science and Technology

MONDAY, NOVEMBER 4


25

Special Session 3D - Design Automation for Power ElectronicsTime: 4:15pm - 5:45pm | Room: Westminster IIIModerator:

Jose Ayala - Complutense Univ.

Organizers:Miroslav Vasic - Univ. Politecnica de MadridJose Ayala - Complutense Univ.

DesignAutomationhasbecomeofstrategicimportanceforthePowerElectronicsSocietyasmodernhighlyintegrateddesignsaredealingwithmulti-physicsproblems,shorterdesigntimeandmultivariableoptimizationtoobtainhigherefficienciesandbetterpowerdensity.Additionally,thedevelopment and employment of Wide Bandgap devices (GaN and SiC based) has opened a set of design problems that has not been seen with Si based technology. All these trends are driving the needtorevisitdesigntoolsandcapabilities.

ThepurposeofthisspecialsessionistounderstandtheproblemsofDesignAutomationinPowerElectronicsandidentifymethodologiesthathavebeenusedsofarbyacademiaandindustry.Thefocus of the special session is to bring together the experts in both Power Electronics and Design Automationandhavethempresentingtheirperspectivesontheemergingneeds.

Theexpectedresultsare:

• AclearidentificationofthecommongroundandsynergybetweenPowerElectronicsand DesignAutomation

• An understanding where the limits of the current technology and tools are in Design AutomationforPowerElectronics

3D.1 DesignAutomationforPowerElectronicsAlanMantooth - Univ. of Arkansas

3D.2 TowardstheLimitsofGaNPowerElectronicsElisonMatioli - Ecole Polytechnique Fédérale de Lausanne (EPFL)

3D.3 Ultra-HighFidelityReal-TimeSimulationforPowerElectronicsand Microgrids:EmpoweringTestDrivenControlDevelopment

IvanCelanovic - Typhoon HIL

MONDAY, NOVEMBER 4

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Additional Meeting - AI / Machine Learning at CadenceTime: 5:45pm - 6:15pm | Room: Westminster I

Sponsored by:

Additional Meeting - Second Working Group Meeting on Logic Locking and Anti-Trojan SolutionsTime: 6:00pm - 10:00pm | Room: Westminster II & Westminster IIIOrganizers:

Swarup Bhunia - Univ. of FloridaYierJin - Univ. of FloridaJ. V. Rajendran - Texas A&M Univ.

ItwillbethesecondofthetwoWorkingGroupMeetingsonLogicLockingandAnti-TrojanSolutions,sponsoredbyDARPA.Thegoalofthismeetingistobringtogethermembersfromacademia,industryandgovernmenttodiscusscurrentchallengesandneedsinobfuscationandTrojancountermeasures;identifypromisingresearchdirectionsintheseareas;andsuggestappropriateactionsfortheDoDenterprise.ThefirstworkshopwassuccessfullyheldonJune5,2019,co-locatedwithDesignAutomationConference(DAC).

Networking ReceptionTime: 6:15pm - 6:45pm | Room: Westminster FoyerWhateveryourgoal,networkingreceptionsaretheperfectvenueforyoutoexpandyournetworkandkeepyouconnected!Joinustodaytocatchupwithyourcolleaguesanddiscusstheday’spresentationswiththeconferencepresenters.Allattendeesareinvited.

Machine Learning though not a new idea is currently one of the most hot topics in computer science. Cadence as a company which has lot of experience withcomputationaltasksisheavilyadoptingMachineLearningforvariousaspectsofEDAdesignmethodology.Inthepresentationareaswillbeshown,where Cadence is already using Machine Learning and ethe “inside” and “outside”usageofMLinCadencedesignflowwillbeexplained.CadenceasIPproviderisprovidingdesignandprocessorIP,whicharetargetedoncreationofML-assistedsystemsinthecloudandontheedge.Thedifferentrequirements

fortheIP,whichistargetedatdifferentusescenarioswillbeexplainedinthepresentation.

Biography:AntonKlotz,studiedTechnicalComputerScienceatMannheimUniv.inGermanyandjoinedCadenceDesignSystemsin2004asApplicationEngineer,wherehewasresponsibleforphysicalverificationandDFMforlargedigitaldesigns.In2015hebecameUniv.ProgramManagerfor the EMEA region. He is running Cadence Academic Network, which is the interface to all academia-related topics at Cadence, such as academic licenses, academic conference, internship program and government-funded research projects”

Sponsored by:

MONDAY, NOVEMBER 4TUESDAY SCHEDULE

27

Sponsored by:

Additional Meeting - ACM Student Research Competition Technical PresentationsTime: 6:45pm - 8:15pm | Room: Westminster ITheACMStudentResearchCompetitionallowsbothgraduateandundergraduatestudentstodiscuss their research with student peers, as well as academic and industry researchers, in an informalsetting,whileenablingthemtoattendICCAD.

ThissessionisthefinalroundofACMSRCatICCAD2019.Eachstudentwillpresentfor10minutes,followedbya2-minutequestionandanswerperiod.Thissessionwillbeattendedbytheevaluatorsandanyinterestedconferenceattendees.Thetopthreewinnersineachcategorywillbechosenbasedonthesepresentations.Theundergraduateandgraduatefinalistswillbeeligibletocompete in the ACM SRC Grand Finals to be held in June 2020.

Moredetailscanbefoundat:

https://www.sigda.org/sigda-events/src/

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TUESDAY SCHEDULE

8:30 - 10:00amSession 4A: Quantum Computing Location: Westminster IV

Session 4B: FPGA Emulation and Optimization Location: Westminster I

Special Session 4C: Placement for Heterogeneity Location: Westminster II

Special Session 4D: Advanced Logic Locking Techniques for Hardware IP Protection Location: Westminster III


10:30am - 12:00pmSession 5A: System-Level Attacks and Protection Location: Westminster IV

Session 5B: Pushing the Frontiers of Synthesis Location: Westminster I

Session 5C: Advanced Design Techniques for Manufacturability Location: Westminster II

Embedded Tutorial 5D: When Neural Networks Meet Hardware: The Princess, The Knight, and the Very Bad Dragon Location: Westminster III

12:00 - 12:30pmLunch Location: Legacy Ballroom

12:30 - 1:30pmCurrent Progress in Quantum Computing

Paul Nation - IBM T.J. Watson Research Center | Location: Legacy Ballroom

Sponsored by:

Sponsored by:

TUESDAY, NOVEMBER 5

29

TUESDAY SCHEDULE

1:45 - 3:45pmSession 6A: Algorithmic Innovations for Neural Computing Location: Westminster IV

Session 6B: Verified and Efficient Embedded Security Location: Westminster I

Session 6C: Overcoming the Complexity of System Level Validation Location: Westminster II

Special Session 6D: Quantum Computing - Resilience and Security Location: Westminster III


4:15 - 6:15pmSpecial Session 7A: The Road to Safe Autonomy: Neural Networks Meet Formal Reasoning Location: Westminster IV

Session 7B: Accelerator Design and Modeling Location: Westminster I

Session 7C: Combating Circuit Aging and Device Variability Location: Westminster II

Special Session 7D: Breaking the Ice Between Silicon Photonics Design and EDA: Electronic-Photonic Design Automation Location: Westminster III


6:45 - 8:30pmACM/SIGDA Member Meeting Location: Legacy Ballroom


design automation

Sponsored by:

Sponsored by:

Sponsored by:

TUESDAY, NOVEMBER 5

30


Session 4B - FPGA Emulation and OptimizationTime: 8:30am - 10:00am | Room: Westminster IModerator:

Daniel Große - Univ. of Bremen ThissessionincludesthreeimpactfulresearchexplorationsonFPGAemulationplatformsandoptimizations.Thefirstpaperpresentsanopen-sourceFPGAemulationplatformforin-storagecomputingthatcanprovideapubliclyavailableplatformforrapidevaluationforin-storageapplications.Thesecondpaperproposesaco-designapproachtoperformsparsematrix-vectormultiplicationefficientlyonaCPU-FPGAheterogeneousplatform.Thelastpaperexploresanautomatedmulti-acceleratorSoCgenerationtoolchain,whichcanperformrapidandaccuratefull-systemsimulationofSoCswithuser-specifiedaccelerators.

*4B.1 AnalyzingandModelingIn-StorageComputingWorkloadsOnEISC—AnFPGA-Based System-LevelEmulationPlatform

ZhenyuanRuan, Tong He, Jason Cong - Univ. of California, Los Angeles

4B.2 ReDESK:AReconfigurableDataflowEngineforSparseKernelsonHeterogeneous Platforms

KaiLu,ZhaoshiLi,LeiboLiu,JiaweiWang,ShouyiYin,ShaojunWei - Tsinghua Univ.

4B.3 Centrifuge:EvaluatingFull-SystemHLS-GeneratedHeterogenous-AcceleratorSoCs usingFPGA-Acceleration

QijingHuang,ChristopherYarp,SagarKarandikar,NathanPemberton,BenjaminBrock - Univ. of California, BerkeleyLiang Ma - Politecnico di TorinoGuohao Dai - Tsinghua Univ.RobertQuitt,KrsteAsanovic,JohnWawrzynek - Univ. of California, Berkeley

Session 4A - Quantum ComputingTime: 8:30am - 10:00am | Room: Westminster IVModerator:

Rolf Drechsler - Univ. of BremenThissessionpresentsthreecontributionstotheemergingfieldofquantumcomputing.Thefirstoneprovidesanimplementationofadecisiondiagrampackagewithaparticularfocusontheefficientrepresentationofcomplexvalues.ThesecondpapershowshowlogicsynthesisforXOR-ANDgraphscangeneratequantumcircuitsandyieldbetterupperboundsonresourcesforfault-tolerantquantumcomputing.ThethirdoneliftstheconsiderationtoahigherlevelandprovidesanHDL-based synthesis approach for related reversible circuits that enables to generate components for quantumcircuitswithoutadditionalqubits.

*4A.1 HowtoEfficientlyHandleComplexValues?ImplementingDecisionDiagramsfor QuantumComputing

Alwin Zulehner, StefanHillmich, Robert Wille - Johannes Kepler Univ. Linz

4A.2 TheRoleofMultiplicativeComplexityinCompilingLowT-CountOracleCircuitsGiuliaMeuli, Mathias Soeken - École Polytechnique Fédérale de LausanneEarl Campbell - Univ. of SheffieldMartinRoetteler - Microsoft CorporationGiovanni De Micheli - École Polytechnique Fédérale de Lausanne

4A.3 TowardsHDL-BasedSynthesisofReversibleCircuitswithNoAdditionalLinesRobertWille - Johannes Kepler Univ. LinzMajid Haghparast - Islamic Azad Univ.Smaran Adarsh, Tanmay M - People’s Education Society Univ.

TUESDAY, NOVEMBER 5

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Session 4C - Placement for HeterogeneityTime: 8:30am - 10:00am | Room: Westminster IIModerator:

StephenYang - Xilinx Inc.

Inthisheterogeneousworld,placementisfarmorethanjust2Dgeometricoptimization.Issueslikemulti-dimensions,diversefabrics,heterogeneouscellsizesarechallenginginthislong-studiedarea.Inthissession,wehavethreepapersonplacementdealingwiththesechallenges.ThefirsttwoareonFPGAandthelastoneisonASICmacroplacement.Thefirstpaperextendsthe-state-of-the-artASIC placer ePlace to FPGA and achieves good performance. The second work is on 2.5D FPGA placementwithnon-linearoptimization,andthelastworkisonASICmacroplacementwithanovelsimulatedevolutionalgorithm.

4C.1 elfPlace:Electrostatics-BasedPlacementforLarge-ScaleHeterogeneousFPGAsWuxiLi,YiboLin,DavidZ.Pan - Univ. of Texas at Austin

4C.2 AnalyticalPlacementwith3DPoisson’sEquationandADMMBasedOptimizationfor Large-Scale2.5DHeterogeneousFPGAs

JianliChen - Fudan Univ. & Fuzhou Univ.Wenxing Zhu - Fuzhou Univ.JunYu - Fudan Univ.Lei He - Univ. of California, Los AngelesYao-WenChang - National Taiwan Univ.

4C.3 ANovelMacroPlacementApproachBasedonSimulatedEvolutionAlgorithmJai-MingLin,You-LunDeng,Ya-ChuYang,Jia-JianChen,Yao-ChiehChen - National Cheng Kung Univ.

TUESDAY, NOVEMBER 5

32


Special Session 4D - Advanced Logic Locking Techniques for Hardware IP ProtectionTime: 8:30am - 10:00am | Room: Westminster IIIModerator:

YierJin - Univ. of Florida

Organizers:YierJin - Univ. of FloridaSwarup Bhunia - Univ. of Florida

Theglobalizationofthesemiconductorsupplychainintroducesever-increasingsecurityandprivacyrisks.TwomajorconcernsareIPtheftthroughreverseengineeringandmaliciousmodificationofthedesign.Thelatterconcerninpartreliesonsuccessfulreverseengineeringofthedesignaswell.Developinglowoverheadlocking/camouflagingschemesthatcanresisttheever-evolvingstate-of-the-artattackshasbeenaresearchchallengeforseveralyears.Thisspecialsessionprovidesacomprehensiveoverviewofthestate-of-artwithrespecttolocking/camouflagingtechniques.

4D.1 APracticalApplicationofTrustThroughTechnologyYierJin,SwarupBhunia - Univ. of FloridaEric Breckenfeld - DARPASaverio Fazzari - Booz Allen Hamilton, Inc.KennethPlaks - DARPA

4D.2 ProtectingMicroelectronicsIP:Issues,Needs,andEmergingResearchDirectionsVipulJ.Patel - Air Force Research Lab

4D.3 SFLL-HLS:Stripped-FunctionalityLogicLockingMeetsHigh-LevelSynthesisMuhammadYasin,ChongzhiZhao,JeyavijayanRajendran - Texas A&M Univ.

4D.4 ResolvingtheTrilemmainLogicEncryptionHaiZhou,AminRezaei,YuanqiShen - Northwestern Univ.


TUESDAY, NOVEMBER 5

33


Session 5A - System-Level Attacks and ProtectionTime: 10:30am - 12:00pm | Room: Westminster IVModerator:

BoYuan - Rutgers Univ.

Althoughpowerful,theautonomoussystemsalsoexposetoanemergingphysicalattackingspacethroughsoftware/hardwareside-channels.Thissectionincludespapersthatcharacterize,analyze,anddefendagainsttheseattackscenariosandprovidenovelanduniquesolutions.Thefirstpaperproposesanovelmetricforleakageassessmentofpowerbasedsidechannelattacksoncryptographicimplementations.Thesecondpaperpresentsanautomatedsystemtopreciselyandefficientlyrepositiontheprobewhenperformingrepeatedmeasurements.Thethirdpaperproposesaconsolidatedruntime-configurablehardware-assistedsecuritymechanism,whichsupportspropersecuritylevelaccordingtothetrade-offbetweensecurityrequirementandperformanceoverhead.

5A.1 HolisticPowerSide-ChannelLeakageAssessment:TowardsaRobustMultidimensional Metric

AlricAlthoff, Jeremy Blackstone, Ryan Kastner - Univ. of California, San Diego

5A.2 AutomatedProbeRepositioningforOn-DieEMMeasurementsBastianRichter - Ruhr Univ. BochumAlexander Wild - NXP SemiconductorsAmir Moradi - Ruhr Univ. Bochum

5A.3 CHASE:AConfigurableHardware-AssistedSecurityExtensionforReal-TimeSystemsGhadaDessouky, Shaza Zeitouni, Ahmad Ibrahim - Technische Univ. DarmstadtLucas Davi - Univ. of Duisburg-EssenAhmad-Reza Sadeghi - Technische Univ. Darmstadt

TUESDAY, NOVEMBER 5

34


Session 5B - Pushing the Frontiers of SynthesisTime: 10:30am - 12:00pm | Room: Westminster IModerator:

Mathias Soeken - Swiss Federal Institute of Technology

Thissessionprovidesanewperspectivetosynthesis.ThefirstpaperproposesanewFPGAarchitectureandmappingflow,combiningthecompletenessofLUTandtheexpressivenessofthresholdlogicfunctions.Thesecondpaperproposesadeepreinforcementlearningschedulingsolutionforhigh-levelsynthesisinFPGA.Thethirdpaperintroducesanovelcanonicalsententialdecisiondiagramvariant,showingsmallerrepresentationthanotherdecisiondiagrams.

5B.1 EmbeddingBinaryPerceptronsinFPGAtoImproveArea,Power,andPerformanceAnkitWagle, Elham Azari, Sarma Vrudhula - Arizona State Univ.

5B.2 ADeep-Reinforcement-Learning-BasedSchedulerforFPGAHLSHongzhengChen, Minghua Shen - Sun Yat-sen Univ.

5B.3 TaggedSententialDecisionDiagrams:CombiningStandardandZero-Suppressed CompressionandTrimmingRules

Liangda Fang - Jinan Univ.Biqing Fang, Hai Wan - National Sun Yat-sen Univ.Zeqi Zheng - Jinan Univ.Liang Chang - Guilin Univ. of Electronic TechnologyQuanYu - Qiannan Normal Univ. for Nationalities

TUESDAY, NOVEMBER 5

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Session 5C - Advanced Design Techniques for ManufacturabilityTime: 10:30am - 12:00pm | Room: Westminster IIModerator:

Takashi Sato - Kyoto Univ.

Thissessionintroducesthelatestprogressindesignformanufacturabilitytechniques.Thefirstpaperproposestiming-awarefillinsertionthatsimultaneouslyconsidersthetotalcapacitanceandmetaldensityconstraintsforbettertimingandforlesscrosstalk.ThesecondpaperpresentsanILPapproachandamoreefficientbinaryILPapproachforcutredistributionintwo-dimensionaldirectedself-assembly.Thethirdpapercriticallyanalyzesexistingworksonmachinelearning-basedlithographichotspotdetectionandpinpointstheircommonmisconceptions.

5C.1 Timing-AwareFillInsertionswithDesign-RuleandDensityConstraintsTingshen Lan, Xingquan Li - Fuzhou Univ.JianliChen - Fudan Univ. & Fuzhou Univ.JunYu - Fudan Univ.Lei He - Univ. of California, Los AngelesSenhua Dong - Huada Empyrean Software Co., LtdWenxing Zhu - Fuzhou Univ.Yao-WenChang - National Taiwan Univ.

5C.2 Graph-andILP-BasedCutRedistributionforTwo-DimensionalDirectedSelf-AssemblyZhan-LingWang,Yao-WenChang - National Taiwan Univ.

5C.3 MachineLearning-BasedHotspotDetection:Fallacies,PitfallsandMarchingOrdersGauravRajavendraReddy - Univ. of Texas at DallasKareem Madkour - Mentor, A Siemens BusinessYiorgosMakris - Univ. of Texas at Dallas

TUESDAY, NOVEMBER 5

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Embedded Tutorial 5D - When Neural Networks Meet Hardware: The Princess, The Knight, and the Very Bad Dragon Time: 10:30am - 12:00pm | Room: Westminster IIIModerator:

Qinru Qiu - Syracuse Univ.

Organizer:Jingtong Hu - Univ. of Pittsburgh

Hardwareaccelerationofneuralnetworks,whichcombinestheperformanceofneuralnetworksandthespeedofdedicatedhardware,hasbeenwidelyadoptedinmanyapplications.However,themarriagebetweenhardwareandneuralnetworksisnotasstraightforwardasitseems.Carelessimplementationswithoutconsideringvarioushardwarerelatedissueswouldeasilyleadtodesignswith inferior speed, performance, or even reliability. In this tutorial, three talks will cover the most criticalpartsinthedesignflowofhardwareacceleratorsofneuralnetworks.Specifically,thefirsttalkwilldiscusshardware-awareneuralarchitecturesearch;Thesecondtalkwillintroducehardware-awareneuralarchitecturecompression;Thethirdtalkwillcoverhardware-defect-tolerantneural networks. Together they convey an important message that neural network and hardware needstobeco-designedandco-optimizedthroughoutthedesignflowformaximumspeed,performance and reliabilty.

5D.1 Hardware-AwareNeuralArchitectureSearchQingLu, Weiwen Jiang - Univ. of Notre DameJingtong Hu - Univ. of PittsburghYiyuShi - Univ. of Notre Dame

5D.2 HowtoObtainandRunLightandEfficientDeepLearningNetworksFanChen,WeiWen,LinghaoSong,JingchiZhang,HaiLi,YiranChen - Duke Univ.

5D.3 MakingtheFault-ToleranceofEmergingNeuralNetworkAcceleratorsScalableTaoLiu - Florida International Univ.Wujie Wen - Lehigh Univ.

LunchTime: 12:00pm - 12:30pm | Room: Legacy BallroomJoinfellowattendeesforlunchinLegacyBallroom.

TUESDAY, NOVEMBER 5

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CEDA Invited Luncheon Talk: Current Progress in Quantum Computing Time: 12:30pm - 1:30pm | Room: Legacy Ballroom

Sponsored by:

Speaker:PaulNation- IBM T.J. Watson Research Center

Sincethefirstpubliclyavailablequantumcomputerwasintroducedby IBM in 2016, we have seen an explosion of interest in exploring

theapplicationofquantumcomputingsystemstoreal-worldproblems.Althoughstillintheirinfancy, quantum computers have already been applied in a variety of disciplines such as quantum chemistry,machinelearning,andoptimization.Inthistalkwegiveabriefoverviewofquantumcomputingbeforedetailingthecurrentstateoftheartinquantumcomputinghardwareandsoftware.Wewillseehowthesesystemsarehelpingtotrainusersforthetimewhenthereisadefinitiveadvantagetorunningcertaintasksonaquantumcomputer.

Biography:PaulNationisatheoreticalphysicistfocusingonnumericalmethodsforopenquantumsystemsandhigh-fidelityquantumoperationsinsuperconductingquantumsystems.Hereceived his PhD in 2010 from Dartmouth College, and was a Postdoctoral Research at RIKEN in Japan.BeforejoiningIBMQuantumhewasanAssistantProfessoratKoreaUniversity,andaStaffPhysicist at Northrup Grumman.

TUESDAY, NOVEMBER 5

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Session 6A - Algorithmic Innovations for Neural ComputingTime: 1:45pm - 3:45pm | Room: Westminster IVModerator:

Xuan ‘Silvia’ Zhang - Washington Univ.

Thissectionpresentsfourinterestingpapersatthealgorithmicaspectforneuralcomputing.Thefirstpaperlooksatmethodstoacceleratetensordecompositiononresource-constraineddevices.Thesecondpaperpresentsabrain-inspiredhyper-dimensionalcomputationalplatformthatistrained via a semi-supervised learning algorithm. The third paper proposes a novel disturbance-basedmethodtoencrypttheweightsthatarestoredinnon-volatilememorytoachievesecurein-memoryneuralnetworkcomputing.Finally,thelastpapershowsamethodologyforneuralarchitecturesearchwithvaryingbitprecisiontodesignenergyefficientarchitectures.

6A.1 TuckerTensorDecompositiononFPGAKaiqiZhang, Xiyuan Zhang, Zheng Zhang - Univ. of California, Santa Barbara

6A.2 SemiHD:Semi-SupervisedLearningUsingHyperdimensionalComputingMohsenImani - Univ. of California, San DiegoSamuel Bosch - École Polytechnique Fédérale de LausanneMojan Javaheripi, Bita Darvish Rouhani, Xinyu Wu, Farinaz Koushanfar, Tajana Rosing - Univ. of California, San Diego

6A.3 EnablingSecurein-MemoryNeuralNetworkComputingbySparseFastGradient Encryption

YiCai - Tsinghua Univ.Xiaoming Chen - Chinese Academy of SciencesLuTian,YuWang,HuazhongYang - Tsinghua Univ.

6A.4 MixedPrecisionNeuralArchitectureSearchforEnergyEfficientDeepLearningChengyue Gong, ZixuanJiang,DilinWang,YiboLin,QiangLiu,DavidZ.Pan - Univ. of Texas at Austin

TUESDAY, NOVEMBER 5

39All speakers are denoted in bold | * denotes Best Paper Candidate

Session 6B - Verified and Efficient Embedded SecurityTime: 1:45pm - 3:45pm | Room: Westminster IModerator:

Xiaolong Guo - Kansas State Univ.

Thissessionpresentsverifiedandefficienttechniquestoenhancethesecurityofembeddedsystems.Thefirstpaperproposestouseverifiedremoteattestationforsecuritysoftwareupdates,erasureandresets.Thesecondpaperpresentsamulti-versionconcurrencycontrolonintermittentsystems. The third paper explores the reverse engineering approach to understand GPU memory resourceallocation.Thelastpaperdevelopsanefficientgeneticalgorithm-basedframeworktospeed up logic unlocking.

6B.1 PURE:UsingVerifiedRemoteAttestationtoObtainProofsofUpdate,ResetandErasure inLow-EndEmbeddedSystems

IvanDeOliveiraNunes - Univ. of California, IrvineKarim Eldefrawy - SRI InternationalNorrathepRattanavipanon,GeneTsudik - Univ. of California, Irvine

6B.2 MultiversionConcurrencyControlonIntermittentSystemsWei-MingChen - National Taiwan Univ. & Academia SinicaYi-TingChen - National Taiwan Univ.Pi-Cheng Hsiu - Academia SinicaTei-Wei Kuo - National Taiwan Univ.

6B.3 UnderstandingandExploitingtheInternalsofGPUResourceAllocationforCritical Systems

AlejandroJ.Calderón - Univ. Politècnica de Catalunya & Ikerlan Technology Research CentreLeonidas Kosmidis - Barcelona Supercomputing CenterCarlos F. Nicolás - Ikerlan Technology Research CentreFrancisco J. Cazorla - Barcelona Supercomputing CenterPeio Onaindia - Ikerlan Technology Research Centre

*6B.4 GenUnlock:AnAutomatedGeneticAlgorithmFrameworkforUnlockingLogic Encryption

HuiliChen, Cheng Fu, Jishen Zhao, Farinaz Koushanfar - Univ. of California, San Diego

TUESDAY, NOVEMBER 5


Session 6C - Overcoming the Complexity of System Level ValidationTime: 1:45pm - 3:45pm | Room: Westminster IIModerator:

Christopher Harris - Auburn Univ.

SystemlevelvalidationisgettingmorecomplicatedformodernSoCswithincreasingnumberofembeddedcores.Thissessionpresentsrecentadvancementsinthefieldforovercomingthegrowing complexity challenges. The session includes four papers that address the challenges in differentaspects,includingtwopapersinemulation,oneinmulti-corememorycoherence,andanovelapproachtoconvertacombinationalcircuitintoasequentialone.

6C.1 ReducingCompilationEffortinCommercialFPGAEmulationSystemsUsingMachine Learning

AnthonyAgnesina - Georgia Institute of TechnologyEtienneLepercq,JoseEscobedo - Synopsys, Inc.Sung Kyu Lim - Georgia Institute of Technology

6C.2 GoldenGate:BridgingTheResource-EfficiencyGapBetweenASICsandFPGA Prototypes

AlbertMagyar, David Biancolin, Jack Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanović - Univ. of California, Berkeley

6C.3 Spec&Check:AnApproachtotheBuildingofShared-MemoryRuntimeCheckersfor MulticoreChipDesignVerification

Marleson Graf, Olav P. Henschel, Rafael P. Alevato, LuizC.V.dosSantos - Federal Univ. of Santa Catarina

6C.4 Time-FrameFolding:BacktotheSequentialityPo-ChunChien, Jie-Hong Roland Jiang - National Taiwan Univ.

TUESDAY, NOVEMBER 5


Special Session 6D - Quantum Computing - Resilience and Security Time: 1:45pm - 3:45pm | Room: Westminster IIIModerator:

Rolf Drechsler - Univ. of Bremen

Organizers:Swaroop Ghosh - Pennsylvania State Univ.AnupamChattopadhyay - Nanyang Technological Univ.

TheNoisyIntermediateScaleQuantum(NISQ)computerssufferfromdecoherenceandgateerrors.Quantumerrorcorrection(QEC)e.g.,Shorcode,Steanecode,Surfacecodeincreasestheoverheadsubstantiallye.g.,20Xinsurfacecode.AdvancementinEDAisrequiredtoenhancetheresiliencebyexploringtrade-offopportunitiespresentatvariouslevelsofdesignhierarchy,accommodatewide variety of qubits and their system architecture. A resilient quantum computer presents a threattoconventionalcrypto-systemssinceitcansolvecombinatoriallyhardproblemssuchas,factorization.Post-QuantumCryptography(PQC)isbeingdevelopedtoaddressthisissuehowevertheirrealdeploymentinawiderangeofcomputingdevicesfacesseveralchallengesthatneedtoberesolved.QuantumsystemsalsobringnewsecuritypromisesintermsofQuantumKeyDistribution(QKD),quantum-enabledsecurityprimitivese.g.,TRNG.Thisspecialsessionthatincludes5invitedtalks by speakers from academia, industry and government agency, will provide in-depth treatment of both sides of the coin namely the resilience and security of NISQ era quantum computers includingPQC/QKD.Talk-1willdescribeaholisticquantumcomputerarchitectureforinterfacingwithIntel’squantumcomputer.Talk-2willpresentNASA’sperspectiveonalgorithmictodeviceoptimizationforresilience.Talk-3willintroduceasingle-passqubitallocationandtechnologymappingflowfornoiseresilience.Talk-4willdiscussthesecurityofquantumcryptography.Talk-5willcovernewapproachesinlattice-basedpost-quantumcryptography.

6D.1 QuantumComputing:FromQubitstoQuantumAcceleratorKoen Bertels - Delft Univ. of Technology

6D.2 ANASAPerspectiveonQuantumComputingEleanorRieffel,ZhihuiWang - NASA Ames Research Center

6D.3 IntegratedQubitAllocationandTechnologyMappingforNISQComputingDebjyotiBhattacharjee - Nanyang Technological Univ.Abdullah-Ash Saki, Mahabubul Alam - Pennsylvania State Univ.AnupamChattopadhyay - Nanyang Technological Univ.SwaroopGhosh - Pennsylvania State Univ.

6D.4 SecurityofQuantumCryptographyAnindita Banerjee - QuNu LabsMT Karunakaran - QuNu labs

6D.5 EngineeringLattice-BasedPost-QuantumCryptographySujoySinhaRoy - Univ. of Birmingham

TUESDAY, NOVEMBER 5

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Special Session 7A - The Road to Safe Autonomy: Neural Networks Meet Formal ReasoningTime: 4:15pm - 6:15pm | Room: Legacy BallroomModerator:

Wenchao Li - Boston Univ.

Organizers:Wenchao Li - Boston Univ.JyotirmoyDeshmukh - Univ. of Southern California

Recent advances in neural networks and deep learning have spurred a race towards increasing autonomy in both civilian and military spaces. However, recent incidents such as the Uber crash in March 2018 have raised alarms over the safety of these autonomous systems. This session introduces the topic of safety assurance of autonomous systems through the lens of formal reasoning.Thefourtalksarecontributedbyexpertsinthisfieldfrombothacademiaandindustry,anddiscussexistingtechniquesandopenchallengesofsafetyassuranceindiverseapplicationssuch as automated insulin delivery and autonomous driving.

7A.1 VerifyingConformanceofNeuralNetworkModelsMonalNarasimhamurthy,TaisaKushner,SouradeepDutta,SriramSankaranarayanan - Univ. of Colorado

7A.2 nn-Dependability-Kit:EngineeringNeuralNetworksforSafety-CriticalAutonomous DrivingSystems

Chih-HongCheng, Chung-Hao Huang, Georg Nührenberg - fortiss GmbH

7A.3 LearningDeepNeuralNetworkControllersforDynamicalSystemswithSafety Guarantees

JyotirmoyDeshmukh - Univ. of Southern CaliforniaJames Kapinski - Amazon.com, Inc.TomoyaYamaguchi,DanilProkhorov - Toyota Research Institute of North America

7A.4 TowardsVerification-AwareKnowledgeDistillationforNeural-NetworkControlled Systems

Jiameng Fan - Boston Univ.Chao Huang - Northwestern Univ.Wenchao Li - Boston Univ.Xin Chen - Univ. of DaytonQiZhu - Northwestern Univ.

TUESDAY, NOVEMBER 5

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Session 7B - Accelerator Design and ModelingTime: 4:15pm - 6:15pm | Room: Westminster IModerator:

Joerg Henkel - Karlsruhe Institute of Technology

Thissessionincludespapersthatproposenovelmethodologies,whichenableexplorationoftheacceleratordesignspace.Thefirsttwopapersfocusonmodelingenergyconsumptioninaccelerators,whilethethirdpaperfocusesonjointlyoptimizingaccuracyoftheDNNsandenergyconsumed by the underlying hardware.

7B.1 AUniformModelingMethodologyforBenchmarkingDNNAcceleratorsIndranil Palit - ValeoQiuwenLou, Robert Perricone, Michael Niemier, X. Sharon Hu - Univ. of Notre Dame

7B.2 PABO:PseudoAgent-BasedMulti-ObjectiveBayesianHyperparameterOptimization forEfficientNeuralAcceleratorDesign

MaryamParsa, Aayush Ankit - Purdue Univ.Amirkoushyar Ziabari - Oak Ridge National LaboratoryKaushik Roy - Purdue Univ.

7B.3 Accelergy:AnArchitecture-LevelEnergyEstimationMethodologyforAccelerator Designs

YannanN.Wu, Joel S. Emer - Massachusetts Institute of Technology & NVIDIA Corp.Vivienne Sze - Massachusetts Institute of Technology

Session 7C - Combating Circuit Aging and Device Variability Time: 4:15pm - 6:15pm | Room: Westminster IIModerator:

Vojtech Mrazek - Brno Univ. of Technology

Timing,reliability,andvariabilityhavebeencriticalissuesincircuitdesignswhenprocesstechnology enters into sub-10nm era.

Thefirstpaperinthissessionproposesanasymmetricagingconcepttoenhancereliabilityformulti-coresystems.Thesecondpaperproposesananalyticaltimingmodel,thatisapplicableforstatisticaltimingcalculationofnearthresholdcircuits.Thethirdpaperpresentsameta-modelbasedimportancesamplingmethodforefficientyieldestimationofSRAMcells.

7C.1 ROAD:ImprovingReliabilityofMulti-CoreSystemsviaAsymmetricAgingYu-GuangChen - National Central Univ.Ing-Chao Lin, Jian-Ting Ke - National Cheng Kung Univ.

7C.2 AStatisticalTimingModelforLowVoltageDesignConsideringProcessVariationPengCao,ZhiyuanLiu,JiangpingWu,JingjingGuo,JunYang,LongxingShi - Southeast Univ.

7C.3 EfficientYieldAnalysisforSRAMandAnalogCircuitsusingMeta-ModelBased ImportanceSamplingMethod

XiaoShi - Univ. of California, Los AngelesHaoYan,JiajiaZhang,QiancunHuang,LongxingShi - Southeast Univ.Lei He - Univ. of California, Los Angeles

TUESDAY, NOVEMBER 5

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Special Session 7D - Breaking the Ice Between Silicon Photonics Design and EDA: Electronic-Photonic Design AutomationTime: 4:15pm - 6:15pm | Room: Westminster IIIModerator:

Joerg Henkel - Karlsruhe Institute of Technology

Organizers:Mahdi Nikdast - Colorado State Univ.Ulf Schlichtmann - Tech. Univ. of Munich

SiliconPhotonics(SiPh)israpidlyemergingasastandardplatformforlarge-scalephotonicintegratedcircuits. Today’s SiPh circuits, which are mostly Datacom-driven, are generally small in size and low in complexity(i.e.,circuitswithasmallnumberofopticaldevicesand/orsimplerepetitivescaling,e.g.,atransceiver).However,emergingapplicationsofSiPh(e.g.,HPC,biosensing,quantumcomputing,LIDAR)arepushingtheboundariesofsuchsimpledesigns,creatingabottleneckforthecurrentcomponent-orientedSiPhdesign.Thisnecessitatesamorecircuit-orienteddesignflow,whichmakesabstractionfromthe very detailed geometry and enables design on a larger scale. As a result, the SiPh design process is evolvingalongthelinesofelectronicdesignautomation(EDA),hencethetermelectronic-photonicdesignautomation(EPDA).Thisspecialsessiondiscussesthestate-of-the-artofthisemergingSiPhcircuitdesignflowanditssynergieswithEDA.ItdiscussesthemostrecentadvancesinEPDA,thedesignchallengesandrequirementsthatcanbeaddressedthroughdesignautomationsolutionstoscaleSiPhcircuits,aswellasthoseinsystemsintegratingopticalinterconnects.Particularly,thesessionaimsatbridgingthegap between the Silicon Photonics Community and the EDA and CAD community, discussing the latest advancesandchallengesthatcanbeaddressedbyeachcommunity.Itiscomprisedoffiveinvitedtalksfrom pioneer groups in both academia and industry. This special session is of high interest to researchers whowanttolearnaboutthepromiseofsiliconphotonicsandunderstandpotentialresearchtopicsandchallengesrelatedtothedesignofsuchcircuitsthatcanbeaddressedthroughdesignautomationandCADsolutions.Moreover,thosealreadyworkingonsiliconphotonicsandwanttounderstandthepromiseofdesignautomationinSiPhdesignwillhighlybenefitfromthisspecialsession.

7D.1 Wavelength-RoutedOpticalNoCs:DesignandEDA–StateoftheArtandFuture Directions

Tsun-Ming Tseng, Alexandre Truppel, Mengchu Li - Tech. Univ. of MunichMahdi Nikdast - Colorado State Univ.UlfSchlichtmann - Tech. Univ. of Munich

7D.2 DesignTechnologyforScalableandRobustPhotonicIntegratedCircuitsZhengZhao,ZhoufengYing,ChenghaoFeng,JiaqiGu,RayT.Chen, David Z. Pan - Univ. of Texas at Austin

7D.3 SystematicExplorationofHigh-RadixIntegratedSiliconPhotonicSwitchesfor Datacenters

ZhifeiWang, Jiang Xu, Xuanqi Chen, Zhehui Wang, Jun Feng, Jiaxu Zhang, Shixi Chen - Hong Kong Univ. of Science and Technology

7D.4 LatestAdvancementstotheIndustry-LeadingEPDADesignFlowforSiliconPhotonicsJames Pond, Xu Wang, Zeqin Lu - Lumerical Inc.Gilles Lamant, Ahmadreza Farsaei - Cadence Design Systems, Inc.

7D.5 FromInverseDesigntoImplementationofPracticalPhotonicsJinhie Skarda, Logan Su, KiYoulYang, Dries Vercruysse, Rahul Trivedi, Jelena Vuckovic - Stanford Univ.

TUESDAY, NOVEMBER 5

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Additional Meeting - ACM/SIGDA Member MeetingTime: 6:45pm - 8:30pm | Room: Legacy BallroomTheannualACM/SIGDAMemberMeetingwillbeheldonTuesdayeveningfrom6:45-8:00pm.ThemeetingisopenforACMSIGDAmemberstoattend.MembersoftheElectronicDesignAutomationcommunitywhowouldliketolearnmoreaboutSIGDAorgetinvolvedwithSIGDAactivitiesarealsoinvited.Dinnerandbeverageswillbeserved.

ThemeetingwillbeginwithabriefoverviewofSIGDA,includingitsorganization,activities,volunteeringopportunities,andmemberbenefits.Next,theOutstandingYoungFacultyAwardwinner will present a brief talk on his work. Finally, we will end the evening with the announcement ofthewinnersofACMDesignAutomationStudentResearchCompetitiontakingplaceatthisyear’sICCAD.Wehopetoseeyouthere!

Sponsored by:


design automation

Sponsored by:

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WEDNESDAY SCHEDULE

8:30 - 9:30amKeynote: Probabilistic and Machine Learning Approaches for Autonomous Robots and Automated Driving Wolfram Burgard - Toyota Research Institute | Location: Westminster IV


9:45 - 11:45pmSession 8A: In-Memory and Analog-Domain Neural Computing Location: Westminster IV

Session 8B: Hot Data Architectures Location: Westminster I

Session 8C: Adaptive Cyber-Physical Systems Location: Westminster II

Special Session 8D: Results, Perspectives and Trends on Open-Source EDA Location: Westminster III

11:45am - 12:45pmLunch Location: Legacy Ballroom

1:00 - 3:00pmSession 9A: (Un)Locking the Pandora’s Box: Logic Locking Techniques Location: Westminster IV

Special Session 9B: Open-Source Microfluidic Design Ecosystem: Recent Developments and Upcoming Challenges Location: Westminster I

Session 9C: Analog Layout and Performance Optimization Location: Westminster II

Special Sessionl 9D: Tensor Methods for Accelerated Machine Learning and Electronic Design Automation Location: Westminster III

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WEDNESDAY SCHEDULE


3:30 - 5:00pmSession 10A: Mitigating Side-Channel Analysis: From EDA to Cloud Location: Westminster IV

Session 10B: Thermal and Power Management for Circuits and Systems Location: Westminster I

Session 10C: Global and Detailed Routing Location: Westminster II

Special Session 10D: The Impact of Emerging Technologies on Architectures and System-Level Management Location: Westminster III


5:30 - 7:00pmCareer & Diversity @ ICCAD Location: Westminster IV

Sponsored by:


design automation

Sponsored by:

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KEYNOTE ADDRESS

Keynote: Probabilistic and Machine Learning Approaches for Autonomous Robots and Automated DrivingTime: 8:30am - 9:30am | Room: Westminster IVSpeaker:WolframBurgard - Toyota Research Institute

Thecapabilitytorobustlyperceivetheirenvironmentsandtoexecutetheiractionsistheultimategoal in the areas autonomous robots and automated driving. The key challenge is that there are no sensors and no actuators that are perfect, which means that robots and cars need the ability to properlydealwiththeresultinguncertainty.InthispresentationIwillprovideanintroductiontotheprobabilisticapproachtorobotics,whichprovidesarigorousstatisticalmethodologytodealwiththeperceptionandplanning.Iwillfurthermorediscusshowthisapproachcanbeextendedusingstate-of-the-art technology from machine learning to bring us closer to the development of truly robust systems able to serve us in our every-day life.

Biography:WolframBurgardisVPforAutomatedDrivingTechnologyattheToyotaResearchInstituteinLosAltos,USA.HeisonleavefromaProfessorshipforAutonomousIntelligentSystemsattheUniv.ofFreiburg,Germany.HisinterestslieinAIandRobotics.Hehasmadesubstantialcontributionstoseveralrelevantproblemsincludingstateestimation,navigation,localization,SLAMandmobilemanipulation.Forhiswork,WolframBurgardreceivedtheGottfriedWilhelmLeibnizPrizefromtheDeutscheForschungsgemeinschaft,themostprestigiousGermanresearchaward,and an Advanced Grant from the European Research Council. He is fellow of the AAAI, the EurAI aswellastheIEEE.HecurrentlyalsoservesasPresidentoftheIEEERoboticsandAutomationSociety.


WEDNESDAY, NOVEMBER 6

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Session 8A - In-Memory and Analog-Domain Neural ComputingTime: 9:45am - 11:45am | Room: Westminster IVModerator:

Chia-LinYang - National Taiwan Univ.

Thissessionpresentsnoveltechniquesthatlookbeyondconventionaldigitalimplementationtoenableefficientdeeplearningandneuromorphiccomputing.Onedirectionistoexploreanalogandmixed-signaldomainrepresentations;anotheristoperformthein-situcomputationinsidethememory to reduce expensive data movement.

8A.1 NeuralNetwork-InspiredAnalog-to-DigitalConversiontoAchieveSuper-Resolution withLow-PrecisionRRAMDevices

WeidongCao,LiuKe,AyanChakrabarti,XuanZhang - Washington Univ.

8A.2 AnEvent-DrivenNeuromorphicSystemwithBiologicalPlausibleTemporalDynamicsHaowenFang,AmarShrestha,ZiyiZhao,YilanLi,QinruQiu - Syracuse Univ.

8A.3 APVT-RobustCustomized4TEmbeddedDRAMCellArrayforAcceleratingBinary NeuralNetworks

HyeinShin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim - Korea Advanced Institute of Science and Technology

8A.4 AnEnergy-EfficientProcessing-in-MemoryArchitectureforLongShortTermMemoryin aSpinOrbitTorqueMRAM

KyeonghanKim, Hyein Shin, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim - Korea Advanced Institute of Science and Technology


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Session 8B - Hot Data ArchitecturesTime: 9:45am - 11:45am | Room: Westminster IModerator:

Tulika Mitra - National Univ. of Singapore

This session brings together research that looks into the challenges of coping with hot data, minimizingdatamovementwithinnovativestorageandcomputationarchitectures,andacceleratingstorage management for data that is no longer hot.

8B.1 Re-Tangle:ReRAM-BasedProcessing-in-MemoryArchitectureforTransaction-Based Blockchain

Qian Wang, Tianyu Wang, ZhaoyanShen, Zhiping Jia, Mengying Zhao - Shandong Univ.Zili Shao - Chinese Univ. of Hong Kong

8B.2 HAML-SSD:AHardwareAcceleratedHotness-AwareMachineLearningBasedSSD Management

BingzheLi - Univ. of Minnesota, Twin CitiesChunhua Deng - Rutgers Univ.JinfengYang,DavidLilja - Univ. of Minnesota, Twin CitiesBoYuan - Rutgers Univ.David Du - Univ. of Minnesota, Twin Cities

8B.3 AcceleratingGarbageCollectionfor3DMLCFlashMemorywithSLCBlocksShuai Li, Wei Tong, Jingning Liu, BingWu,YazhiFeng - Huazhong Univ. of Science & Technology

Session 8C - Adaptive Cyber-Physical SystemsTime: 9:45am - 11:45am | Room: Westminster IIModerator:

Zili Shao - Chinese Univ. of Hong Kong

Thissessionpresentsworkoninnovativetechniquesforruntimeadaptationacrossdiversecyber-physicalsystems,spanningwearablesensingplatforms,automotivesystems,andFPGAplatforms.

8C.1 Multi-StageOptimizationforEnergy-EfficientActiveCellBalancinginBatteryPacksDebayanRoy, Swaminathan Narayanaswamy, Alma Pröbstl, Samarjit Chakraborty - Tech. Univ. of Munich

8C.2 Adar:AdversarialActivityRecognitioninWearablesRameshK.Sah, Hassan Ghasemzadeh - Washington State Univ.

8C.3 4D-CGRA:IntroducingBranchDimensiontoSpatio-TemporalApplicationMappingon CGRAs

ManupaKarunaratne, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh - National Univ. of Singapore

8C.4 WCETGuaranteesforOpportunisticRuntimeReconfigurationMarvin Damschen, LarsBauer, Jörg Henkel - Karlsruhe Institute of Technology


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Special Session 8D - Results, Perspectives and Trends on Open-Source EDATime: 9:45am - 11:45am | Room: Westminster IIIModerator:

Alexandre Levisse - École Polytechnique Fédérale de Lausanne

Organizer:Pierre-Emmanuel Gaillardon - Univ. of Utah

WhileacademicresearchhasbeenlongfuelinginnovationsinElectronicDesignAutomation,therecentlyintroducedDARPAElectronicsResurgenceInitiativewitha$1.5Bfundingdidputopen-source EDA in the spotlight. The aim of this special session is to present an overview of the current situationinthefourmainfieldsofEDA,namelylogicsynthesis,digitalphysicaldesign,digitalverificationandanalogphysicaldesign.

8D.1 LookingIntotheMirrorofOpenSourceAndrewB.Kahng - Univ. of California, San Diego

8D.2 LSOracle:aLogicSynthesisFrameworkDrivenbyArtificialIntelligenceWalterLauNeto,MaxAustin,ScottTemple - Univ. of UtahLuca Amaru - Synopsys, Inc.Xifan Tang, Pierre-EmmanuelGaillardon - Univ. of Utah

8D.3 UnlockingthePowerofFormalHardwareVerificationwithCoSAandSymbolicQEDFlorianLonsing, Karthik Ganesan, Makai Mann, Srinivasa Shashank Nuthakki, Eshan Singh, MarioSrouji,YahanYang,SubhasishMitra,ClarkBarrett - Stanford Univ.

8D.4 MAGICAL:TowardFullyAutomatedAnalogICLayoutLeveragingHumanandMachine Intelligence

BiyingXu,KerenZhu,MingjieLiu,YiboLin,ShaolanLi,XiyuanTang,NanSun, DavidPan - Univ. of Texas at Austin

LunchTime: 11:45am - 12:45pm | Room: Legacy BallroomJoinfellowattendeesforlunchinLegacyBallroom.


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Session 9A - (Un)Locking the Pandora’s Box: Logic Locking TechniquesTime: 1:00pm - 3:00pm | Room: Westminster IVModerator:

MuhammadYasin - Texas A&M Univ.

Logiclockingtechniquesactivelydefendagainstattacksinthesemiconductorsupplychain,includingoverproduction,piracy,andreverseengineering.Inthissession,wehavethreepapersdiscussingthetwosidesoflogiclocking:attacksanddefenses.Thefirstpapertargetslockedsequentialdesignsevenwhentheirscanchainisinaccessible.Thesecondpaperbreaksmanylocking techniques that introduce loops into circuits. Finally, the third paper sheds light on what secure locking techniques will look like in the future.

9A.1 IsRobustDesign-for-SecurityRobustEnough?AttackonLockedCircuitswithRestricted ScanChainAccess

NimishaLimaye, Abhrajit Sengupta - New York Univ.Mohammed Nabeel, Ozgur Sinanoglu - New York Univ., Abu Dhabi

9A.2 IcySAT:ImprovedSAT-BasedAttacksonCyclicLockedCircuitsKavehShamsi - Univ. of FloridaDavid Z. Pan - Univ. of Texas at AustinYierJin - Univ. of Florida

*9A.3 SecurityandComplexityAnalysisofLUT-basedObfuscation:FromBlueprinttoRealityGauravKolhe - Univ. of California, DavisHadi Mardani Kamali - George Mason Univ.Miklesh Naicker, Tyler David Sheaves, Hamid Mahmoodi - San Francisco State Univ.Sai Manoj Pudukotai Dinakarrao - George Mason Univ.Houman Homayoun - Univ. of California, DavisSetarehRafatirad,AvestaSasan - George Mason Univ.


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Special Session 9B - Open-Source Microfluidic Design Ecosystem: Recent Developments and Upcoming ChallengesTime: 1:00pm - 3:00pm | Room: Westminster IModerator:

Tsung-YiHo - National Tsing Hua Univ.

Organizer:Tsung-YiHo - National Tsing Hua Univ.

Despitetheimpressiveresearchprogressoverthelast15-20yearsandrecentcommercialization,themicrofluidiccommunityisstillrathersmall.Thatismainlybecausethedevelopmentofmicrofluidicsproductstodayisoflowefficiencyandhighcost.First,lackingofstandardizedruleanddesignautomationtoolsformicrofluidics,onehastodrawthelayoutofadevicemanuallywhichmaytakeweeks;second,duetosmallnumberofmicrofluidicchipsalabnormallyrequires,makingsmallamountmicrofluidicchipsismuchmoreexpensivethanmassproduction;third,peopleareusingnon-standardizedcomponentsandapplication-uniquelayout.Thereisalmostnoabilitytoconnectdisparatepartstosynergiesbreakthroughsortocreateeconomicdevelopmentviaspecialization.Tokeepmicrofluidiccommunitygrowing,welookedintothepossibilityofbuildinganopen-sourceecosystem where a wide range of users (e.g., researchers, entrepreneurs, students, hobbyists) can focusontheirownideasandapplicationswithoutworryingabouttheengineeringandmanufacturingsideofmicrofluidictechnology.Thesessionwillconsistoffivetalksoncomprehensiveaspectsofbothopen-sourcesoftwareandhardwarefordigitalandcontinuous-flowmicrofluidicresearch,includingopen-sourceincubationecosystem,cloud-basedplatform,API,benchmark,anditsapplicationonInternetofMicrofluidicThings.Webelievethatthespecialsessionwillgenerateinterestinthistopic,leadingto more research, future challenges, and several open problems in this area. This is a novel and multidisciplinarytopicofrelevancetotheEDAcommunity.

9B.1 Open-SourceIncubationEcosystemforDigitalMicrofluidics—StatusandRoadmapXing Huang, Chi-Chun Liang - National Tsing Hua Univ.Jia Li - Univ. of California, Los AngelesTsung-YiHo - National Tsing Hua Univ.Chang-JinKim - Univ. of California, Los Angeles

9B.2 ScalingMicrofluidicstoComplex,DynamicProtocolsMaxWillsey, Ashley Stephenson, Chris Takahashi - Univ. of WashingtonBichlien Nguyen, Karin Strauss - MicrosoftLuis Ceze - Univ. of Washington

9B.3 Specification,Integration,andBenchmarkingofContinousFlowMicrofluidicDevicesRadhakrishna Sanka - Boston Univ.BrianCrites,JeffreyMcDaniel,PhilipBrisk - Univ. of California, RiversideDouglas Densmore - Boston Univ.

9B.4 CloudColumba:AccessibleDesignAutomationPlatformforProductionandInspirationTsun-MingTseng,MengchuLi,YushenZhang - Tech. Univ. of MunichTsung-YiHo - National Tsing Hua Univ.Ulf Schlichtmann - Tech. Univ. of Munich

9B.5 TheInternetofMicrofluidicThings:PerspectivesonSystemArchitectureandDesign Automation

MohamedIbrahim - IntelMaria Gorlatova, Krishnendu Chakrabarty - Duke Univ.


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Session 9C - Analog Layout and Performance OptimizationTime: 1:00pm - 3:00pm | Room: Westminster IIModerator:

EvangelineF.Y.Young - Chinese Univ. of Hong Kong

Thissessionpresentsasetofnoveltechniquesforanalogcircuitdesign.Thefirsthalfofthesessionaddressesrouting,whilethesecondhalfisrelatedtoperformanceoptimization.Thefirstpaperinthesessionusesgenerativeneuralnetworktechniquestosolvetheanalogroutingproblem,mimickinghumandesignthroughnetworktraining.Inthenextpaper,anovelroutingmodelbasedonCartesiandetectionlinesisusedtomigratelayoutsfromonetechnologynodetoanother.ThelasttwopapersaredirectedtowardoptimizingtheperformanceofanalogcircuitsusingBayesianoptimizationtomodeltheParetofrontofoptimaldesigns,andbyusingtransposedneuralnetworkstomodelandoptimizeinductorsinvoltageregulatorcircuits.

9C.1 GeniusRoute:ANewAnalogRoutingParadigmUsingGenerativeNeuralNetwork Guidance

KerenZhu,MingjieLiu,YiboLin,BiyingXu,ShaolanLi,XiyuanTang,NanSun,DavidZ.Pan - Univ. of Texas at Austin

9C.2 AchievingRoutingIntegrityinAnalogLayoutMigrationviaCartesianDetectionLinesHao-YuChi - National Chiao Tung Univ.Zi-Jun Lin, Chia-Hao Hung - National Central Univ.Chien-Nan Liu, Hung-Ming Chen - National Chiao Tung Univ.

9C.3 EfficientPerformanceTrade-offModelingforAnalogCircuitbasedonBayesianNeural Network

ZhengqiGao,JunTao,FanYang,YangfengSu - Fudan Univ.Dian Zhou - Univ. of Texas at DallasXuan Zeng - Fudan Univ.

9C.4 ASpectralConvolutionalNetforCo-OptimizationofIntegratedVoltageRegulatorsand EmbeddedInductors

HakkiTorun,HuanYu,NiharDasari,VenkataChaitanyaKrishnaChekuri,ArvindSingh,Jinwoo Kim, Sung Kyu Lim, Saibal Mukhopadhyay, Madhavan Swaminathan - Georgia Institute of Technology


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Special Session 9D - Tensor Methods for Accelerated Machine Learning and Electronic Design AutomationTime: 1:00pm - 3:00pm | Room: Westminster IIIModerator:

Wei Zhang - Hong Kong Univ. of Science and Technology

Organizers:Zhiru Zhang - Cornell Univ.Zheng Zhang - Univ. of California, Santa Barbara

Asahigh-ordergeneralizationofmatricesandvectors,tensorcomputationhasemergedasapowerfultooltosolvehigh-dimensionalproblemsinscientificcomputing,machinelearning,dataminingandoptimalcontrol.Despiteitssuperiorefficiencyinovercomingthecurseofdimensionality,theresearchoftensorcomputationinhardwareacceleratorsandinEDAisstillinthe early stage.

Recentlywenotethatanactivebodyofresearchhasemergedinbothacademiaandindustry,ranging from hardware design to EDA algorithms, making encouraging progress in both theory andengineeringapplications.Thisspecialsessionwillpresentanumberoftheseresearchefforts,with topics ranging from new tensor-based EDA algorithms (wafer data analysis, circuit modeling andsimulation,parasiticextraction,uncertaintyquantification)totensorhardwareaccelerators(tensorized DNN on edge devices, architecture for tensor-based DNN). We envision that the discussionsinthissessionwillleadtonovelcross-layersolutionstheenablehighlyefficienttensor-based machine learning systems and EDA frameworks.

9D.1 DEEPEYE:ADeeplyTensorCompressedNeuralNetworkHardwareacceleratorYuanCheng - Shanghai Jiaotong Univ.Guangya Li - Southern Univ. of Science and TechnologyNgai Wong - Univ. of Hong KongHai-Bao Chen - Shanghai Jiao Tong Univ.HaoYu - Southern Univ. of Science and Technology

9D.2 High-PerformanceHardwareArchitectureforTensorSingularValueDecompositionChuanhua Deng - Rutgers Univ.Xiaoyang Liu - Columbia Univ.MiaoYin - Rutgers Univ.Xiaodong Wang - Columbia Univ.BoYuan - Rutgers Univ.

9D.3 TensorMethodsforGeneratingCompactUncertaintyQuantificationandDeepLearning Models

ChunfengCui, Cole Hawkins, Zheng Zhang - Univ. of California, Santa Barbara

9D.4 TensorMethodsforModelingNonlinearCircuitsandSystemsNgaiWong - Univ. of Hong Kong

9D.5 FacilitatingDeploymentOfAWafer-BasedAnalyticSoftwareUsingTensorMethodsLi-C.Wang, Chuanhe (Jay) Shan, Ahmed Wahba - Univ. of California, Santa Barbara

9D.6 TensorTrainAcceleratedElectromagneticModelingofInterconnectsShucheng Zheng - Univ. of ManitobaZhuotong Chen - Univ. of California, Santa BarbaraVladimirOkhmatovski - Univ. of Manitoba


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Session 10A - Mitigating Side-Channel Analysis: From EDA to CloudTime: 3:30pm - 5:00pm | Room: Westminster IVModerator:

Wenjie Che - New Mexico State Univ.

Thissessionisonmitigatingpower-basedside-channelanalysiswiththreepaperstargetingdifferentabstractionlayers.ThefirstpaperfocusesonEDAtechniquestoautomaticallyidentifyand modify vulnerable gates in a netlist. The second paper proposes circuit-level techniques for randomizing the clock source to hide side-channel exposure. The last paper analyzes remote side-channelattacksonmulti-tenantFPGAcloudsanddemonstratesstrategiesforimproving side-channel resiliency.

10A.1 Karna:AGate-SizingBasedSecurityAwareEDAFlowforImprovedPowerSide-Channel AttackProtection

Patanjali Slpsk, PrasannaKarthikVairam, Chester Rebeiro - Indian Institute of Technology MadrasKamakotiV - Professor

10A.2 SCRIP:SecureRandomClockExecutiononSoftProcessorSystemstoMitigate Power-BasedSideChannelAttacks

DarshanaJayasinghe, Aleksandar Ignjatovic, Sri Parameswaran - Univ. of New South Wales

10A.3 ActiveFencesagainstVoltage-BasedSideChannelsinMulti-TenantFPGAsJonasKrautter,DennisGnad - Karlsruhe Institute of TechnologyFalk Schellenberg, Amir Moradi - Ruhr Univ. BochumMehdi Tahoori - Karlsruhe Institute of Technology



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Session 10B - Thermal and Power Management for Circuits and SystemsTime: 3:30pm - 5:00pm | Room: Westminster IModerator:

YuWang- Tsinghua Univ.

Thissessioncoverstopicsinthermalandpower-awaredesignmethods.Thefirstpaperpresentsaclockgatingtechniquetoaddresscycliclogicpaths.Thesecondpaperpresentsadynamicpowermanagementschemeutilizingpredictivemodelstoleveragetimingslackinvaryingworkloadcharacteristicsinamulti-FPGAsystem.Finally,thesessionisconcludedwithatemperaturemodelingapproachthatcanreachnanoscalespatialresolutionwithhighaccuracy.

10B.1 ClockGatingSynthesisofNetlistwithCyclicLogicPathsYonghwiKwon - Korea Advanced Institute of Science and TechnologyInhak Han - BAUMYoungsooShin - Korea Advanced Institute of Science and Technology

10B.2 Workload-AwareOpportunisticEnergyEfficiencyinMulti-FPGAPlatformsSahandSalamat, Behnam Khaleghi, Mohsen Imani, Tajana Rosing - Univ. of California, San Diego

*10B.3NanoTherm:AnAnalyticalFourier-BoltzmannFrameworkforFullChipThermal Simulations

Shashank Varshney, Hameedah Sultan - Indian Institute of Technology DelhiPalkesh Jain - Qualcomm Technologies, Inc.SmrutiR.Sarangi - Indian Institute of Technology Delhi


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Session 10C - Global and Detailed RoutingTime: 3:30pm - 5:00pm | Room: Westminster IIModerator:

William Swartz - Timberwolf Systems, Inc.

Findinggoodroutingsolutionsisoneofthemostcriticalchallengesfortheadvancednodes.Ifcongestionandroutingviolationscannotberesolved,designsgonowhere.Thissessionfirstpresentsanewwaytomodelglobalroutinggraphwhichhaven’tbeenchangedfordecades.Then,ahybridmulti-threadingschemeisintroducedtofurtherspeedupglobalroutingalgorithms.Lastbutnotleast,adetailedroutingpaperwillbepresentedtominimizedesign-rule-checkingviolationsandconvergeroutingchallenges.

10C.1 GlobalRoutingonRhomboidalTilesNicolai Hähnle - Advanced Micro Devices, Inc.PietroSaccardi - Univ. of Bonn

10C.2 SPRoute:AScalableParallelNegotiation-basedGlobalRouterJiayuanHe - Univ. of Texas at AustinMartinBurtscher - Texas A&M Univ.Rajit Manohar - Yale Univ.Keshav Pingali - Univ. of Texas at Austin

10C.3 Dr.CU2.0:AScalableDetailedRoutingFrameworkwithCorrect-by-Construction DesignRuleSatisfaction

HaochengLi,GengjieChen,BentianJiang,JingsongChen,EvangelineYoung - Chinese Univ. of Hong Kong


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Special Session 10D - The Impact of Emerging Technologies on Architectures and System-Level ManagementTime: 3:30pm - 5:00pm | Room: Westminster IIIModerator:

Sri Parameswaran - Univ. of New South Wales

Organizers:Jörg Henkel - Karlsruhe Institute of Technology (KIT)Hussam Amrouch - Karlsruhe Institute of Technology (KIT)

Thegoalofthissessionistointroduceanddiscussdifferentkindsofemergingtechnologiesforlogiccircuitryandmemorywithrespecttothekeyquestionofhowtheywillimpactfuturesystem-on-chip architectures and system-level management techniques. It is obvious that emerging technologies should have an impact there in order to fully exploit their technological advantages but also in order to deal with any disadvantages they might come with. In this special session, threepromisingemergingtechnologiesarepresented:(i)NegativeCapacitanceField-EffectTransistor (NCFET) as a new CMOS technology with advantages primarily for low-power design, (ii)FerroelectricFET(FeFET)asanon-volatile,area-efficientandlow-powercombinedlogicandmemoryaswellas(iii)aPhase-ChangeMemory(PCM)andResistiveRAM(ReRAM)offeringalargepotentialfortacklingthememorywallprobleminthevonNeumannarchitecture.Ouranalysisdemonstratesthatnotonlynewcomputingparadigmsarepromotedbythesenewtechnologies,itwillalsobeseenthatthetrade-offsbetweentheclassicaldesignparametersoflowpower,performanceetc.willshiftandhenceemergingtechnologieswilloffernewParetopointsinthedesign space of future on-chip architectures. In that context, this special session is unique as it bridges the gap between the technology side and system/architecture-level side to draw a vision of new technologies and their impact on architectures and system-level management.

10D.1 NCFET’sImpactonArchitectureandSystem-LevelManagementJörgHenkel,HussamAmrouch,MartinRapp,SamiSalamin - Karlsruhe Institute of Technology (KIT)Dayane Reis - Univ. of Notre DameDi Gao - Zhejiang Univ.Michael Niemier, Cheng Zhou, X. Sharon Hu - Univ. of Notre DameHsiang-YunCheng - Academia SinicaChia-LinYang - National Taiwan Univ.

10D.2 BlurringtheBoundaryofComputeandMemoryviaFeFETsDayane Reis - Notre Dame Univ.Di Gao - Zhejiang Univ.XunzhaoYin,MichaelNiemier - Univ. of Notre DameCheng Zhuo - Zhejiang Univ.X.SharonHu - Univ. of Notre Dame

10D.3 Device-ArchitectureCo-DesigntoEnableFutureResistiveMemorySystemsHsiang-YunCheng - Research Center for Information Technology Innovation, Academia SinicaChia-LinYang - National Taiwan Univ.


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Additional Meeting - Career & Diversity @ ICCADTime: 5:30pm - 7:00pm | Room: Westminster IVModerator:

Patrick Groeneveld - Stanford Univ.

Organizers:EvangelineYoung-The Chinese Univ. of Hong KongPatrick Groeneveld - Stanford Univ.

This session will focus primarily on two closely related issues, career development and diversity at work. Recruiters from industry will share their views and opinions on what companies are looking for from young graduates, and there will also be sharings from young graduates from industry on theirworks,experiences,andtipsinlocatingasuitablecareerforPhDstudentswhoaregoingtograduate soon. While career planning and development is important for individuals, diversity at workisanessentialingredientforahealthyorganizationandcompany.Studieshaveshownthatdiversecompanieshaveasignificantlyhigherchanceofsuccesswithmorefinancialreturnsabovetheirrespectiveindustrymedians.Thissessionwillalsoseektoincreaseunderstandingoftheimportance of diversity and inclusion at works. Light food and beverage will be provided.

Speakers:LalehBehjat - Univ. of Calgary MengLi- Facebook RangharajanVenkatesan - NVIDIA Corp.

Sponsored by:

Sponsored by:special interest group on

design automation

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THURSDAY SCHEDULE8:00am - 12:00pmHands On Workshop on Machine Learning, Deep Learning and Reinforcement Learning for EDA Developers Location: Westminster I

8:00am - 6:00pm3rd International Workshop on Quantum Compilation Location: Westminster II

8:00am - 5:50pmTop Picks in Hardware and Embedded Security Location: Cotton Creek II

8:15am - 5:00pmWorkshop on Hardware and Algorithms for Learning On-a-Chip Location: Westminster III

8:30am - 5:30pmSecond Workshop on Open-Source EDA Technology (WOSET) Location: Westminster IV

9:00am - 7:00pmInternational Workshop on Design Automation for Analog and Mixed-Signal Circuits Location: Cotton Creek I

11:30am - 1:30pmWorkshop Lunch Location: Legacy Ballroom

1:00 - 6:00pm1st Workshop on Accelerator Computer-Aided Design Location: Westminster I

SavetheDateforICCAD2020November2-5,2020|HiltonSanDiegoSpa&Resort

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THURSDAY, NOVEMBER 7

Workshop 1W - Workshop on Hardware and Algorithms for Learning On-a-ChipTime: 8:15am - 5:00pm | Room: Westminster IIIModerator:

YiranChen - Duke Univ.

Organizers:YiranChen - Duke Univ.Qinru Qiu - Syracuse Univ.YanzhiWang - Northeastern Univ.Jishen Zhao - Univ. of California, San Diego

In recent years, machine/deep learning algorithms has unprecedentedly improved the accuracies inpracticalrecognitionandclassificationtasks,someevensurpassinghuman-levelaccuracy.However, to achieve incremental accuracy improvement, state-of-the-art deep neural network (DNN)algorithmstendtopresentverydeepandlargemodels,whichposessignificantchallengesforhardwareimplementationsintermsofcomputation,memory,andcommunication.Thisisespeciallytrueforedgedevicesandportablehardwareapplications,suchassmartphones,machinetranslationdevices,andsmartwearabledevices,wheresevereconstraintsexistinperformance,power, and area.

Thereisatimelyneedtomapthelatestcomplexlearningalgorithmstocustomhardware,inordertoachieveordersofmagnitudeimprovementinperformance,energyefficiencyandcompactness.Exemplaryeffortsfromindustryandacademiaincludemanyapplication-specifichardwaredesigns(e.g.,xPU,FPGA,ASIC,etc.).Recentprogressincomputationalneurosciencesandnanoelectronictechnology, such as emerging memory devices, will further help shed light on future hardware-softwareplatformsforlearningon-a-chip.

Theoverarchinggoalofthisworkshopistoexplorethepotentialofon-chipmachinelearning,torevealemergingalgorithmsanddesignneeds,andtopromotenovelapplicationsforlearning.Itaimstoestablishaforumtodiscussthecurrentpractices,aswellasfutureresearchneedsintheaforementionedfields.

Speakers:Hsien-Hsin Lee - FacebookVikas Chandra - FacebookYu Wang - Tsinghua Univ.Jae-Joon Kim -Yingyan Lin - Rice Univ.Tinoosh Mohsenin - Univ. of MarylandJaewoong Sim - Intel Corp.Siddharth Garg - New York Univ.Zhen Zhang - Univ. of California, Santa BarbaraPierre-Emmanuel Gailiardon - Univ. of UtahCatherine Schuman - Oak Ridge National Laboratory

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Workshop 2W - Hands On Workshop on Machine Learning, Deep Learning and Reinforcement Learning for EDA DevelopersTime: 8:00am - 12:00pm | Room: Westminster IOrganizer:

Claudionor Coelho - Google Inc.

This workshop covers the basics of machine learning, deep learning and reinforcement learning withexamplesonhowtousethisinformationtobuildthenextgenerationofEDAtools.

MachinelearningisgaininggreateracceptanceinEDAindustry,replacingcomplicatedheuristicsandsolvingproblemsthatwereveryhardtocharacterizewithoutaprobabilisticmindset,withapplicationsindesign,verification,physicalimplementationanddebugging.

This workshop shows how to solve common EDA problems using Naïve Bayes, regression andclassification,goingtoconvolutionalandrecurrentneuralnetworks,andfinallypresentingreinforcementlearning,inacompletelyhandsonmanner,sothattheattendeeswillhavefirsthandexperienceinsolvingEDAproblemswithML/DL/RLformulations.Wewillalsofocusonhowtodebug these problems and understand what goes on when the results do not match what you expected.

During the workshop, we have selected a number of small EDA projects that are going to be executedbytheattendees.

1.RegressionandclassificationofparametersinNPcompleteheuristics

2.Estimatingdelaysoflibrariesusingmachinelearninganddeeplearningtechniques

3. Using reinforcement learning to solve EDA problems

4. Using recurrent networks to analyze temporal data in EDA

Attendeeswillreceiveanexecutablenotebookcontainingallthematerial,withexamplesbothinKeras and PyTorch.

Attheendoftheworkshop,attendeeswillbeabletouseML/DL/RLtosolvethemostchallengingproblemsinEDA,beingabletodiscuss,implementandarchitectsolutions.

Speakers:ManishPandey - Synopsys, Inc. ClaudionorCoelho - Google, Inc

Workshop LunchTime: 11:30am - 1:30pm | Room: Legacy BallroomJoinfellowattendeesforlunchinLegacyBallroom.

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Workshop 3W - 1st Workshop on Accelerator Computer-Aided Design Time: 1:00pm - 6:00pm | Room: Westminster IOrganizers:

Ibrahim Elfadel - Khalifa Univ.Subhasish Mitra - Stanford Univ.

1. Topics

This workshop provides a forum to present and discuss the current trends in computer-aided designinsupportofdomain-specificacceleratorchips,especiallyforartificialintelligenceandmachinelearningapplications.TheworkshopwillbeconcernedwiththeVLSImethodologyflowfromhigh-levelsynthesistophysicalverificationandperformanceprediction,particularlyinthewayitgetsimpactedwiththeemergingdesignparadigmsofdomain-specificinstructionsets,approximatecomputing,in-memorycomputing,andstochasticcomputing.OfparticularinteresttotheworkshoparethetransformationsthatVLSICADhastoundergotoadapttothepost-CMOStechnologies when they are considered in the context of accelerator design. The workshop will include,butwillnotbelimitedto,thefollowingtopics:

• High-level synthesis of machine-learning accelerators

• Designspaceexplorationofdomain-specificaccelerators

• Toolsandmethodologiesforin-memorycomputing

• Toolsandmethodologiesforapproximatecomputing

• CADforemergingacceleratortechnologies:ReRAM,MRAM,Photonics,etc.

• Tools and methodologies for the post-CNN era

• Toolsandmethodologiesforthetestingandverificationofacceleratorchips.

2. Audience

The workshop will be of interest to all designers and CAD engineers involved in accelerator projects or to academics and graduate students interested in the state of the art of CAD for accelerator chip design.

Speakers:YiranChen-Duke Univ.PriyankaRaina-Stanford Univ.SteliosDiamantidis-Synopsys, Inc.VictorKravets- IBM ResearchDannyBankman- Stanford Univ.

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Workshop 4W - 3rd International Workshop on Quantum CompilationTime: 8:00am - 6:00pm | Room: Westminster IIOrganizers:

Mathias Soeken - École Polytechnique Fédérale de LausanneThomas Haener - Microsoft

Theworkshopaimstobringtogetherresearchersfromquantumcomputing,electronicdesignautomation,andcompilerconstruction.Openquestionsthatweanticipatethisgrouptotackleincludenewmethodsforcircuitsynthesisandoptimization,optimizationsandrewriting,techniquesforverifyingthecorrectnessofquantumprograms,andnewtechniquesforcompilingefficientcircuits and protocols regarding fault-tolerant and architecture constraints.

The scope of the workshop includes, but not limited to, current hot topics in quantum circuit design suchas:-space-optimizingcompilersforreversiblecircuits-design-spaceexplorationforautomaticcodegenerationfromclassicalHDLspecification- quantum programming languages- reversible logic synthesis- technology-aware mapping-errorcorrection-optimizedlibraries(e.g.,forarithmeticandHamiltoniansimulation)- benchmarking of circuits for small and medium scale quantum computers- quantum and reversible circuit peep-holing and (re)synthesis-softwareandtoolsforallabovementionedtopics-quantumoutreach:codingcontests,tutorials,education

Speakers:AlexanderCowtan- Cambridge Quantum ComputingMarcGrauDavis- Univ. of California, BerkeleyVadymKliuchnikov-Microsoft CorporationRabanIten-ETH ZurichDamienNguyen-Huawei Technologies Co., Ltd.Eric Peterson - Rigetti ComputingYunongShi- Univ. of ChicagoSeyonSivarajah-Cambridge Quantum ComputingMitchellThornton-Southern Methodist Univ.

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Workshop 5W - International Workshop on Design Automation for Analog and Mixed-Signal CircuitsTime: 9:00am - 7:00pm | Room: Cotton Creek IOrganizers:

Xin Li - Duke Univ.Chandramouli Kashyap - IntelMasanori Hashimoto - Osaka Univ.Jaeha Kim - Seoul National Univ.ScottLittle - Maxim IntegratedChris Myers - Univ. of UtahDejan Nickovic - Austrian Institute of Technology

Growingdigitizationofintegratedcircuitshascontributedtomakingsystem-on-chipsevermorecomplex.Yet,asubstantialportionofachipconsistsofanalogandmixed-signal(AMS)circuitsthatprovidecriticalfunctionalitylikeclockgeneration,voltageregulation,interfacewiththeexternalworld,etc.AggressivescalingofICtechnologiesaswellasadvancingtheintegrationofheterogeneousphysicaldomainsonchipsubstantiallycomplicatesthedesignofAMScomponents.On the one hand, their modeling and design becomes extremely complex. On the other hand, their interplaywiththerestofthesystem-on-chipchallengesdesign,verificationandtest.ThesenewtechnologytrendsbringenormouschallengesandopportunitiesforAMSdesignautomation.ThisisreflectedbyanincreaseinresearchactivityonAMSCADworldwide.ThepurposeofthisworkshopistobringtogetheracademicandindustrialresearchersfrombothdesignandCADcommunitiestoreportrecentadvancesandmotivatenewresearchtopicsanddirectionsinthisarea.

Speakers:RonaldRohrer - Southern Methodist Univ.ChandramouliKashyap - Intel Corp.MarkPo-HungLin - National Chiao Tung Univ.ChunfengCui - Univ. of California, Santa BarbaraHanbinHu - Univ. of California, Santa BarbaraDuaneBoning - Massachusetts Institute of TechnologyJun-YangLei - Georgia Institute of TechnologyThaoDang - Univ of Grenoble-Alpes FranceMingjieLiu - Univ. of Texas at AustinJunTao - Fudan Univ.JiahuaLi - Southern Methodist Univ.

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Workshop 6W - Second Workshop on Open-Source EDA Technology (WOSET)Time: 8:30am - 5:30pm | Room: Westminster IVOrganizers:

Sherief Reda - Brown Univ.Andrew Kahng - Univ. of California, San DiegoSachin Sapatnekar - Univ. of MinnesotaMohamned Shalan - The American Univ. in Cairo

ThecostanddifficultyofICdesigninadvancednodeshavestifledhardwaredesigninnovationand raised unprecedented barriers to bringing new design ideas to the marketplace. Notably, commercial EDA tools have become both expensive and highly complex, as they are aimed at leading-edge,expertusers.Unlikethethrivingsoftwarecommunity,whichenjoysalargenumberofopen-sourceoperatingsystems,compilers,librariesandapplications,thehardwarecommunitylacks such an ecosystem. This workshop aims to organise the open-source EDA movement. The workshopwillbringtogetherEDAresearcherswhoarecommittedtoopen-sourceprinciplestosharetheirexperiencesandcoordinateeffortstowardsdevelopingareliable,fullyopen-sourceEDAflow.Theworkshopwillfeaturepresentationsandpostersthatoverviewexistingorunder-development open-source tools, designs and technology libraries. A live demo-session for tools in advanced state will be planned. The workshop will feature a panel on the present status and futurechallengesofopen-sourceEDA,andhowtocoordinateeffortsandensurequalityandinteroperability across open-source tools. A cash award will be given for a Best Tool Award.

Submissioncategories:

-Overviewofanexistingorunder-developmentopen-sourceEDAtool

-Overviewofsupportinfrastructure,suchasdatabases,fileformats,anddesignbenchmarks.

- Open-source cloud-based tools

-Positionstatements(e.g.criticalgaps,blockers/obstacles).

http://woset.org

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Workshop 7W - Top Picks in Hardware and Embedded SecurityTime: 8:00am - 5:30pm | Room: Cotton Creek IIOrganizers:

Ramesh Karri - New York Univ.Jeyavijayan Rajendran - Texas A&M Univ.Ahmad-Reza Sadeghi - Technische Univ. DarmstadtGang Qu - Univ. of Maryland, College Park

The top picks will be selected from conference papers that have appeared in leading hardware security conferences including but not limited to DAC, DATE, ICCAD, HOST, VLSI Design, CHES, ETS,VTS,ITC,IEEES&P,EuroS&P,UsenixSecurity,ASIACCS,NDSS,ISCA,HASP,MICRO,ASPLOS,HPCA,ACSACandACMCCS.ThetoppickswillappearinanIEEETransactionsonCADspecialsectionon“TopPicksinHardwareandEmbeddedSecurity.”Toreiterate,toppickswillspana gamut of topics in hardware, microarchitecture, and embedded security from leading conferences. Shortlist of papers are invited to the “Top Picks” workshop, collocated with ICCAD 2019. Authors arerequiredtopresentthepaperattheworkshop.Thisismandatoryforconsiderationtobeatoppick. Selected papers are then invited for submission to TCAD Top Picks. http://toppicksinhardwaresecurity.alari.ch/

Speakers:BoyouZhou-ADI Global DistributionCynthiaSturton-Univ. of North CarolinaHongyuFang-George Washington Univ.HodaNaghibijouybari-Univ. of California, RiversideRuiZhang-Univ. of North Carolina, Chapel HillFarinazKoushanfar-Univ. of California, San DiegoJVRajendran-Texas A&M Univ.BitaDarvishRouhani- Microsoft CorporationDennisR.E.Gnad-Karlsruhe Institute of TechnologyShreyasSen-Purdue Univ.WenjieXiong-Yale Univ.ReiUeno-Tohoku Univ.

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EXECUTIVE COMMITTEE

GENERAL CHAIRDavid Z. Pan Dept. of Electrical & Computer Engineering The Univ. of Texas at Austin Austin, TX 78712 512-471-1436 [email protected]

PROGRAM CHAIRYuan Xie Univ. of California, Santa Barbara 5159 HFH Hall, UCSB Santa Barbara, CA 93106 805-893-5563 [email protected]

VICE PROGRAM CHAIRRolf Drechsler Univ. of Bremen/DFKI Bibliothekstr. 5, 28359 Bremen, Germany +49 421 218 63932 [email protected]

EUROPEAN REPRESENTATIVEUlf Schlichtmann Technical Univ. of Munich Institute for EDA Arcisstr. 21, Muenchen, Germany 80333 +49 89 289 23665 [email protected]

ASIAN REPRESENTATIVETakashi Sato Kyoto Univ. Graduate School of Informatics, 36-1 Yoshida-Hommachi, Sakyo-ku, Kyoto 606-8501 Japan [email protected]

TUTORIAL & SPECIAL SESSION CHAIRTulika Mitra National Univ. of Singapore School of Computing 13 Computing Drive Singapore 117417 [email protected]

ACM/SIGDA REPRESENTATIVESri Parameswaran Univ. of New South Wales School of Computer Science & Engineering Sydney, Australia 61296626725 [email protected]

CEDA REPRESENTATIVETsung-Yi Ho National Tsing Hua Univ. Dept. of Computer Science No. 101, Sec. 2, Kuang-Fu Rd.Hsinchu, Taiwan 30013 +886-3-5731214 [email protected]

CONFERENCE PLANNER & REGISTRATION MANAGERNannette Jordan MP Associates, Inc. 1721 Boxelder St., Ste. 107 Louisville, CO 80027 303-530-4562 [email protected]

INDUSTRY LIAISONPatrick Groeneveld Stanford Univ.Stanford, CA 94305 [email protected]

PAST CHAIRIris Bahar School of Engineering Brown Univ. 182 Hope Street Providence, RI 02906 401-863-1430 (office) 401-603-6972 (mobile) [email protected]

WORKSHOP CHAIREvangeline Young The Chinese Univ. of Hong Kong Dept. of Computer Science and Engineering New Territories, Hong Kong 852-39438401 [email protected]

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TECHNICAL PROGRAM COMMITTEE

PROGRAM CHAIRYuan Xie Univ. of California, Santa Barbara

VICE PROGRAM CHAIRRolf Drechsler Univ. of Bremen/DFKI

Luca AmaruSynopsys Inc.

Hussam AmrouchKarlsruhe Institute of Technology

David AtienzaÉcole Polytechnique Fédérale de Lausanne (EPFL)

Aydin AysuNorth Carolina State Univ.

Kia BazarganUniv. of Minnesota

Laleh BehjatUniv. of Calgary

Davide BertozziUniv. of Ferrara

Swarup BhuniaUniv. of Florida

Paul BogdanUniv. of Southern California

Eli BozorgzadehUniv. of California, Irvine

Andrea CalimeraPolitecnico di Torino

Ro CammarotaIntel

Benjamin Carrion SchaeferThe Univ. of Texas at Dallas

Mario R. CasuPolitecnico di Torino, Department of Electronics and Telecommunications

Wanli ChangUniv. of York

Naehyuck ChangKAIST

Abhijit ChatterjeeGeorgia Tech

Xiaoming ChenInstitute of Computing Technology, Chinese Academy of Sciences

Deming ChenUIUC

Jianli ChenFuzhou Univ.

Tung-Chieh ChenSynopsys

Yiran ChenDuke Univ.

Chung Kuan ChengUCSD

Hsiang-Yun ChengAcademia Sinica

Fabien ClermidyCEA-LETI

Steve DaiCornell Univ.

Yixiao DingCadence Design Systems

Marco DonatoHarvard Univ.

Deliang FanUniv. of Central Florida

Pierre Emmanuel GaillardonUniv. of Utah

Siddharth GargUniv. of Waterloo

Tony GivargisUniv. of California, Irvine

Jie HanUniv. of Alberta

Song HanMIT

Christopher HarrisAuburn Univ.

Tsung-Yi HoNational Tsing Hua Univ.

Houman HomayounGeorge Mason Univ.

Jiun-Lang HuangNational Taiwan Univ.

Tsung-Wei HuangUniv. of Illinois at Urbana-Champaign

William HungCadence Design Systems

Yier JinUniv. of Florida

Ajay JoshiBoston Univ.

Kerim KalafalaIBM

Myung Chul KimIBM Corporation

Taewhan KimSeoul National Univ.

Michel KinsyBoston Univ.

Yukihide KohiraThe Univ. of Aizu

Farinaz KoushanfarUniv. of California San Diego

Jaydeep KulkarniUniv. of Texas at Austin

Yingjie LaoClemson Univ.

Hsien-Hsin Sean LeeFacebook Inc

Jin-Fu LiNational Central Univ.

Meng LiFacebook Inc

Ing-Chao LinNational Cheng Kung Univ.

Jai-Ming LinDepartment of Electrical Engineering, National Cheng Kung Univ.

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Yibo LinUniv. of Texas at Austin

Mark Po-Hung LinNational Chung Cheng Univ.

Xue LinNortheastern Univ.

Chunsheng LiuAlibaba inc

Wen-Hao LiuCadence Design Systems

Weichen LiuNanyang Technological Univ.

Yung-Hsiang LuPurdue Univ.

Ken MaiCarnegie Mellon Univ.

Prabhat MishraUniv. of Florida

Tulika MitraNational Univ. of Singapore

Kartik MohanramUniv. of Pittsburgh

Tinoosh MohseninUniv. of Maryland Baltimore County

Gabriela NicolescuEcole Polytechnique de Montréal

Seda Ogrenci-MemikNorthwestern Univ.

Hamed OkhraviMIT Lincoln Laboratory

Sule OzevASU

Jongsun ParkKorea Univ.

Sudeep PasrichaColorado State Univ.

Hiren PatelUniv. of Waterloo

Yu PuAlibaba DAMO Academy

Weikang QianShanghai Jiao Tong Univ.

Jeyavijayan RajendranTexas A&M Univ.

Bipin RajendranNew Jersey Institute of Technology

Sandip RayUniv. of Florida

Arijit RaychowdhuryGeorgia Institute of Technology

Sherief RedaBrown Univ.

Tajana RosingUCSD

Ahmad-Reza SadeghiTechnische Universitaet Darmstadt

John (Jack) SampsonPenn State

Sachin S. SapatnekarUniv. of Minnesota

Fareena [email protected]

Takashi SatoKyoto Univ.

Patrick SchaumontVirginia Tech

Shreyas SenECE, Purdue Univ.

Abhronil SenguptaThe Pennsylvania State Univ.

Jae-sun SeoArizona State Univ.

Muhammad ShafiqueVienna Univ. of Technology (TU Wien)

Zili ShaoThe Chinese Univ. of Hong Kong

Yiyu ShiUniv. of Notre dame

Weiping ShiTexas A&M Univ.

Youngsoo ShinKAIST

Mathias SoekenEPFL

Volker J. SorgerGeorge Washington Univ.

Mircea StanUniv. of Virginia

Dmitri StrukovUC Santa Barbara

Guangyu SunPeking Univ.

YasuhiroTakashimaUniv. of Kitakyushu

Sheldon TanUniv. of California at Riverside

Sebastien ThuriesCEA-LETI

Aida Todri-SanialCNRS-LIRMM/Univ. of Montpellier

Rasit Onur TopalogluIBM

Li-C. WangUCSB

Ting-Chi WangNational Tsing Hua Univ.

Yanzhi WangUniv. of Southern California

Lan WeiUniv. of Waterloo

Sheng WeiRutgers Univ.

Wujie WenFlorida International Univ.

Robert WilleJohannes Kepler Univ. Linz

Martin WongThe Chinese Univ. of Hong Kong

Ngai WongThe Univ. of Hong Kong

Hua XiangIBM Research

JinJun XiongIBM T.J. Watson Research

Chengmo YangUniv. of Delaware

Chia-Lin YangNational Taiwan Univ.

Zuochang YeTsinghua Univ.

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Yang (Cindy) YiVirginia Tech

Mehmet YildizCadence Design Systems

Shouyi YINTsinghua Univ.

Evangeline YoungThe Chinese Univ. of Hong Kong

Hao YuSouthern Univ. of Science and Technology, China

Shimeng YuGeorgia Institute of Technology

Xuan ZengFudan Univ.

Xuan (Silvia) ZhangWashington Univ. in St. Louis

Jishen ZhaoUC San Diego

Dakai ZhuUniv. of Texas at San Antonio

Qi ZhuNorthwestern Univ.

Cheng ZhuoZhejiang Univ.

Qiaosha ZouFudan Univ.

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CONFERENCE SPONSORS

About ACMACM,theAssociationforComputingMachinery,acm.org, is the world’slargesteducationalandscientificcomputingsociety,uniting

computingeducators,researchersandprofessionalstoinspiredialogue,shareresourcesandaddressthefield’schallenges.ACMstrengthensthecomputingprofession’scollectivevoicethroughstrongleadership,promotionofthehigheststandards,andrecognitionoftechnicalexcellence.ACMsupportstheprofessionalgrowthofitsmembersbyprovidingopportunitiesforlife-longlearning,careerdevelopment,andprofessionalnetworking.ACMprovidesthecomputingfield’spremierDigitalLibrary (DL), an invaluable online resource of over two million fully searchable pages of text, including a50+yeararchive,fromACM’shighqualityjournalsandproceedings.TheDLalsoreachestheentireworldofcomputingthroughthefullyintegratedGuidetoComputingLiterature.ACM’s37SpecialInterestGroups(SIGs)focusondifferentcomputingdisciplines.MorethanhalfofallACMmembersjoinoneormoreoftheseSpecialInterestGroups.TheSIGspublishnewslettersandsponsorimportantconferences such as SIGGRAPH, SPLASH including OOPSLA, DAC, ICCAD and CHI, giving members opportunitiestomeetexpertsintheirfieldsofinterestandnetworkwithotherknowledgeablemembers.Become an ACM member today and join thousands of other leading professionals, researchers and academicswhobenefitfromallACMhastooffer.JoinACMonlineatacm.org, or contact ACM directly byphone:800-342-6626(USandCanada)or212-626-0500(Global),byfax:212-944-1318,orbye-mail:[email protected].

Join ACM/SIGDA: The Resource For EDA ProfessionalsACM/SIGDA,(SpecialInterestGrouponDesignAutomation)providesabroadarray of resources to our members, to students, professors, industry professionals

and,totheEDAfieldingeneral.SIGDAsponsorsvariouseventstopromoteinteractionamongthecommunity to share the latest technical and professional advances. It also serves as a forum to support eventsthatnurturenewideasandinfusevitalityintonewemergingtrendsinthefield.SIGDAhasalonghistoryofsupportingconferencesandtheEDAprofessionincludingICCAD,DAC,DATE, and ASP-DAC, plus around 15 focused symposia and workshops. SIGDA supports various eventssuchas-theUniv.ResearchDemonstrationthathelpstofosterinteractionsbetweenstudentsandindustry;DesignAutomationSummerSchoolthatexposesstudentstotrendingtopics;YoungFacultyWorkshops;Ph.D.Forumsinconjunctionwithmajorconferences,designcontestssuchasCADAthlon.SIGDAfundsvariousscholarshipsandrecognizesoutstandingresearchpublications.Awardsrecognizesignificantcontributionsatallstagesoftheprofessionalcareerfromstudent awardstothePioneerAwardforLifetimeachievement.SIGDAhaslaunchednewprogramssuchas SIGDA Live, a series of monthly webinars on topics of general interest to the SIGDA community and a moreglobalE-Newsletterwithanewlyformededitorialboard.SIGDAalsosupportslocalchaptersthathelpwithprofessionalnetworking.SIGDAalsoadministratesStudentResearchCompetitiononbehalfof ACM.SIGDA pioneered electronic publishing of EDA literature, beginning with the DA Library in 1989. SIGDAalsoprovidesstrongsupportfortheACMjournalTODAES(TransactionsonDesignAutomationofElectronicSystems).MajorbenefitsprovidedtoSIGDAmembersincludefreeaccesstoallSIGDAsponsoredpublicationsintheACMDigitalLibrary,andreducedregistrationratesforSIGDAsponsoredevents.ForfurtherinformationonSIGDA’sprogramsandresources,seesigda.org.PleasejoinusinbuildingamorevibrantcommunityandvolunteerforSIGDA.


design automation

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CONFERENCE SPONSORS

IEEEIEEEistheworld’slargestprofessionalassociationdedicatedtoadvancing

technologicalinnovationandexcellenceforthebenefitofhumanity.IEEEanditsmembersinspireaglobalcommunitythroughIEEE’shighlycitedpublications,conferences,technologystandards,andprofessionalandeducationalactivities.

IEEE Council on Electronic Design Automation (CEDA)

TheIEEECouncilonElectronicDesignAutomation(CEDA)wasestablishedtofosterdesignautomationofelectroniccircuitsandsystemsatalllevels.TheCouncil’sfieldofinterestspansthetheory,implementation,anduseofEDA/CADtoolstodesignintegratedelectroniccircuitsandsystems.Thisincludestoolsthatautomatealllevelsofthedesign,analysis,andverificationofhardwareandembeddedsoftwareuptoandincludingcompleteworkingsystems.

CEDAenablestheexchangeoftechnicalinformationbymeansofpublications,conferences,workshops,andvolunteeractivities.

Asanorganizationalunit(OU)ofIEEE,CEDAhassevenmembersocieties,namely:AntennasandPropagation,CircuitsandSystems,Computer,ElectronDevices,ElectronicsPackaging,MicrowaveTheory&Techniques,andSolid-StateCircuitsSocieties.

FormoreinformationonCEDA,visit:ieee-ceda.org.

CASTheIEEECircuitsandSystemsSociety’sfieldofinterestspansthetheory,analysis,design(computeraideddesign),andpracticalimplementationofcircuits,andtheapplicationofcircuittheoretictechniquestosystemsandtosignalprocessing.Thecoverageofthisfieldincludesthespectrumofactivitiesfrom,andincluding,basic

scientifictheorytoindustrialapplications.

The IEEE Circuits and Systems Society (CASS) believes that the Grand Engineering Challenges of the 21st century can only be addressed in an inter-disciplinary and cross-disciplinary manner. TheSociety’suniqueandprofoundexpertiseinCircuits,Systems,Signals,Modeling,Analysis,andDesign can have a decisive impact on important issues such as Sustainable Energy, Bio-Health, GreenInformationTechnology,Nano-Technology,andScalableInformationTechnologySystems.

Our mission is to foster CASS members across disciplines to address humanity’s grand challenges byconceivingandpioneeringsolutionstofundamentalandappliedproblemsincircuitsandsystems.

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COOPERATING ENTITIES

IEEE Electron Devices Society

The IEEE Electron Devices Society (EDS) is involved in the advancement of electronics and electrical engineering through research, development, design, manufacture, materials, and applicationsofelectrondevices.EDSisconcernedwithtechnical,educational,scientificpublicationandmeetingactivitieswhichprovidebenefitstomemberswhilecontributingtowardstheprogressofthisfield.eds.ieee.org.

Thank You to our Technical Program Dinner Corporate Sponsor

Conference Sponsor Recognition

Monday Evening Reception, November 4

Coffee Breaks on Tuesday, November 5 and Evening Reception, November 6

Tuesday Evening Reception, November 5

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Are You Ready to Create Tomorrow’s Technology, Today?Explore career opportunities at Cadence

Make Your MarkCadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. Our Intelligent System Design™ strategy helps customers develop differentiated products in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial, and other market segments. Join our teams that are playing a valuable role in creating the technologies that modern life depends on. Apply today at www.cadence.com/cadence/careers.

Academic Network The Cadence® Academic Network is a knowledge network among universities, research institutes, industry advisors, and Cadence. To enjoy the benefits of collaboration with fellow experts, join us today at www.cadence.com/site/academicnetwork.

Cadence Talk at ICCAD Join us on Monday, November 4, from 5:45pm to 6:15pm in Westminster I, to hear a talk about “AI and Machine Learning at Cadence” by Anton Klotz, University Program Manager from Cadence.

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