computing with nano-crossbar arraysproject details gathers globally leading research groups working...

COMPUTING WITH NANO-CROSSBARARRAYS

The Twelfth International Conference on Advances in Circuits,Electronics and Micro-electronics (CENICS’19)Oct. 28th, 2019

Mustafa Altun, PhD

Electronics & Communication EngineeringIstanbul Technical University

Web: http://www.ecc.itu.edu.tr/

This project has received funding from the European Union's H2020 researchand innovation programme under the Marie Skłodowska-Curie grant agreement

No 691178.

This work is supported by the TUBITAK-2501project #218E068.

Project Details

Gathers globally leading research groups working on nanoelectronicsand EDA

Targets variety of emerging technologies including nanowire/nanotubecrossbar arrays, magnetic switch-based structures, and crossbarmemories

Contributes to the construction of emerging computers beyond CMOSby proposing nano-crossbar based computer architectures.

Budget: 724500 EURO

• Dr. Mustafa Altun, – Coordinator – Emerging Circuits and Computation

Group, Istanbul Technical University, Turkey

• Dr. Dan Alexandrescu, IROC Technologies, Grenoble, France

• Dr. Lorena Anghel, TIMA Lab., Grenoble, France

• Dr. Valentina Ciriani, ALOS Lab., University of Milan, Italy.

• Dr. Csaba A. Moritz, Nanoscale Computing Fabrics Lab., University of

Massachusetts, USA

• Dr. Kaushik Roy, Nanoelectronics Research Lab., Purdue University, USA

• Dr. Georgios Sirakoulis, Department of Electrical and Computer

Engineering, Democritus University of Thrace, Greece

• Dr. Mircea Stan, High-Performance Low-Power Lab., University of Virginia,

USA

• Dr. Mehdi B. Tahoori, Dependable Nano-Computing Group, Karlsruhe

Institute of Technology, Germany

Project Details

Project Details

Defect Tolerance

Defect-aware Defect-unaware Defect-aware

Perm

an

en

tD

efe

ct

To

lera

nce

Testing Transient FaultTolerance Performance

Tra

nsie

nt

Fau

ltT

ole

ran

ce

Variance Tolerance

Delay Power

Defect map

Perfo

rman

ce

Op

timiza

tion

Fa

bri

ca

tio

n

Determining TechnologyCrosspoint as

Memristor/Diode FET 4-Terminal

Determiningfunctionality

RedundantHardware

Size

Single OutputFunctions

Multiple OutputFunctions

Lo

gic

Syn

thesis

Two-terminal vs. Four-terminal

Four-terminal SwitchNano array

Closed Open

Switch


Shannon’s work: A Symbolic Analysis of Relay andSwitching Circuits(1938)


What are the Boolean functionsimplemented in (a) ad (b)?

Logic Synthesis

8

Defect Tolerance


Perm

an

en

tD

efe

ct

To

lera

nce


Tra

nsie

nt

Fau

ltT

ole

ran

ce

Variance Tolerance

Delay Power

Defect map

Perfo

rman

ce

Op

timiza

tion

Fa

bri

ca

tio

n




RedundantHardware

Size



Lo

gic

Syn

thesis

Diode/Memristor-based Model


Example: Implement the Boolean function f = A+B with diodebased nanoarrays.

Diode-resistor logic


Example: Implement the Boolean function f = AB with diodebased nanoarrays.

D1

D2

A

B

R1

f

Diode-resistor logic


Example: Implement the Boolean function f = AB + C D withdiode based nanoarrays.

FET-based Model

From Snider, G., et al., (2004). CMOS-like logic in defective, nanoscale crossbars. Nanotechnology.

FET-based Model

Example: Implement the Boolean function f = Aꞌ with FETbased nanoarrays using CMOS-like logic.

FET-based Model

Example: Implement the Boolean function f = (AB + C D)ꞌ withFET based nanoarrays using CMOS-like logic.

Four-terminal Switch-based Model

3 × 3 2D switching network and its lattice form

LE

FT

RIG

HTL

EF

T

RIG

HT

Four-terminal Switch-based Model

Switches are controlled by Boolean literals.

fL evaluates to 1 iff there exists a top-to-bottom path.

gL evaluates to 1 iff there exists a left-to-right path.

x9

x1 x4

x2 x5

x7

x8

x3 x6

TOP

BOTTOM

gL

0

1 0

1 1

1

0

0 1

TOP

BOTTOM

gL

Logic Synthesis Problem

How can we implement a given target Boolean functionfT with a lattice of four-terminal switches?

Example: fT = x1x2x3+x1x4

x2 x1

x1 x4

x3 x1

BOTTOM

TOP

x2 x4

x1 x1

x3 x4

BOTTOM

TOP

Logic Synthesis Problem

LE

FT

RIG

HT

Example: fT = x1x2x3+x1x4+x1x5

9 TOP-TO-BOTTOM PATHS!

Synthesis Method

Example: fT = x1x2x3+x1x4+x1x5

x1x2x3

x1x4

x1x5

x1

x2 x4 x5

x3 x4 x5 {x5}

{x1} {x1}

{x2} {x4}

{x1}

{x5}

{x3} {x4}

x1x2x3

x1x4

x1x5

x1

x2 x4 x5

x3 x4 x5

fTD = (x1+x2+x3)(x1+x4)(x1+x5)

fTD = x1 + x2x4x5 + x3x4x5

x5

x1 x1

x2 x4

x1

x5

x3 x4

x1x2x3

x1x4

x1x5

x1

x2 x4 x5

x3 x4 x5

Start with fT and its dual.

Assign each product of fT to acolumn.

Assign each product of fTD to

a row.

Compute an intersection setfor each site.

Arbitrarily select a literal froman intersection set and assignit to the corresponding site.

Experimental Results

Implementation of fXOR2 with different nanocrossbar types

Experimental Results

Defect/Fault Tolerance

13

Defect Tolerance


Perm

an

en

tD

efe

ct

To

lera

nce


Tra

nsie

nt

Fau

ltT

ole

ran

ce

Variance Tolerance

Delay Power

Defect map

Perfo

rman

ce

Op

timiza

tion

Fa

bri

ca

tio

n




RedundantHardware

Size



Lo

gic

Syn

thesis


Permanent Faults occur mostly in fabrication and are tolerated inpost-fabrication by redundancy and reconfigurability (mapping).Transient Faults occur in field and are tolerated by redundancy


Defect tolerance is achieved by realizing atarget logic function on a defective crossbarusing row and column permutations

For the worst-case, N!M! permutations arerequired to find a successful mapping for NXMcrossbar. Defect-unaware algorithms aim to find the

largest possible kXk defect-free sub-crossbarfrom a defective NXN crossbar where k ≤ N;

Defect-aware considers the defect characteristics(stuck-at-0 or stuck-at-1), then decide whichswitch to employ during the mapping.

Technology Development forFET/Diode/Memristor based Arrays

POST CMOS TECHNOLOGIES

Technology Development for Four-Terminal Switch based Arrays

How about the technology?

We propose CMOS-compatible technologywith TCAD simulations

By fitting the TCAD data to the standardCMOS current-voltage equations, we developa Spice model of a four-terminal switch

We are currently working toward thefabrication.

Device Structures

1: Diffusion region 2: Gate electrode 3. Gate insulator region

4: Local Oxidation of Silicon (LOCOS) or Shallow Trench Isolation (STI) layers

5: Bulk layer

THANK YOU!

Emerging Circuits and Computation GroupWeb: http://www.ecc.itu.edu.tr/

computing with nano-crossbar arraysproject details gathers globally leading research groups working...

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