1

Computer System Organization

I/O systemProcessor

CompilerOperating

System(Windows 98)

Application (Netscape)

Digital DesignCircuit Design

Instruction Set Architecture

° Coordination between levels of abstraction

Datapath & Control

transistors

MemoryHardware

Software Assembler

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Abstraction Levels of a Computer System

° Application S/W• MS Word computer as electronic type-writer

• MS Excel computer as electronic calculator

° System S/W• Compilers computer as translator (source to executable program)

• Operating Systems computer as machine that executes programs, stores files, prints content of files to printers, communicate with other computers

° Instruction Set• What basic operations can be carried out

• What, where, and how data can be stored & retrieved in/from memory

• How can data be exchanged to the outside “world”

° Computer H/W• The 5 components: Datapath, Control, Memory, Input, Output

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Levels of Programming Languages

High Level Language Program (e.g., C)

Assembly Language Program

Machine Language Program (80x86)

Control Signal Specification

Compiler

Assembler

Machine Interpretation

A = 25;

B = 8;

C = A * B;A dw 25B dw 8C resw 1mov eax, [A]mov ebx, [B]add eax, ebxmov [C], eax

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

°°

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Java: Interpreted Programming Language

Java Language Program

Byte Code

Machine Language Program (80x86)

Control Signal Specification

Java Compiler

Machine Interpretation

°°

Interpreter (Java Virtual Machine)+

Just In Time (JIT) Compiler

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Components of a Computer

KEYBOARD: to input command/data

MONITOR: to output data

SPEAKER: to output data

“CPU”: to process command & data

MOUSE: to input command/data

DISK: to input/output data

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Five main components of a computer

Processor (active)

Computer

Control(“brain”)

Datapath(“brawn”)

Memory(passive)

(where programs, data live whenrunning)

Devices

Input

Output

Keyboard, Mouse

Display, Printer

Disk (where programs, data live whennot running)

“CPU”

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Processor

° Responsible of executing program stored in memory

• read instructions & input data

• execute

• store results (output data)

° Datapath (“muscle”):• ALU: Aritmetic & Logical Unit

• Exposed register

- Size of register determines processor smallest data unit (i.e., 8-bit, 16-bit, 32-bit, 64-bit computers)

• Hidden register

° Control Unit (“brain”):• interprete instruction

• control data transfer between registers

• define processsor’s ‘language’ complexity (e.g., RISC vs. CISC)

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Memory

° Responsible of storing instructions/data

° Each unit of instruction/data is stored in a memory cell, whose address is known to the processor

° Any memory cell can be accessed by a processor randomly (RAM: random access memory)

° The amount of instruction/data accessed by a processor may vary (1, 2, ..., n memory cells at a time)

° To achieve trade-off between speed and cost, memory is structured hierarchically memory hierarchy

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Input/Output (Device)

° Responsible of communicating with the outside (of computer) world

° A device may serve as Input-only, Output-only, or both (Input-Output) device

• Input-only: keyboard

• Output-only: monitor display

• Input-Output: floppy disk, hard disk

° Data translation may be needed when processor exchanges data with an I/O device so humans can understand them

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Interconnection between components

 

Gbr. 5. (a) back view (b) side view

*Taken from http://www.ui.ac.id/pdpt/ppkk/PengenalanKomputer.html

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Interconnections between components

Proc

CachesProcessor-Memory Bus

Memory

I/O Devices:

Controllers

adapters

DisksDisplaysKeyboards

Networks

Interconnected by a BUS

I/O Bus

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Technology Trend

13

Year

Transistors

1000

10000

100000

1000000

10000000

100000000

1970 1975 1980 1985 1990 1995 2000

i80386

i4004

i8080

Pentium

i80486

i80286

i8086

Technology Trend: Microprocessor Capacity

2X transistors/ChipEvery 1.5 years

Called “Moore’s Law”

Alpha 21264: 15 millionPentium Pro: 5.5 millionPowerPC 620: 6.9 millionAlpha 21164: 9.3 millionSparc Ultra: 5.2 million

Moore’s Law

Pentium 4: 42 millionPentium III: 9.5 million

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Technology Trend: Processor Performance

0100200300400500600700800900

87 88 89 90 91 92 93 94 95 96 97

DEC Alpha 21264/600

DEC Alpha 5/500

DEC Alpha 5/300

DEC Alpha 4/266IBM POWER 100

DEC AXP/500

HP 9000/750

Sun-4/260

IBMRS/6000

MIPS M/120

MIPS M

2000

1.54X/yr

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Technology Trend: Memory Capacity (1 Chip DRAM)

size

Year

Bits

1000

10000

100000

1000000

10000000

100000000

1000000000

1970 1975 1980 1985 1990 1995 2000

year size(MB)

1980 0.0625

1983 0.25

1986 1

1989 4

1992 16

1996 64

2000 256

Now 1.4X/yr, or doubling every 2 years4000X since 1980

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Technology Trend: Disk Capacity

Year Areal Density1973 1.71979 7.71989 631997 30902000 17100

1

10

100

1000

10000

100000

1970 1980 1990 2000

Year

Are

al D

ensity

• Areal Density = BPI x TPI

- BPI: Bit Per Inch

- TPI: Tracks Per Inch

• Change slope 30%/yr to 60%/yr about 1991

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High Performance Computers

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Intel Pentium Pro Quad

• All coherence and multiprocessing glue in processor module

• Highly integrated, targeted at high volume

• Low latency and bandwidth

P-Pro bus (64-bit data, 36-bit addr ess, 66 MHz)

CPU

Bus interface

MIU

P-Promodule

P-Promodule

P-Promodule256-KB

L2 $Interruptcontroller

PCIbridge

PCIbridge

Memorycontroller

1-, 2-, or 4-wayinterleaved

DRAM

PC

I bus

PC

I busPCI

I/Ocards

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SUN Enterprise

° Proc + mem card - I/O card• 16 cards of either type• All memory accessed over bus, so symmetric• Higher bandwidth, higher latency bus

Gigaplane bus (256 data, 41 addr ess, 83 MHz)

SB

US

SB

US

SB

US

2 F

iber

Cha

nnel

100b

T, S

CS

I

Bus interface

CPU/memcardsP

$2

$

P

$2

$

Mem ctrl

Bus interface/switch

I/O cards

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Cray T3E

• Scale up to 1024 processors, 480MB/s links• Memory controller generates request message for non-local references• No hardware mechanism for coherence

- SGI Origin etc. provide this

Switch

P

$

XY

Z

External I/O

Memctrl

and NI

Mem

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Intel Paragon

Memory bus (64-bit, 50 MHz)

i860

L1 $

NI

DMA

i860

L1 $

Driver

Memctrl

4-wayinterleaved

DRAM

IntelParagonnode

8 bits,175 MHz,bidirectional2D grid network

with processing nodeattached to every switch

Sandia’ s Intel Paragon XP/S-based Super computer

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Memory bus

MicroChannel bus

I/O

i860 NI

DMA

DR

AM

IBM SP-2 node

L2 $

Power 2CPU

Memorycontroller

4-wayinterleaved

DRAM

General interconnectionnetwork formed from8-port switches

NIC

IBM SP-2

° Made out of essentially complete RS6000 workstations

° Network interface integrated in I/O bus (bw limited by I/O bus)

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Berkeley NOW

° 100 Sun Ultra2 workstations

° Inteligent network interface

• proc + mem

° Myrinet Network• 160 MB/s per link

• 300 ns per hop

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Intel 80x86 Architecture

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Intel History: ISA evolved since 1978

° 8086: 16-bit, all internal registers 16 bits wide; no general purpose registers; ‘78

° 8087: + 60 Fl. Pt. instructions, (Prof. Kahan) adds 80-bit-wide stack, but no registers; ‘80

° 80286: adds elaborate protection model; ‘82

° 80386: 32-bit; converts 8 16-bit registers into 8 32-bit general purpose registers; new addressing modes; adds paging; ‘85

° 80486, Pentium, Pentium II: + 4 instructions

° MMX: + 57 instructions for multimedia; ‘97

° Pentium III: +70 instructions for multimedia; ‘99

° Pentium 4: +144 instructions for multimedia; '00

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Architecture of Intel P6 (Pentium Pro)

Control Unit

Data Path

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Example: Pentium-based Computer

Processor/MemoryBus

PCI Bus

I/O Busses

Memory

Processor

I/O