computer system configuration and function computer architecture and design lecture 6
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Computer System Configuration and
Function
Computer Architecture and Design
Lecture 6
Youpyo Hong & Kangwoo Lee @ DGU
Micro-operation
Digital Modules are best defined by Registers Operations performed on the data stored in them
This “operation” is called the “micro-operation”
Microoperation (-op) An elementary operation performed on data stored in register(s) Results of operations may
Replace previous data, or Be transferred to another register
Example: Shift, Count, Clear, Load, Add, Sub, ...
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Definition of RTL
Hardware Organization is Best Defined by specifying Set of registers in it & their functions Sequence of -ops performed on data stored in registers Controls governing the execution of -ops
RTL (Register Transfer Language) Definition:
Symbolic notation describing data xfers & -ops between registers
Usefulness:
-ops imply the availability of hardware logic circuits that can perform specified -ops RTL can be transformed to hardware by tools
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-operations that we will learn
Register Transfer
Bus & Memory Transfer
Arithmetic -ops
Logic -ops
Shift -ops
Arithmetic Logic Shift Unit (ALU)
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Registers
Notation: Capital letters (for naming) + optional numerals
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Name Description Usage
AR Address Register To designate memory location
PC Program Counter To designate next instruction
IR Instruction Register To store the instr. to execute
DR Data Register To store operands / results
R1 General Register To store temporary data
7 6 5 4 3 2 1 0R1
R1
15 0
PC(H)
15 8 7 0
PC(L)
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Register Transfer
Example: R2 R1
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There are at least two registers (R1 & R2) in the system
There is a connected path between R1 & R2 for data movement
R2 has “parallel load” function
There are at least two registers (R1 & R2) in the system
There is a connected path between R1 & R2 for data movement
R2 has “parallel load” function
Transfer of the content in R1 into R2
Content of R1 does not change
Transfer of the content in R1 into R2
Content of R1 does not change
Hardware
Operation
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Control Function
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Goal: To let operations take place under a certain condition
Example: P: R2 R1
Register xfer from R1 to R2 is done only when P=1
ControlCircuit
R2
R1
clock
Load
P
n
P is set to 1 Xfer occurs
t t+1
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Basic Xfer Operations
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Symbol
Letters (+ Num)
Parenthesis
Arrow
Comma
Description
Denotes register
Denotes part of a register
Denotes information xfer
Separate simultaneous -ops
Examples
R1, AR, PC
R1(0-7), R2(L)
R2 R1
R2 R1, R1 R2
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Common Bus
Bus : Set of wires, one for each bit, thru which binary data are xferred
Common Bus Paths must exist to xfer data among many registers Control Signal determines registers for data movement
BUS C, R1 BUS R1 C
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RegisterRegister Register
RegisterRegister
RegisterRegister Register
RegisterRegister
Register-to-Register Connection Common Bus-based Connection
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Common Bus Control
Sender Side MUX selects the sender
Receiver Side Load signal is selected
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R1
R2
IR
DR
NR x 1MUX
Control Unit
Select
Load CommonBus
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Bus System for Registers
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4x1MUX
3 2 1 0
D2 C2 B2 A2
4x1MUX
3 2 1 0
D1 C1 B1 A1
4x1MUX
3 2 1 0
D0 C0 B0 A0
4x1MUX
3 2 1 0
3 2 1 0
D2 D1 D0
3 2 1 0
C2 C1 C0
3 2 1 0
B2 B1 B0
3 2 1 0
A2 A1 A0
S1
S0
Register D Register C Register B Register A
4 line
common
bus
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Three-State Bus Buffers
3-State Gates Output : 0, 1 & High Impedance Buffer gate is the most popular
Bus line with 3-state buffers
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2x4Dec.
Bus line for bit 0A0
B0
C0
D0
S1
S0
Enable
Select
E
0
1
2
3
Input A
Cmtr C
Output:Y = A if C=1H.I. If C = 0
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Memory Transfer
Need to specify memory location of interested data
Example:
Read: DR M[AR]
Write: M[AR] DR
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Arithmetic Microoperations
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Basic Arithmetic -ops : +, -, Increment, Decrement & Shift
Example: R3 R1 + R2
There are at least three registers (R1, R2, R3)
There are connected paths among R1, R2 & R3
There is an functional unit that can perform arithmetic addition
R3 has “parallel load” function
There are at least three registers (R1, R2, R3)
There are connected paths among R1, R2 & R3
There is an functional unit that can perform arithmetic addition
R3 has “parallel load” function
Perform addition of the contents stored in R1 and R2
Transfer of the result into R3 Contents of R1 & R2 do not change
Perform addition of the contents stored in R1 and R2
Transfer of the result into R3 Contents of R1 & R2 do not change
Hardware
Operation
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Basic Arithmetic -ops
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Contents of R1 plus R2 xferred to R3
Contents of R1 minus R2 xferred to R3
Complement contents of R2 (1’s complement)
2’s complement of R2 (negate)
Description
R3 R1 + R2
R3 R1 - R2
R2 R2’
R2 R2’ + 1
Symbol
R1 plus 2’s complement of R2 (subtraction)
Increment content of R1 by 1
Decrement content of R1 by 1
R3 R1 + R2’ + 1
R1 R1 + 1
R1 R1 - 1
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Binary Adder
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FA
C4
B3 A3
S3
FAC3
B2 A2
S2
FAC2
B1 A1
S1
FAC1
B0 A0
S0
C0
xS
C
yz
Full Adder
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Binary Adder-Subtractor
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FA
C4
B3 A3
S3
FAC3
B2 A2
S2
FAC2
B1 A1
S1
FAC1
B0 A0
S0
C0
M
If M = 0 A + BIf M = 1 A + (B’ + 1) A - B
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Arithmetic Circuit
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4x1 MUX
S1
S0
0123
X1 C1
FAY1 C2
D1
A1
B1
4x1 MUX
S1
S0
0123
X2 C2
FAY2 C3
D2
A1
B1
4x1 MUX
S1
S0
0123
X0 C0
FAY0 C1
D0
A1
B1
4x1 MUX
S1
S0
0123
X3 C3
FAY3 C4
D3
A1
B1
Cout
Cin
S1, 0
0
0 0 0 B D = A + B Add
0 0 1 B D = A + B + 1 Add w/ carry
0 1 0 B’ D = A + B’ Sub w/ barrow
0 1 1 B’ D = A + B’+ 1 Sub
1 0 0 0 D = A Xfer A
1 0 1 0 D = A + 1 Inc. A
1 1 0 1 D = A - 1 Dec. A
1 1 1 1 D = A Xfer A
S0 S1 Cin Y
OutputD=A+Y+Cin
-opsSelect
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Logical Microoperation
Binary operations for strings of bits stored in registers.
Example1: P: R1 R1 R2
Example2: Mixed use of Operators
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1010 Content of R1
1100 Content of R2
0110 Content of R1 when P=1
P + Q: R1 R1 + R2, R3 R4 R5
OROperation
AddOperation
OROperation
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H/W Implementation of Some Logic -ops
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0000000011111111
F 0 ClearAND
Transfer A
Transfer B
EX-OROR
NOREX-NOR
Comple. B
Comple. A
NANDSet to all 1’s
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
-ops Name
Allpossiblefunctions
fortwo
variables
Boolean Function
F0 = 0 F1 = xy F2 = xy’ F3 = x F4 = x’y F5 = y F6 = x y F7 = x + y F8 = (x + y)’ F9 = (x y)’ F10 = y’ F11 = x + y’ F12 = x’ F13 = x’ + y F14 = (xy)’ F15 = 1
0 00 11 01 10 00 11 01 10 00 11 01 10 00 11 01 1
0000111100001111
F A B F A B’ F A F A’ B F B F A B F A B F (A B)’ F (A B)’ F B’ F A B’ F A’ F A’ B F (A B)’ F all 1’s
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H/W Implementation of Some Logic -ops
AND, OR, XOR & Complement , only
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Ai
Bi
S1
S0
Ei
4 x 1
MUX
0
1
2
3
Comple. A1 1 E A’ EX-OR1 0 E A B
OR0 1 E A B AND0 0 E A B
OperationS1 S0 Output
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Shift Operation – Logical Shift
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R1 shl R1R1 shl R1
0 1 1 0 1
1 1 0 1 00
SerialInput
Lost
R1 shr R1R1 shr R1
0 1 1 0 1
0 0 1 1 0 1
SerialInput
Lost
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Shift Operation – Circular Shift
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R1 cil R1R1 cil R1
0 1 1 0 1
1 1 0 1 0
R1 cir R1R1 cir R1
0 1 1 0 1
1 0 1 1 0
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Shift Operation – Arithmetic Shift
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R1 ashr R1R1 ashr R1
0 1 1 0 1
0 0 1 1 0 1
Sign Lost
1 1 1 0 1
1 1 1 1 0 1
Sign Lost
Complementedform of zero
zero
Divide by 2
Keep the sign bit
MSB of Mag. is Zero, always
NOTE:
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R1 ashl R1R1 ashl R1
0 0 1 0 1
0 1 0 1 00
SerialInput
Lost
Sign
1 1 0 0 1
1 0 0 1 01
SerialInput
Lost
Sign
Complementedform of zero
Actually, insert Zero
at MSB position
0 1 1 0 1
1 1 0 1 00
SerialInput
Lost
Sign
1 0 0 0 1
0 0 0 1 00
SerialInput
Lost
Sign
Complementedform of one
Change of Sign bit
Overflow
Overflow
Condition:
Vs = Rn-1 Rn-2
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H/W Implementation of Shift -ops
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MUXS
01
H0
MUXS
01
H1
MUXS
01
H2
MUXS
01
H3
A0
A1
A2
A3
Select: 0 shift right (down) 1 shift left (up)
Serial Input
Serial Input
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Arithmetic Logic Unit with Shift -ops
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Onestage
ofarithmetic
circuit(Fig. 4.9)
Onestage
oflogiccircuit
(Fig. 4.10)
4 x 1 MUX
S
0
1
2
3
S3
S2
S1
S0
Bi
Ai
Bi-1
Ai-1shl
Ei
Di
Fi
Ci
Ci+1
shr 14 -opsin all
0 0 0 0 00 0 0 0 10 0 0 1 00 0 0 1 10 0 1 0 00 0 1 0 10 0 1 1 00 0 1 1 10 1 0 0 x0 1 0 1 x0 1 1 0 x0 1 1 1 x1 0 x x x1 1 x x x
S3 S1 Cin
S2 S0
F A Inc.Add
Add w/ carrySub w/ borrow
SubDec.
-ops Name
F A+1F A+BF A+B+1 F A+B’ F A+B’+1 F A-1F AF A BF A BF A B F A’F shr A F shl A