computer structure slides

Computer Structure

Mr Arthur

Aims of Lesson 1

1. To discuss the 3 main parts of the processor

2. To discuss the functions of these 3 parts

3. To introduce the address, data and control buses

Block Diagram of the Computer System

PROCESSOR

MAIN MEMORY

BACKING STORAGE DEVICES

INPUT DEVICES

OUTPUT DEVICES

Parts of the Processor Control Unit

Makes sure the program instructions are carried out in the correct order

Controls the ALU and Registers Makes sure everything happens in the correct place at

the correct time Registers

A group of storage locations in the processor for holding instructions being executed and addresses to be accessed

Arithmetic Logic Unit Carries out all calculations in the processor Carries out all logic functions using AND, OR and NOT

gates

The Processor Structure

Main Memory

Other registers

Arithmetic and Logic

Unit

Memory Address Register

Memory Data

Register

Control Unit

Address Bus

Data Bus

Control Bus

Electronic Clock

Clock Pulses

Buses

Buses Three sets of wires

called buses connect the processor to the memory and input/output devices

Address Bus Data Bus Control Bus

Buses

Address Bus The address bus carries the address

information from the processor to main memory and is unidirectional

The number of wires in the address bus affects how many storage locations can be accessed

Each of the wires in the bus can be switched on or off

A typical microcomputer has 32 wires in the address bus and can therefore address 2 locations

32

Using 2 wires you could address 4 locations i.e.

01

10

00

11

4 wires = 16 locations

8 wires = 256 locations

16 wires = 65,536 locations

Aims of Lesson 2

1. To revise the role of the address bus

2. To introduce the data and control buses

3. To discuss the different control lines1. Read/Write

2. Maskable/Non Maskable Interrupt

3. Reset


Main Memory

Other registers


Unit


Memory Data

Register

Control Unit

Address Bus

Data Bus

Control Bus

Electronic Clock

Clock Pulses

1000 0001

Address Bus

The address bus carries the address information from the processor to main memory and is unidirectional

4 wires = 16 locations 8 wires = 256 locations 16 wires = 65,536 locations 32 wires = 4,294,967,292 locations0000 0000 0000 0000 0000 0000 0000 00001111 1111 1111 1111 1111 1111 1111 1111


Main Memory

Other registers


Unit


Memory Data

Register

Control Unit

Address Bus

Data Bus

Control Bus

Electronic Clock

Clock Pulses

1001 0111

1001 0111

READ LINE


Main Memory

Other registers


Unit


Memory Data

Register

Control Unit

Address Bus

Data Bus

Control Bus

Electronic Clock

Clock Pulses

0001 0001

READ LINE


Main Memory

Other registers


Unit


Memory Data

Register

Control Unit

Address Bus

Data Bus

Control Bus

Electronic Clock

Clock Pulses

0001 0001

WRITE LINE

Buses

Data Bus The data bus carries data to and from the processor The data bus is therefore bi-directional or 2 way The number of wires in the data bus determines the

quantity of data that the bus can carry Increasing the number of wires in the data bus is one

method of improving computer performance

Control Bus The control bus is made up of a number of

separate wires each with their own functions Read/Write Line

Reading from or writing to Main Memory Reset

Used to return the processor to its initial state when the system freezes

Clock The clock line carries a series of clock pulse at a

constant rate. These pulses synchronise the processing Measure in Giga hertz

Control Bus

Interrupts A signal from an input or output device that

causes a break in the processor’s current program, for example, printer out of paper etc Maskable

A piece of code can be written to ignore certain interrupts

Non Maskable Interrupts The processor cannot mask or ignore the interrupt

Aims of Lesson 3

Last Lessons To revise the 3 different

buses1. Address2. Data 3. Control

To discuss the different control lines

1. Read/Write2. Maskable/Non Maskable

Interrupt3. Reset4. Clock

Today’s Lesson Discuss the Fetch Execute

cycle Total Addressable Memory

Memory Read Operation

Main Memory

Other registers


Unit


Memory Data

Register

Control Unit

Address Bus

Data Bus

Control Bus

Electronic Clock

Clock Pulses

1001 0111

READ LINE

Fetch Execute Cycle

1. The processor places a value in the Memory Address Register and sets up the Address Bus with address

2. Control Unit activates the Read line

3. Instruction is transferred from memory to processor using data bus

4. Instruction is decoded

5. Instruction is executed This may result in another Memory Read Operation or a Memory Write Operation

Memory Read Operation

Memory Write Operation

Main Memory

Other registers


Unit


Memory Data

Register

Control Unit

Address Bus

Data Bus

Control Bus

Electronic Clock

Clock Pulses

0001 0001

WRITE LINE

Memory Write Operation

1. The processor sets up the Address bus

2. Processor sets up the data bus with value to be written to memory

3. Write line is activated4. Contents are transferred to

the required storage location in Main Memory

Total Addressable Memory

= Number of storage locations X Size of each storage location

What is the total addressable memory if you have an 8 bit address bus and a 16 bit data bus?

= 2 X 16= 256 X 16 = 4096 bits

8= 512 kilobytes

8


What is the total addressable memory if you have a 32 bit address bus and a 16 bit data bus?

= 2 X 16 bits2 X 2 bytes = 2= 1 Gigabyte X 2= 8 Gigabytes

2 = 1 kilobyte 2 = 1 megabyte 2 = 1 gigabyte

32

32

33

10

20

30

3

Aims of Lesson 4Last Lessons To revise the 3 different

buses1. Address2. Data 3. Control




Discuss the Fetch Execute cycle


Today’s Lesson Elements of Computer

Memory Registers Cache Main Memory Backing Storage

Types of RAM Dynamic Random Access

Memory Static Random Access

Memory Video Random Access

Memory

Computer Memory

The elements of computer memory are registers, cache, main memory and backing storage

Registers Storage locations inside

the processor where data can be accessed immediately, or around 1 nanosecond 10 seconds

-9

Cache Memory

A small amount of memory used to store often used instructions

Level 1 Cache = build in to the processor chip, speeds of access = 5 nanoseconds

Level 2 Cache = build on to processor or very close to it,

speed of access = 15 nanoseconds

Cache Memory (SRAM)

ProcessorMain

Memory (DRAM)

Dynamic Random Access Memory

DRAM is a type of RAM chip which needs to have its contents constantly refreshed (about 1000 times per second)

Typical access time = 50 nanoseconds Majority of computer’s main memory is made

up of DRAM as it is much cheaper that SRAM

Static Random Access Memory

Used in the processors cache memory

SRAM does not need to be constantly refreshed

Much faster that DRAM, typically 10 nanoseconds

Keep contents as long as power is applied to RAM chip

Aims of Lesson 5Last Lessons To revise the 3 different buses

1. Address2. Data 3. Control




Discuss the Fetch Execute cycle

Total Addressable Memory Elements of Computer Memory

Register, Cache, Main Memory, Backing Storage

DRAM, SRAM

Today’s Lesson Video Random Access

Memory Types of ROM Backing Storage Comparing Computer Memory Measures of Performance

Video Random Access Memory

VRAM is used to hold the data which is displayed on the monitor

The amount of VRAM is directly related to the number of colours and the screen resolution

VRAM is sometimes contained in a separate graphics card and can be upgraded to display 3D graphics

ROM Read Only Memory is a type of Memory where the

contents are stored permanently Holds the Bootstrap loader Programmable Read Only Memory = is empty of

data when you buy it and is programmed by the user

Erasable PROM = can be programmed, erased and reprogrammed, using a UV light

Flash ROM = May be programmed whilst inside the computer and used in USB Pens and Memory cards for cameras

Type of Memory Speed (nano seconds)

Registers Immediate 1

Cache

SRAMVery Fast 5/15

Main Memory

DRAMFast 50

Main Memory

ROMFast 50 to 100

Backing Store

Hard Disk (Virtual Memory)Slow 1000000

Backing Store

Optical DiskSlow >1000000

Measures of Performance Clock Speed = The number of pulses per second

measured in Ghz More clock cycles = more data fetched and executed Fetching 1 instruction may take 10 clock cycles MIPS = Millions of Instructions per second Measure of the average number of machine code

instructions executed FLOPS = Floating Point Operations Per Second Measure of the Arithmetical Calculating Speed of the

computer

Aims of Lesson 6Last Lessons To revise the 3 different buses

1. Address2. Data 3. Control


1. Read/Write2. Maskable/Non Maskable Interrupt3. Reset4. Clock

Discuss the Fetch Execute cycle Total Addressable Memory Elements of Computer Memory

Register, Cache, Main Memory, Backing Storage

DRAM, SRAM Video Random Access Memory Types of ROM Backing Storage Comparing Computer Memory Measures of Performance

Today’s Lesson Computer Structure Revision

Quiz Factors affecting system

performance Data Bus Width Use of cache Rate of transfer from

peripherals Other Factors

Increasing clock speed Adding more Main Memory Increasing VRAM Adding more processors

Computer Structure Quiz

1. Name the 3 buses connecting the processor to Memory and Input and Output devices

2. List 4 functions of control bus3. Give the 5 steps in the fetch execute cycle4. My computer has a 24 bit address bus and

a 16 bit data bus. Calculate the total addressable memory

5. Which bus affects computer performance, explain your answer

Computer Structure Quiz

6. What is cache memory

7. Name the 2 main types of RAM

8. List the following in order of speed of access, with the fastest first

Cache Registers Backing Storage Main Memory

9. Name the 3 different types of ROM

10. Give 3 measures of computer performance

Factors Affecting System Performance

Data Bus Width Increasing the data bus width

increases the quantity of data flowing between the processor and memory

word length Use of cache

It is much faster to access instructions and data from cache than main memory

Cache may have a separate data bus called the backside bus

Rate of transfer from peripherals The rate of transfer is

determined by the type of interface connecting peripheral to processor

USB 1 = 12 Megabits per second

USB 2 = 480 Megabits per second

Increasing clock speed Adding more Main

Memory Increasing VRAM Adding more processors

Current Trends

1. Increasing clock speeds1. Increase cannot go on indefinately

2. Heat and power consumption problems

2. Increasing Memory1. Increased memory required to hold the

operating system

2. Memory required for individual applications has risen

3. Increasing Backing Storage1. Increase in Video cameras, digital cameras,

mp3s require more backing storage

Data Representation – Learning Aims

1. Detailed description of the purpose of the ALU and the Control Unit

2. Description of the purpose of registers, to hold data being processed, instructions being executed, and addresses to be accessed

3. Description of the function of the data bus and the address bus

4. Description of the read, write and timing functions of the control lines

5. Identification of other control lines, including reset and interrupt lines


6. Simple description, referring to the appropriate buses and control lines, of the steps in the fetch and execute cycle

7. Description of the following elements of computer memory, registers, cache, main memory and backing storage

8. Distinction between the above elements of memory according to function and speed of access

9. The concept of addressability


10. Description and evaluation of the following measures of performance; clock speed, MIPS, FLOPS and application based tests

11. Description of the effect the following factors have on system performance; data bus width, use of cache memory, rate of data transfer to and from peripherals

12. Description of the following trends in computer hardware, including increasing clock speeds, increasing memory and backing storage capacity