computer science 37 lecture 4
TRANSCRIPT
-
8/4/2019 Computer Science 37 Lecture 4
1/17
1
4.1
Lecture4
MoreCombinationalCircuits,
MemoryElementsand
Clocks
-
8/4/2019 Computer Science 37 Lecture 4
2/17
2
4.2
XNORfromNANDs andNORs
A B BA
BAABBA +=
(i) FromNANDs:startwithSOPform
andapplyinvolution.
(ii) FromNORs:getthe0-rows,writethe
maxterms andtaketheproduct,then
applyinvolution:
))(( BABABAF ++==
)()( BABAFF +++==
-
8/4/2019 Computer Science 37 Lecture 4
3/17
3
4.3
MultiplexerThinkofitasamulti-wayswitchoraselector.
0I
1I
Out
SELECT
2-to-1MUX
-
8/4/2019 Computer Science 37 Lecture 4
4/17
4
4.4
Multiplexer
4-to-1MUX
Question: Howmanybitsare
neededtoselectwhichinputwillbe
shownattheoutput?
-
8/4/2019 Computer Science 37 Lecture 4
5/17
5
4.5
GenericDesignforaMultiplexer
Question: ForanN-to-1MUX,
whatkindofdecoderwillwe
need?
-
8/4/2019 Computer Science 37 Lecture 4
6/17
6
4.6
Exercise:DesignaDemultiplexer
0O
In
SELECT
1O
2O
nO
1-to-NDEMUX
-
8/4/2019 Computer Science 37 Lecture 4
7/17
7
4.7
ProgrammableLogicArray(PLA)
AND gates
OR gates
Product terms
Outputs
Inputs
Usedtoimplementgeneric
functions
directlyfromtheSOP
canonicalform.
Theyarecalled
programmablebecausethey
haveafixedstructureandthe
designeronlyhastodefine
connectionsinorderto
implementafunction.
nnF 22:
-
8/4/2019 Computer Science 37 Lecture 4
8/17
8
4.8
InsideaPLA
A
B
C
Inputs
D
E
F
Outputs
AND plane
OR plane
EachcolumnintheAND
planecorrespondstoa
minterm.Eachrowinthe
ORplanecorrespondsto
asum ofminterms.
)()()( CABCBABCAE++=
Thereisanelectronicallyprogrammablesimilarcomponent
calledPAL(programmablearraylogic).
-
8/4/2019 Computer Science 37 Lecture 4
9/17
9
4.9
MemoryElements
Nothingweveseensofarhastheabilityto
storedata,notevenasinglebit.
Whenyouremove(orchange)anyinput,
afterapropagationdelay,theoutput
correspondinglychanges.
Aswewellknow,acomputerneedsto
rememberpiecesofinformation
-
8/4/2019 Computer Science 37 Lecture 4
10/17
10
4.10
TheS-RLatch
not
allowed
nochange
S R Q
QQS
QQR
=+=
=+=
00
00
10
011
==
==+=
QS
QQR
11
010
==
==+=
QS
QQR
Note: statechangeshappenwhentheyhappen.
Youcantcontrolwhen.
-
8/4/2019 Computer Science 37 Lecture 4
11/17
11
4.11
Clocks
Clock period Rising edge
Falling edge
Aclocksignal isasquarewaveform(usuallysymmetrical)
definedbyaperiodorcycletime.Itisareferencesignalthat
allowsonetomeasurethepassageoftime.
Theclockrate orclockfrequency istheinverseofthecycle
timeandismeasuredinHertz:
secondperntimesHertz =n
-
8/4/2019 Computer Science 37 Lecture 4
12/17
12
4.12
ClockEdges
Clock period Rising edge
Falling edge
Ourcircuitswillallbeedge-triggered,thatis,thingshappen
onlywhenclockvalueschangefor0-to-1or1-to-0.
Notethattheclockperiodmustbechosensothatitislong
enoughforallsignalsinacombinationalcircuittostabilize.
Definition: setuptime istheminimumtimethattheinputs
mustbevalidbeforetheclockedge.
Definition: holdtime istheminimumtimeduringwhichtheinputsmuststayvalidaftertheclockedge.
-
8/4/2019 Computer Science 37 Lecture 4
13/17
13
4.13
TheDFlip-Flop
D
C
Q
Q
Whentheclocklinetransitionsfrom0to1,thevaluepresentedat
theD lineisreadintothecomponentandbecomesthestateofthe
flip-flop.
-
8/4/2019 Computer Science 37 Lecture 4
14/17
14
4.14
Register:MorethanaSingleBit
D
C
Q D
C
Q D
C
Q D
C
Q
clock
nR 1nR 2nR 0R
nD 1nD 2nD 0D
-
8/4/2019 Computer Science 37 Lecture 4
15/17
15
4.15
RegisterFile:MorethanaSingleRegister
Read registernumber 1 Read
data 1
Readdata 2
Read registernumber 2
Register fileWriteregister
Writedata Write
-
8/4/2019 Computer Science 37 Lecture 4
16/17
16
4.16
InsideaRegisterFile:ReadPorts
M
ux
Register 0
Register 1
Register n 1
Register n
M
ux
Read data 1
Read data 2
Read register
number 1
Read register
number 2
-
8/4/2019 Computer Science 37 Lecture 4
17/17
17
4.17
InsideaRegisterFile:WritePorts
n-to-1
decoder
Register 0
Register 1
Register n 1
C
C
D
D
Register n
C
C
D
D
Register number
Write
Register data
0
1
n 1
n