computer organization, unit 1 & 2

7/28/2019 computer organization, Unit 1 & 2

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Chapter 1. Basic Structure of

Computers


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pesse computer organization unit-1 2

INTRODUCTION

This chapter discusses the computerhardware, software and their interconnection,and it also discusses concepts like Computer types Functional Units Bus Structures

Performance Multiprocessor, RISC and CISC systems.


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COMPUTER TYPES

Computers are classified based on the parameters like

Speed of operation

Cost

Computational power

Type of application


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DESK TOP COMPUTER Eg: Personal computers which is used in homes and offices

Advantage: Cost effective, easy to operate, suitable for general purposeeducational or business application

NOTEBOOK COMPUTER Compact form of personal computer (laptop)

Advantage is portability


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WORK STATIONS

More computational power

Costlier

Used to solve complex problems which arises in engineering application (graphics,CAD/CAM etc)

ENTERPRISE SYSTEM (MAINFRAME)

More computational power

Larger storage capacity

Used for business data processing in large organization

Commonly referred as servers or super computers


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SERVER SYSTEM

Supports large volumes of data which frequently need to be accessed or to bemodified

Supports request response operation

SUPER COMPUTERS

Faster than mainframes

Helps in calculating large scale numerical and algorithm calculation in short span

of time

Used for aircraft design and testing, military application and weather forecasting


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Functional Units


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Functional Units

Figure 1.1. Basic functional units of a computer.

I/O Processor

Output

Memory

Input andArithmetic

logic

Control


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Information Handled by a

Computer Instructions/machine instructions Govern the transfer of information within a computer as well

as between the computer and its I/O devices

Specify the arithmetic and logic operations to be performed

List of instructions is called a Program

Data Used as operands by the instructions


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INPUT UNIT:Converts the external world data to a binary format, which can be understand byCPUEg: Keyboard, Mouse, Joystick etc

OUTPUT UNIT:

Converts the binary format data to a format that a common man can understand

Eg: Monitor, Printer, LCD, LED etc


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Memory Unit

Store programs and data

Two classes of storage Primary storage

Fast Programs must be stored in memory while they are being executed

Large number of semiconductor storage cells

Processed in words

Distinct Address associated with each location

Secondary storage larger and cheaper


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Arithmetic and Logic Unit (ALU)

Most computer operations are executed in

ALU of the processor.

Load the operands into memory bring them

to the processor and store them in registers

perform operation in ALU store the result

back to memory or retain in the processor.


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Control Unit

All computer operations are controlled by the controlunit.

The timing signals that govern the I/O or data or anytransfers are also generated by the control unit.


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Operations of a computer:

Accept information in the form of programs and datathrough an input unit and store it in the memory

Fetch the information stored in the memory, underprogram control, into an ALU, where the information is

processed

Output the processed information through an outputunit

Control all activities inside the machine through acontrol unit


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Basic Operational Concepts


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Review

Activity in a computer is governed by instructions.

To perform a task, an appropriate program consisting of a

list of instructions is stored in the memory.

Individual instructions are brought from the memory intothe processor, which executes the specified operations.

Data to be used as operands are also stored in the

memory.


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A Typical Instruction

Add LOCA, R0

Add the operand at memory location LOCA to theoperand in a register R0 in the processor.

Place the sum into register R0.

The original contents of LOCA are preserved.

The original contents of R0 is overwritten.

Instruction is fetched from the memory into the

processor the operand at LOCA is fetched and added tothe contents of R0 the resulting sum is stored inregister R0.


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Prev example combines a memory access

operation with an ALU operation

This can be realized asLoad LOCA,R1

Add R1,R0

Transfers b/w the memory and the cpu arestarted by sending the address of the location

to memory unit and issuing the appropriate

control signals


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Connection Between the Processor

and the Memory

i u r 1. . nn c ti n t n t h r c r n th m m r .

rc rI

n t r l

LU

n-

n n r l u r r i t r


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Registers

Instruction register (IR)

instruction register holds the instruction that iscurrently being executed.

Instruction present in IR will be decoded by whichprocessor understand what operation it has toperform

Program counter (PC)program counter keeps track of execution of

program.

Increments the contents of PC by 1, so that it points

to the next instruction address


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General-purpose register (R0 Rn-1)

Memory address register (MAR)holds the address of the location to beaccessed.

Memory data register (MDR)

contains the data to be written into or read out

of the addressed location.


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Typical Operating Steps

Programs reside in the memory through inputdevices

PC is set to point to the first instruction

The contents of PC are transferred to MAR

A Read signal is sent to the memory

The first instruction is read out and loaded into

MDR

The contents of MDR are transferred to IR

The instruction is ready to be decoded and

executed


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Typical Operating Steps (Cont)

If the instruction involves an operation beperformed by ALU, then Get operandsGeneral-purpose register

Memory (address to MAR Read MDR to ALU)

Perform operation in ALU

Store the result back

To general-purpose registerTo memory (address to MAR, result to MDR Write)

During the execution of current instruction ,PC is incremented to the next instruction


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Interrupt

Execution may preempted if some device needs urgent servicing. Device raises an interrupt signal.

Interrupt: request from an I/O device for service by the

processor.

Processor provides requested service by executing anappropriate interrupt service routine.

Before servicing the interrupt the contents of PC, general-

purpose registers, and some control information are saved in

memory After completion of interrupt service routine, state of the

processor is restored and interrupted program may continue.


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Bus Structures

There are many ways to connect different

parts inside a computer together.

A group of lines that serves as a connecting

path for several devices is called a bus.

Address/data/control


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Bus Structure

Single-bus

i r . . in l - r r .

m rn ut ut ut r c r


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Single-bus

Simplest way of interconnecting functional

units

All units are connected to this bus

Can be used for only one transfer at a time,

thereby only 2 units can actively use the bus

at a time

Low Cost and flexibility for attaching

peripheral devices


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Multiple Buses

To improve performance multibus structure canbe used

In two bus structure : One bus can be used to

fetch instruction other can be used to fetch data,required for execution.

Thus improving the performance

Also buffer registers can be used with the devices

to hold the information during transfers

smoothes out the timing difference between the

c u memor and i o devices


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Performance


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Performance

Processor time to execute a program depends on the hardwareinvolved in the execution of individual machine instructions.

Mainmemory Processor

Bus

Cachememory

Figure 1.5. The processor cache.


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Processor Clock

Processor circuits are controlled by a timing

signal clock

Clock defines regular time intervals clock

cycles

Each instruction is divided into several basic

steps, each of which completes in one clock

cycle.


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P length of one clock cycle is an important parameterthat affects processor performance.

The inverse of P is the clock rate R = 1/P which ismeasured in cycles per second (frequency or clock

frequency) Clock rates ranges from few hundred million to over a

billion cycles per second

The term cycles per second used to measrue clock rate is

termed as Hertz (Hz).MillionMega(M), billion Giga (G)

500 million/second500 MHz

1250 million per second is 1.25 GHs


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Basic Performance Equation

T processor time required to execute a program that has beenprepared in high-level language

N number of actual machine language instructions needed tocomplete the execution (note: loop)

S average number of basic steps needed to execute one machine

instruction. Each step completes in one clock cycle R clock rate

R

SNT

The execution time T has to be minimized for better performance. For which

values ofN and S must be minimized and value ofR must be enhanced at the

same time.


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Clock Rate

Increase clock rate

Improve the integrated-circuit (IC) technology to make the

circuits faster

Reduce the amount of processing done in one basic step.Thiswill reduce clock period P and enhances R the clock rate.


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Performance Measurement

Measure computer performance using benchmark programs.

System Performance Evaluation Corporation (SPEC) selects and publishesrepresentative application programs for different application domains,together with test results for many commercially available computers.

A benchmark program from a suite of benchmark program will be selectedand compiled for test computer.

The same benchmark program will be compiled and executed on one ofthe typical computer which be selected as a Reference Computer

SPEC95- reference comp- sun sparc station SPEC2000- reference comp- Ultra sparc10 workstation with a 300MHz

UltraSparc Processor


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Performance Measurement

Running time on a Reference Computer

Running time on a test ComputerSPEC Rating =


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EVOLUTION OF COMPUTERS

FIRST GENERATION (1945 1955)

Program and data reside in the same memory (stored program concepts

John vonNeumann)

ALP was made used to write programs

Vacuum tubes were used to implement the functions (ALU & CU design)

Magnetic core and magnetic tape storage devices are used


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SECOND GENERATION (1955 1965)

Transistor were used to design ALU & CU

HLL is used (FORTRAN)

To convert HLL to MLL compiler were used

Separate I/O processor were developed to operate in parallel with CPU, thusimproving the performance


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THIRD GENERATION (1965-1975)IC technology improved

Improved IC technology helped in designing low cost high speed processor andmemory modules

Multiprogramming, pipelining concepts were incorporated

DOS allowed efficient and coordinate operation of computer system withmultiple users

Cache and virtual memory concepts were developed


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FOURTH GENERATION (1975-1985)

With VLSI technology a single chip CPU was developed

Termed asmicroprocessor

INTEL, MOTOROLA, TEXAS,NATIONAL semiconductors stared developingmicroprocessor

Workstations, microprocessor (PC) & Notebook computers were developed

Interconnection of different computer for better communicationLAN,MAN,WAN

Computational speed increased by 1000 times

Specialized processors like Digital Signal Processor were also developed


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BEYOND THE FOURTH GENERATION

(1985 TILL DATE)Computers featuring AI

High speed processor - Ghz speed


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Chapter 2. Machine

Instructions andPrograms


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Objectives

Machine instructions and program execution, including

branching and subroutine call and return operations.

Number representation and addition/subtraction in the

2s-complement system. Addressing methods for accessing register and memory

operands.

Assembly language for representing machine instructions,

data, and programs.

Program-controlled Input/Output operations.


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Number, Arithmetic

Operations, andCharacters


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Signed Integer

3 major representations:

Sign and magnitude

Ones complement

Twos complement

In all three systems, the leftmost bit is 0 for positive and 1 for

negative

Positive numbers have identical representations in allsystems, but negative values have different representations


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Signed Integer

Assumptions:

4-bit machine word

16 different values can be represented

Roughly half are positive, half are negative


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Sign and Magnitude Representation

0000

0111

0011

1011

1111

1110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0

+1

+2

+3

+4

+5

+6

+7-0

-1

-2

-3

-4

-5

-6

-7

0 100 = + 4

1 100 = - 4

+

-

High order bit is sign: 0 = positive (or zero), 1 = negativeThree low order bits is the magnitude: 0 (000) thru 7 (111)Range = -(2n-1 )-1 to +2n-1 -1

Two representations for 0

Ones Complement Representation


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One s Complement Representation

In 1s complement -ve value is obtained by complementing each bit of the

corresponding +ve value The operation of forming 1s complementing is equivalent to subtracting that no. from

2n -1

Still two representations of 0! This causes some problems

0000

0111

0011

1011

1111

1110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0

+1

+2

+3

+4

+5

+6

+7-7

-6

-5

-4

-3

-2

-1

-0

0 100 = + 4

1 01 1 = - 4

+

-

Twos Complement Representation


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Two s Complement Representation

The operation of forming 2s complementing is equivalent to subtracting that no. from

2

n

2s complement of a no. can be obtained by adding 1 to the 1s complement of that no.

Only one representation for 0

One more negative number than positive number

0000

0111

0011

1011

1111

1110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0

+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1

0 100 = + 4

1 100 = - 4

+

-

l ike 1's compexcept shif tedone pos i t ionc lockwise

Binary Signed Integer


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Binary, Signed-Integer

Representations

0

0

0

00

0

0

0

1

1

11

1

1

1

1

0

0

0

0

0

0

00

1

1

1

1

1

1

1

1

1

1

0

01

1

0

0

0

0

11

0

0

1

1

1

0

1

01

0

1

0

0

1

01

0

1

0

1

1+

1-

2+

3+4+

5+

6+

7+

2-3-

4-

5-

6-

7-

8-

0+

0-

1+

2+

3+4+

5+

6+

7+

0+

7-

6-

5-4-

3-

2-

1-

0-

1+

2+

3+4+

5+

6+

7+

0+

7-

6-5-

4-

3-

2-

1-

b3b2b1b0Sign and

magnitude 1's complement 2's complement

B Values represented

Figure 2.1. Binary, signed-integer representations.

SUMMARY OF THE TABLE


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SUMMARY OF THE TABLE

SIGN & MAGNITUE SYSTEM: Negative value is obtained by

changing the sign bit (MSB)Range: -(2n-1 ) -1 to +2n-1 -1

SIGNED 1S COMPLEMENT: Negative number is obtained by

complementing each bit of the corresponding positive number i.e

(2n-1)N

Range: -(2n-1 ) -1 to +2n-1 -1

SIGNED 2S COMPLEMENT: Negative number is obtained by taking2s complement of positive number i.e 2n-N

Range: - (2n-1) to + (2n-1-1)


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Addition of positive numbers

1 1

+1 +0

------ -------

10 1

------ --------


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Addition using 2s Complement

0111

+ 1101

---------

0100

--------

The carry out should be ignored

1


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Example of addition of n bit signed numbers using


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+2 0010 +4 0100

+3 + 0011 -6 + 1010

---- ---------- ----- ---------

+5 0101 -2 1110

----- --------- ----- ----------

-4 1100 -6 1010

-3 + 1101 +3 + 0011--- -------- ---- --------

-7 1001 -3 1101

--- ---------- ---- ---------

2s complement representation

1

Example of subtraction of n - bit signed numbers using 2s


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Example of subtraction of n bit signed numbers using 2 s

complement representation

+4 0100 0100

- +3 - 0011 + 1101------------ -------- -------

+1 0001

------------ ---------

+5 0101 0101

- -2 - 1110 + 0010

------- --------- --------

+7 0111

-------- ---------

1

Example of subtraction of nbit signed numbers using 2s


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complement representation

-3 1101 1101

- -6 - 1010 + 0110------------ -------- -------

+3 0011

------------ ---------

-4 1100 1100

- +2 - 0010 + 1110------- --------- --------

-6 1010

-------- ---------

1

1

1

Example of addition and subtraction of n bit signed numbers


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Example of addition and subtraction of n bit signed numbers

using 2s complement representation leading to overflow

+3 0011 0011

- -6 - 1010 + 0110

------------ -------- -------

+9 1001 -7

------------ ---------

-4 1100

+ -5 + 1011

------- --------

-9 1 0111 +7

-------- ---------


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Memory Locations,

Addresses, andOperations


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MEMORY ADDRESSINGMemory consists of millions of storage cells eachcapable of storing a bit of information

Memory organized in a way such that a group of n

bits can be stored or retrieved in a single basicoperation

n is the word length

k-bit address computer generates an address spaceof 2k locations

24-bit address computer generates an address space of 224

locations i.e 16777216 locations

Memory Location Addresses and


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Memory Location, Addresses, and

Operation

It is impractical to assign distinct addresses toindividual bit locations in the memory.

The most practical assignment is to have

successive addresses refer to successive bytelocations in the memory byte-addressablememory.

Byte locations have addresses 0, 1, 2, Ifword length is 32 bits, they successive wordsare located at addresses 0, 4, 8,

MEMORY ADDRESSING


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MEMORY ADDRESSING

BYTE ADDRESSABILITY

MEMORY ASSIGNMENT

LITTLE ENDIAN BIG ENDIAN

There are two ways of assigning byte addresses

across words

Big-Endian and Little-Endian Assignments


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Big Endian and Little Endian Assignments

2k

4- 2k

3- 2k

2- 2k

1- 2k

4-2k

4-

0 1 2 3

4 5 6 7

00

4

2k

1- 2k

2- 2k

3- 2k

4-

3 2 1 0

7 6 5 4

Byte addressByte address

(a) Big-endian assignment (b) Little-endian assignment

4

Word

address

Figure 2.7. Byte and word addressing.

Big-Endian: lower byte addresses are used for the most significant bytes of

the word Eg: INTEL 8085, INTEL 8086 Processor uses this scheme

Little-Endian: opposite ordering. lower byte addresses are used for the less

significant bytes of the word Eg: Motorola and Power PC Processors


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MEMORY OPERATION

LOAD (READ OR FETCH) STORE (WRITE)

LOAD(READ OR FETCH )


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LOAD(READ OR FETCH )

Transfers a copy of the contents of a specific

memory location to the processor

Processor sends address of the desiredlocation to memory and requests that its

contents be read(Issues read signal)

Memory reads the data and sends it to theprocessor

Memory contents remains unchanged


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STORE OR WRITETransfers an item of info from the cpu to a specific

memory location, destroying the former contents of

that locationProcessor sends the address of the desired location

to the memory, together with the data to be written

Issues write signal

Sends the data via data bus and write into the

selected particular memory location


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Instruction and

Instruction Sequencing

INSTRUCTIONS AND INSTRUCTION


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INSTRUCTIONS AND INSTRUCTION

SEQUENCING

A computer must have instructions capable of

performing following 4 types of operation

Data transfers between the memory and the

processor registers

Arithmetic and logic operations on data

Program sequencing and control

I/O transfers


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Contents of a location are denoted by placing squarebrackets around the name of the location

ex:R1[LOC], R3 [R1]+[R2]

RHS of RTN always denotes a values, and is called Source

LHS of RTN always denotes a symbolic name where value is

to be stored and is called destination

Source contents are not modified

Destination contents are overwritten


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Examples of RTN statements

1. R2 [LOCN]

2. R4 [R3] +[R2]

A bl L N t ti


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Assembly Language Notation

Another type of notation is required torepresent machine instructions and programs.

Move LOC, R1

i.e R1*LOC+

Add R1, R2, R3

i.e R3 *R1+*R2+

TYPES OF INSTRUCTION


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Assume an addition operation

C=A+B


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TYPES OF INSTRUCTION

Three address instruction

Syntax: Operation source 1, source 2, destination

Eg: ADD A,B,C where A,B,C are memory location

Advantage: Single instruction can perform the complete

operation

Disadvantage : Instruction code will be too large to fit in one

word location in memory

TWO ADDRESS INSTRUCTION


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TWO ADDRESS INSTRUCTION

Syntax : Operation source, destination

Eg: Add A,B

i.e B[A]+[B]

Prev instructions can be performed as

MOVE B,C

Add A,C

Disadvantage: Single instruction is not sufficient toperform the entire operation.

Will not normally fit into one word

ONE ADDRESS INSTRUCTION


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ONE ADDRESS INSTRUCTION

Syntax- Operation source/destination

In this type either a source or destination operand

is mentioned in the instruction

Other operand is implied to be a processorregister calledAccumulator

Eg: ADD D

Prev instrn can be performed as1. Load A; ACC [memlocation _A]

2. ADD B; ACC (ACC) +(B)

3. STORE C; memlocation_ C (ACC )


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If processor supports ALU operations only with registersthen the task C=A+B can be performed by the instruction

sequence

Move A, Ri

Move B, Rj

Add Ri, Rj

Move Rj, C


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If processor supports ALU operations where one data may be in

memory and other in register then the instruction sequence is for

ADD A,B,C :

MOVE A, Ri

ADD B, Ri

MOVE Ri,C

Instruction Execution and Straight-


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g

Line Sequencing

R0,C

B,R0

A,R0

Movei+ 8

Begin execution here Movei

ContentsAddress

C

B

A

the programData for

segmentprogram3-instruction

Addi+ 4

Figure 2.8. A program for C [A] + [B].

Assumptions:

- One memory operand

per instruction

- 32-bit word length

- Memory is byte

addressable- Full memory address

can be directly specified

in a single-word instruction

Two-phase procedure-Instruction fetch

-Instruction execute


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PC Program counter: hold the address of the next

instruction to be executed

Straight line sequencing: If fetching and executing of

instructions is carried out one by one from successive

addresses of memory, it is called straight line sequencing.

Major two phase of instruction execution

Instruction fetch phase: Instruction is fetched form

memory and is placed in instruction register IR

Instruction execute phase: Contents of IR is decoded andprocessor carries out the operation either by reading data

from memory or registers.

Branching NUM1,R0Movei


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NUMn

NUM2

NUM1

R0,SUM

NUMn,R0

NUM3,R0

NUM2,R0

Figure 2.9. A straight-line program for adding n numbers.

Add

Add

SUM

Move

Add

i 4n+

i 4n 4-+

i 8+

i 4+

BranchingN,R1Move

R0Clear


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Branching

NUMn

NUM2

NUM1

R0,SUM

R1

"Next" number to R0

Figure 2.10. Using a loop to add n numbers.

LOOP

Decrement

Move

LOOP

loop

Program

Determine address of"Next" number and add

N

SUM

n

R0Clear

Branch>0

Branch target

Conditional branch


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Branch instruction are those which changes the normal

sequence of execution.

Sequence can be changed either conditionally or

unconditionally.

Accordingly we have conditional branch instructions and

unconditional branch instruction.

conditional branch instruction changes the sequence onlywhen certain conditions are met.

Unconditional branch instruction changes the sequence of

execution irrespective of condition of the results.


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CONDITION CODES

Results of various instructions are stored for subsequent

use by conditional instructions

This is done by recording the required info in individual bits,

called as condition code flags grouped together in special

processor register called as condition code register or status

register


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CONDITIONAL CODE FLAGS:

N Negative 1 if results are Negative

0 if results are Positive

Z Zero 1 if results are Zero0 if results are Non zero

V Overflow 1 if arithmetic overflow occurs

0 no overflow occurs

C Carry 1 if carry and from MSB bit0 if there is no carry from MSB bit


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Addressing Modes

Generating Memory Addresses


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g y

Situations like program looping, branching demand convenient

ways of locating memory words or memory operands.

This convenience is being offered by different instructions (of a

particular instruction set as defined by the Microprocessor) viavarious Addressing Modes they support.

Suppose a given memory operand address is too large to fit

into a given instruction format (i.e., in operand field), then it is

the addressing mode (say Register Indirect Mode ) that can

resolve this problem.

What is Addressing Mode . . . ?


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g

The different ways in which the location of an operand is

specified in an instruction are referred to as addressing modes

Add i M d


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Addressing Modes:

Immediate mode

Absolute (Direct) mode

Register mode

Indirect mode

Indexed mode

Relative mode

Auto increment mode

Auto decrement mode


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Here the operand is specified in the instruction itself. Aninstruction that follows immediate mode has an operand field

rather than an address field.

For example:

Move50immediate, R0

A common convention say, a pound symbol # has to

precede the value of an immediate operand

Move#50, R0

Immediate Addressing mode

50

R2

R1

R0


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Here operand resides in Memory and its address is given

explicitly in the address field of an instruction. This scheme

need only one memory reference in addition to instruction

fetch cycle and no further calculation is required to compute

operand address.

Direct Addressing Mode /Absolute Mode


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Register Addressing Mode

In this scheme, the operand is the contents of a registerappearing in the instruction

example

Add R1,R2


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Advantages of this scheme :No memory reference

A few bit address to indicate register location

Speedy execution since register is inside the processor

& has low access time.

Disadvantages of this scheme :

Limited address space as number of registers are less

in many of the processors.

Register Addressing Mode


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Indirect Addressing Mode


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Here, instruction specifies a register in the CPU whose

contents give the effective address of the operand in Memory.

For example Add (R1), R0 i.e. EA = (R1) i.e. contents ofR1 is B

Register Indirect Addressing Mode


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Address Contents

Move N, R1

Move #NUM, R2

Clear R0LOOP Add (R2), R0

Add #4, R2

Decrement R1

Branch > 0 LOOPMove R0, SUM


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The advantage of Register Indirect Addressing:

It uses one less memory reference (memory read operation)

Address field of the instruction uses a fewer bits to

specify a register

Register indirect addressing can be specified with

Effective Address EA = (R) i.e. B

Advantages of Indirect addressing:

a wider address range to refer to a large number of

memory locations.

Disadvantage of Indirect addressing:2 or more memory references (memory read operations)

required to fetch the desired operand in memory.


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Indexed Addressing Mode

Example: Add 20(R1),R2

Add 2000(R3),R4

Assume that a list of scores of the student beginning at

location LIST as shown in the following diagram

A 4 word memory comprises a record that stores relevant info

for each student

Compute the sum of all scores obtained on each of the test

and store these sums in memory locations

SUM1,SUM2,SUM3



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N 5000

LIST 5004

LIST+4 5008

LIST+8 5012LIST+12 5016

LIST+16 5020

nStudent ID

Test1

Test2Test3

Student ID

Test1Test2

Test3

.

Move #LIST, R0

Clear R1


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Clear R1

Clear R2

Clear R3Move N, R4

LOOP Add 4(R0), R1

Add 8(R0), R2

Add 12(R0), R3Add #16, R0

Decrement R4

Branch>0 LOOP

Move R1, SUM1

Move R2, SUM2

Move R3, SUM3


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Advantages of Index mode

is the flexibility it offers to access relative memory locations

Disadvantagesof Index mode

* Is the complexity of computing effective address.

* The instruction requires to have two address fields

at least one of which is an explicit number.


Variations of Indexed AddressingM d


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Mode

several variations of this basic form provide a veryefficient access to memory operands in practicalprogramming situations.

For example, a second register may be used to containthe offset X, in which case we can write the Index mode as

(Ri, Rj) The effective address is the sum of the contents of

registers Ri and Rj.

The second register is usually called the base register.

This form of indexed addressing provides more flexibility in

accessing operands, because both components of theeffective address can be changed.


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Another version of the Index mode uses tworegisters plus a constant, which can be denoted as

X(Ri, Rj)

In this case, the effective address is the sum of

the constant X and the contents of registers Ri andRj.

This added flexibility is useful in accessing multiplecomponents inside each item in a record, where thebeginning of an item is specified by the (Ri, Rj) partof the addressing mode.

Relative Addressing Mode


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This scheme supplies the relative position of the memory

operand to be located.Its like index mode only but program counter register PC

substitutes for base address contents

Commonly used to specify the target address in branch

instruction

Relative Mode specify Effective Address by a notation:

X(PC)

Effective address is EA = [ PC ] + X

Branch > 0 loop Here jump value / displacement X


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The EA of the operand is the contents of a register specifiedin the instruction

After accessing the operand, the contents of this register are

incremented automatically to point to the next operand

in contiguous memory locations.

Notation for Auto Increment Mode: (Ri) +

For example: Add(R2) +, R0

Use of Auto Increment mode instruction eliminates the use ofexplicit increment instruction

Auto Increment Mode


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Assembly Language Here, symbolic codes are used to represent binary pattern of

machine instructions. These symbolic codes are called as

mnemonics.

Mnemonicsare abbreviations that represent operation code

of an instruction in a compact and meaningful symbolic form.

For instance mnemonics for few operation codes include:INC / INR - Increment

ADDI - To add immediate operand

ADD - To add

LOAD - To load operand from memorySTORE - To store operand to memory

MOVE - To transfer data from one location to

another location/Register.


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A complete set of such mnemonics, symbolic names for

register & memory locations and a list of rules for their use

forms a programming language called anAssembly Language.

The basic unit of assembly language program is a line of

code.

Here every line of code has symbolic code called mnemonicopcode and symbolic name to represent address of memory

location / register as the operand field.

The translator program is called an Assembler.

Assembly Language

A bl L t


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For example, assembly language syntax suggests that amove instruction to appear as follows:

MOVE R0, SUM

The opcode mnemonic MOVE is followed by at least one

blank space.

The source operand is in register R0 (register operand).

The destination operand is in the memory location SUM

For instance symbolic name of operand memory locationSUM suggest absolute mode ordirect addressing mode

is used in the instruction.

Assembly Language syntax

A bl L t


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Pound sign # usually denotes an immediate operandin the

instruction using Immediate Addressing mode

For example: ADD #10, R2 or ADDI 10, R2

MOVE #20, R3

Indirect addressing is usually specified by placing

parentheses around the name or symbol For example ADD (A), R0

Assembly Language syntax

Format of Assembly Language Statements

A bl Di i


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Assembler Directives are the assembler commands to the

assembler concerning the program being assembled. These

commands are neither translated into machine opcode nor

assigned any memory location in the object program.

Thus an assembly language program is said to be a complete

one and acceptable to an assembler for translation and forfurther assignment of memory locations if it is associated with

necessary assembler directives.

Examples of Assembler Directives:

S EQU 150The assembler command EQU directs the assembler

during translation that the symbolic name S must be replaced

by value 150,

Assembler Directives

Memory arrangement for the program


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100 Move N, R1104 Move #NUM1,R2

108 Clear R0

112 Add (R2), R0116 Add #4, R2

120 Decrement R1

124 Branch>0 LOOP128 Move R0, SUM



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SUM 200N 204

NUM1 208

NUM2 212

NUMn 604

100

.

.

.

AL representation for the program


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p p g

SUM EQU 200ORIGIN 204

N DATAWORD 100

NUM1 RESERVE 400

ORIGIN 100

START MOVE N,R1

MOVE #NUM1,R2

CLR R0

LOOP ADD (R2),R0

ADD #4,R2

DEC R1

BGTZ LOOPMOVE R0,SUM

RETURN

END START


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ORIGIN 204Instruct assembler to place data block at main memory

locations starting from 204

N DATAWORD 100

Inform the assembler that value of N i.e. data value 100

is to be placed in the memory location 204.

ORIGIN 100

The second ORIGIN directive states that assembler

directive must load machine instructions of the object program

in the main memory starting from location 100.

Assembler Directives


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NUM1 RESERVE 400

This directive declares that a memory block of

400 bytes is to be reserved for data, and thatthe name NUM1 is to be associated with

address 208


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RETURN This is an assembler directive that identifies

the point at which execution of the program

should be terminated. It causes the assemblerto insert an appropriate machine instruction

that returns control to the operating system of

the computer.


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END START

The last statement in the source program is

the assembler directive END, which tells the

assembler that this is the end of the sourceprogram text. The END directive includes the

label START, which is the address of the

location at which execution of the program isto begin.

ASSEMBLY AND EXECUTION OF

PRGRAMS


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PRGRAMS

A source program written in an assemblylanguage must be assembled into a machinelanguage object program before it can beexecuted - performed by assembler

As the assembler scans through a sourceprograms, it keeps track of all names and thenumerical values that correspond to them in a

symbol table


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When a name appears a second time, it is replaced with itsvalue from the table

A problem arises when a name appears as an operand beforeit is given a value. For example, this happens if a forwardbranch is required

A simple solution to this problem is to have the assemblerscan through the source program twice

During the first pass, it creates a complete symbol table. Atthe end of this pass, all names will have been assignednumerical values

The assembler then goes through the source program asecond time and substitutes values for all names from thesymbol table. Such an assembler is called a two-passassembler.


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The assembler stores the object program on amagnetic disk

The object program must be loaded into the

memory of the computer before it is executed. This task is performed by an utility program

called a loader

NUMBER NOTATION


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ADD #93, R1or

ADD #%01011101, R1

or

ADD #$5D, R1

Basic Input/Output Operations


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Basic Input/Output OperationsMechanism of I/O transfer

between processor and keyboard & video monitor:

A character key when pressed from the keyboard its scan

code is sent to an 8-bit buffer registerDATAIN in the keyboard.

Processor is informed about a valid character data presence

in DATAIN register by setting a synchronization flag SIN to 1.

I/O driver program continuously monitors contents of SIN

flag, & when SIN is set to 1, it reads the contents ofDATAIN.

Thus character stored in DATAIN register is transferred toprocessor over a system bus and SIN content is automatically

reset to 0.

M h i f I/O t f


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Mechanism of I/O transfer

between Processor and Keyboard & Video monitor


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A similar set of events take place while transferring a

character data from processor to the display screen. Here a DATAOUT register that holds a characters code to bedisplayed when synchronization control flag SOUT is set to 1.When SOUT equals 1, the display device is ready to receive a

character from processor. The transfer of a character to DATAOUT resets SOUT to 0. I/O driver program instructions control the status of SOUTflag.

The buffer registers DATAIN, DATAOUT, and control flags SIN,SOUT in this hardware setup forms parts of a connectivitycircuits commonly known as device in terfaceor interfacehardware.


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I/O driver program instructions for I/O data transfer

WRITEWAIT Branch to WRITEWAIT if SOUT = 0

Output from R0 to DATAOUT (if SOUT = 1)

SOUT is set to 1 when display terminal is free to display next

character. The wait loop is executed repeatedly until the control flag

SOUT is set to 1 by the display terminal.

Initial state of SIN is 0 and SOUT is 1


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Memory mapped i/o some memory addresses refer toperipheral device buffer registers, such as DATAIN,DATAOUT

Data can be transferred b/w the cpu and these registers usingsame set of instructions and same status flags

Ex: MoveByte DATAIN,R0

MoveByte R0,DATAOUT

Status flags SIN and SOUT can be included device statusregister

Assume that the bit b3 of the status registers

INSTATUS,OUTSTATUS corresponds to SIN and SOUT


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Then read and write operation can be implemented as:READWAIT TestBit #3,INSTATUS

Branch=0 READWAIT

MoveByte DATAIN,R0

WRITEWAIT TestBit #3,OUTSTATUSBranch=0 WRITEWAIT

MoveByte R0,DATAOUT

Program to read a line of chars and to display it


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Move #LOC,R0

READ TestBit #3,INSTATUS

Branch=0 READ

MoveByte DATAIN,(R0)

ECHO TestBit #3,OUTSTATUS

Branch=0 ECHO

MoveByte (R0),DATAOUT

Compare #CR,(R0)+

branch!=0 READ


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Stack is used in order to organize the control and info linkage

b t th d th b ti

Stacks

Last In First Out List


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between the program and the subroutine

Stack refers to storage area in which a group of data items

can be stored at consecutive memory locations with the

accessing restriction that data elements can be added / stored

or removed / deleted at only one end of the list called top of

stack. This kind of list structure is called Pushdown stack.

A special register called Stack Po inter (SP)always points to

the address of top element of the stack.

The two operations that can be performed on a stack areInsertion (PUSH) and Deletion (POP) of data items.

Assume that the stack grows in the decreasing memory

address


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.

.

12

-98.

.

55

.

.

SP->

BOTTOM

2k-1

Stack Operations: PUSH and POP


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Suppose, we would like to insert a new element say 356 onto a stack, then PUSH operation to insert 356 can be

performed using the instructions:

Subtract #4,SP ; SP points to location 104

MOVE NEWITEM, (SP) ; Transfer356 from location

NEWITEM to location 104

Pointed to by SP contents

Now let us remove an element from stack. The POP

operation to delete an element from top of stack can be

performed using the instructions:MOVE (SP), ITEM ; Transfer 356 to location ITEM

Add #4,SP ; SP now points to location 108

Stack Operations: PUSH and POP


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If the processor has the autoincr and autodecr addressingmodes, then push and pop operation can be performed by

single operations:

Move NEWITEM,-(SP)

Move (SP)+,ITEM


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To prevent either the pushing an item on a full stack orpopping an item off an empty stack, the single push and pop

operation can be replaced by the following instructions:

SAFEPOP Compare #2000,SP

Branch>0 EMPTYERRORMove (SP)+,ITEM

SAFEPUSH Compare #1500,SP

Branch


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Data elements are inserted in memory at the increasing

Queue First In First Out List


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order of memory addresses i.e., at the back of Queue.

Data elements are retrieved from memory at the decreasingorder of memory addresses i.e. from the front end of Queue.

Operations such as QINSERT and QDELETE can be performed

on a queue to insert and delete & element respectively.

Queue could grow continuously in the direction of higher

memory addresses

Circular buffer can be used to limit the queue to a fixed region

in memory

A Queue consisting of 6 elements may appear as follows:

Stack Queue

Stack Vs. Queue


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Stack is a LIFO list

One end of the stack is fixed (the bottom),

while the other end rises and falls as data are

pushed and popped.

Needs only one pointer register SP

Insertions & Deletions are made from

only one end i.e., Top of stack

Stack operations are PUSH & POP

Queue is a FIFO list

Both ends of a queue move to higher

addresses as data are added at the back and

removed from the front

Needs two pointer registers QF & QE

Insertion from back end and Deletion

from front end of a Queue

Queue operations are QINSERT &

QDELETE

Subroutines


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A subroutine is a self

contained sub-program designedto be used by other larger programs or main programs.

A task which is required to be carried out frequently, is

usually implemented as a subroutine.

Subroutine mechanisms make use of two kinds ofbranch

instructions:

First, a call instruction that branches from the present

location in calling program or main program to the location

in main memory at which subroutine begins.

Second, a return instruction that returns from thesubroutine to the location in calling program or main

program from which it was called.

Subroutines


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The common places for storing the return addresses:

Link register

Call-is a special branch instruction which performs the

following sequence of operations:

1. Copy the contents of PC (i.e. address of next instruction insequence following a call instruction in a main program) to

link register

2. Transfer control to the beginning of subroutine (the

starting address of subroutine is specified in the Call

instruction itself)

Return is a special branch instruction which performs :Transfer control to the return address contained in link register.


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The way in which a computer makes it possible to call and return

from subroutines is referred to as its subroutine linkage method.

Subroutines Nesting & Processor Stack


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In case of nesting of subroutines a main program calls a

subroutine, and called subroutine can make a call to anothersubroutine inturn. This continues likewise, to extend nesting

of subroutine to any number of levels.

Here successive return addresses must be stored safely to

allow processor to resume program execution at differentplaces from which subroutine calls have been made.

Return addresses hence generated are to be stored and

used in a Last-inFirst out order.

This kind of return address behavior associated with

subroutine call and return suggest that all such returnaddresses must be pushed down to a stack called a processor

stack rather than using a Link register.

g


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These return addresses are popped up inturn in a manner

that suites subroutines return address behaviour for resuming

calling program execution.

For example : Execution of main program (MAIN)

take place in the following sequence of program segments:

Nested Subroutine Call & Return


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Parameter Passing


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When a program calls a subroutine, it must supply thenecessary operands or data to be operated upon by theinstructions ofcalled subroutine.

These operands are referred to as parameters orarguments.

There are many ways of parameter passing such as pass byvalue, pass by reference etc.

Parameters can be placed in register, memory location orprocessor stack from where they can be accessed bysubroutine

g

Passing parameters through registers


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Straight forward and efficient Only few parameters can be passed as the no.

registers are limited

Example


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Move N,R1Move #NUM1,R2

Call LISTADD

Move R0,SUM

LISTADD Clear R0

LOOP Add (R2)+,R0

Decrement R1

Branch>0 LOOPReturn

Passing parameters using stack


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If many parameters are involved, there notmay be enough registers available for passing

them to subroutine

A stack can be used in such situations

Example


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Move #NUM1,-(SP)Move N,-(SP)

Call LISTADD

Move 4(SP),SUM

Add #8,SP


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LISTADD MoveMultiple R0-R2,-(SP)Move 16(SP),R1

Move 20(SP),R2

Clear R0

LOOP Add (R2)+,R0Decrement R1

Branch>0 LOOP

Move R0,20(SP)

MoveMultiple (SP)+,R0-R2Return

T f t k


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Top of stack

level 3

level 2

level 1

[R2]

[R1]

[R0]

Return Address

N

NUM1

Stack Frame The consecutive location on stack that hold list of

parameter including local variables and return addressb ll &


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pertaining to a subroutine call & return, constitute a

private work space called stack frameof the subroutine. The stack frame locations get filled as and when each

subroutine is called for execution. Also, stack framespace is vacated soon after the completion of executionof subroutine

it is useful to have another pointer register, called theframe pointer (FP), for convenient access to theparameters passed to the subroutine and to the localmemory variables used by the subroutine

The pointers SP and FP are manipulated as the stackframe is built, used, and dismantled for a particular ofthe subroutine.


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Assume that SP point to the old top-of-stack (TOS)element

Assume that four parameters are passed to the

subroutine, three local variables are used within the

subroutine, and registers R0 and R1 need to be savedbecause they will also be used within the subroutine.

Before the subroutine is called, the calling programpushes the four parameters onto the stack

The call instruction is then executed, resulting in thereturn address being pushed onto the stack.


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Now, SP points to this return address, and the firstinstruction of the subroutine is about to be executed.

This is the point at which the frame pointer FP is setto contain the proper memory address.

Since FP is usually a general-purpose register, it maycontain information of use to the Calling program.Therefore, its contents are saved by pushing themonto the stack

Since the SP now points to this position, its contents

are copied into FP


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Thus, the first two instructions executed in the subroutine are

Move FP, -(SP)

Move SP, FP

After these instructions are executed, both SP and FP point tothe saved FP contents

Space for the three local variables is now allocated on thestack by executing the instruction

Subtract #12, SP

Finally, the contents of processor registers R0 and R1 are

saved by pushing them onto the stack. At this point, the stackframe has been set up as shown in the fig.

Saved [R1]

Saved [R0]

SP


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Saved [R0]

Localvar3Localvar2

Localvar1

Saved [FP]Return address

Param1

Param2Param3

Param4

FP

Old TOS


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The subroutine now executes its task. When the taskis completed, the subroutine pops the saved valuesof R1 and R0 back into those registers, removes thelocal variables from the stack frame by executing theinstruction.

Add #12, SP

And pops the saved old value of FP back into FP.At this point, SP points to the return address, so the

Return instruction can be executed, transferringcontrol back to the calling program.


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Calling program is responsible for removingthe parameters from the stack frame, some

which may be the results passed back by the

subroutine The SP now points to the old TOS

Stack frames for nested subroutines


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An example of a main program calling a firstsubroutine SUB1, which then calls a second

subroutine SUB2.

The stack frames corresponding to these twonested subroutines are shown in the following

diagram

All parameters involved in this example arepassed on the stack.

The flow of execution is as follows.

The main program pushes the two parameters


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The main program pushes the two parameters

param2 and param1 onto the stack in that orderand then calls SUB1.

This first subroutine is responsible for

computing a single answer and passing it backto the main program on the stack.

During the course of its computations, SUB1

calls the second subroutine, SUB2, in order to

perform some subtask.

SUB1 passes a single parameter param3 to SUB2

and gets a result passed back to it.


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After SUB2 executes its Return instruction, thisresult is stored in register R2 by SUB1.

SUB1 then continues its computations and

eventually passes the required answer back tothe main program on the stack.

When SUB1 executes its return to the main

program, the main program stores this answer inmemory location RESULT and continues with its

computations at next instruction.


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flow of execution The first actions performed by each subroutine

are to set the frame pointer, after saving its

previous contents on the stack, and to save anyother registers required.

SUB1 uses four registers, R0 to R3, and SUB2

uses two registers, R0 and R1. These registers and the frame pointer are

restored just before the returns are executed.

The Index addressing mode involving the framepointer register FP is used to load parameters

from the stack and place answers back on the


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from the stack and place answers back on the

stack. The byte offsets used in these operations are

always 8, 12, . . . , as discussed for the general

stack frame Finally, note that the calling routines are

responsible for removing parameters from the

stack. This is done by the Add instruction in the main

program, and by the Move instruction at location

2164 i SUB1


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LOGIC INSTRUCTIONS


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Logic operations are applied to individual bits,are the basic building blocks of digital circuits

AND

OR NOT

Not dst

SHIFT AND ROTATE INSTRUCTIONS


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There are many applications that require the bits ofan operand to be shifted right or left some specifiednumber of bit positions.

The details of how the shifts are performed depend

on whether the operand is a signed number or somemore general binary-coded information.

For general operands, a logical shift is used

For a number, an arithmetic shift is used, which

preserves the sign of the number.

Logical shifts


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Two logical shift instructions shifting left (LShiftL)

shifting right (LShiftR)

These instructions shift an operand over anumber of bit positions specified in a countoperand contained in the instruction.

The general form of a logical left shiftinstruction is

LShiftL count, dst


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Logical shift leftLShiftL #2, R0

0

Before:

After:

C R0

0 0 1 1 1 0 . . . 0 1 1

1 1 1 0 . . . 0 1 1 0 0


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Logical shift rightLShiftR #2, R0

0 C

Before:

After:

R0

00 1 1 1 0 . . . 0 1 1

10 0 0 1 1 1 0 . . . 0

Digit-Packing Example


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Suppose that two decimal digits representedin ASCII code are located in memory at byte

locations LOC and LOC + 1.

Each of these digits should be represented inthe 4-bit BCD code and store both of them in a

single byte location PACKED. This result is said

to be inpacked-BCD format.

The rightmost four bits of the ASCII code for a

decimal digit correspond to the BCD code for

the digit.


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Hence, the required task is to extract the low-order four bits in LOC and LOC + 1 and

concatenate them into the single byte at

PACKED.

The instruction sequence accomplishes the

task using register R0 as a pointer to the ASCII

characters in memory, and using registers R1

and R2 to develop the BCD digit codes.


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When a MoveByte instruction transfers a bytebetween memory and a 32-bit processor

register, the byte is located in the rightmost

eight bit positions of the register.

The And instruction is used to mask out all but

the four rightmost bits in R2.


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Arithmetic shifts


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Arithmetic shift rightAShiftR #2, R0

C

Before:

After:

R0

01 0 0 1 1 . . . 0 1 0

11 1 1 0 0 1 1 . . . 0

Rotate Operations


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In the shift operations, the bits shifted out of theoperand are lost, except for the last bit shifted outwhich is retained in the Carry flag C.

To preserve all bits, a set of rotate instructions can be

used. They move the bits that are shifted out of oneend of the operand back into the other end

Two versions of both the left and right rotateinstructions are usually provided. In one version, the

bits of the operand are simply rotated. In the otherversion, the rotation includes the C flag.

Rotate left without carry


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RotateL #2, R0

Before:

After:

C R0

0 0 1 1 1 0 . . . 0 1 1

1 1 1 0 . . . 0 1 1 0 1

Rotate left with carry


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RotateLC #2, R0

Before:

After:

C R0

0 0 1 1 1 0 . . . 0 1 1

1 1 1 0 . . . 0 1 1 0 0


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Rotate right without carry

RotateR #2, R0

Before:

After:

00 1 1 1 0 . . . 0 1 1

11 1 0 1 1 1 0 . . . 0

R0C


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Rotate right with carry

RotateRC #2, R0

Before:

After:

00 1 1 1 0 . . . 0 1 1

11 0 0 1 1 1 0 . . . 0

R0C

Multiplication & Division


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Some of the processors instruction sets supports Multiply

and Divide operations. For which they offer direct instructions

to multiply and/or divide on processor register operands.

For instance

MULTIPLY Ri, Rj ;Rj [Ri] * [Rj]

DIVIDE Ri, Rj ;Rj [Rj] / [Ri]

Encoding of Machine Instructions


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An instruction in Machine language is encoded as sequence

of binary digits pattern in a precise and compact form.

Machine instructions can be encoded as 8-bit byte, 16-bit

half word or 32-bit word. This encoding of machine instruction also depends on word-

length of the machine and has considerable influence on

instructions types


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8 7 7 10

one-word instruction

two-word instruction

three-operand instruction

Opcode Source Dest Other info

Opcode Source Dest Other info

Memory address/Immediate operand

Op code Ri Rj Rk Other

info


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Two approaches: CISC &RISC

CISC: A computer or a processor with a large number of

instructions and incorporating variable length instruction

formats (i.e. using multiple words for instructions) is termed a

Complex Instruct ion Set Compu terabbreviated as CISC

Encoding of Machine InstructionsSalient feature of CISC architecture include:


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Support large number of instructions 100 to 250 Support wide variety of addressing modes 5 to 20

Comprises variable length instructionsProvide instructions for direct manipulation of operandsresiding in memory

Provide single complex instructions that resemble and /ortransform a complete statement execution in a high levellanguage programs.

Examples ofCISC architecture computers:DEC VAX computer, IBM 370 computer

Examples ofCISC processorsMotorola 68000, 68020, 68030, 68040 processorsIntel 80 x 86, 80386, 80486, Pentium processors

Salient feature of RISC architecture :

A t ith l ti l ll t f


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A computer or processor with relatively small set of

instruction and incorporating fixed length instruction

format most of them being a register to register

operations, is termed as Reduced Instruct ions Set

Computerabbreviated as RISC

Features of RISC architecture include: Support relatively few instructions and are less complex

Support few addressing modes

Comprises fixed length instructions that can be easily

decodedA restriction to perform all operations in processor

registers only.

RISC Architecture features:


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Memory is accessed with only Load and Storeinstructions

Ability to execute one instruction per clock cycle

Examples ofRISC processors

Power PC 601, 603, 604, 620

Alpha (AXP) processors,

DEC 21064 processor


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End of unit 2

computer organization, unit 1 & 2

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