Computer Organization and Architecture CS2253 PART-A UNIT I

1. What are the basic functional units of a computer?

Input, memory, arithmetic and logic unit, output and control units are the basic functional units of a computer

2. Define Response time and Throughput.

Response time is the time between the start and the completion of the event. Also referred to as execution time or latency. Throughput is the total amount of work done in a given amount of time.

3. Define a program?

A list of instructions that performs a task is called as a program

4.Define data.

Data are numbers and encoded characters that are used as operands by the instructions. The term data, however is often used to mean any digital information.

5.Give some examples for input devices.

Keyboard,joysticks,trackballs and mousse are some examples for input devices.

6.Compute the effective CPI for the processor, for the following instruction mix: Instruction type Clock cycle count Frequency ALU operation 1 40

Loads 3 20

Stores 2 10

Branch taken 3 20

Branch untaken 2 10

Adding a branch prediction unit makes an enhancement to the processor. This decreases the number of cycle taken to execute a branch from 3 to 2. What is the improvement in performance?

Speed up= execution time old

/ execution time new

execution time old

or CPU time= I.C. * Clk Cycles * Cycle time

execution time old =[40*1+20*3+10*2+20*2+10*2] Cycles * cycles time. The enhancement decreases the number of cycles taken for branch instruction from 3 to 2. execution time new =[40*1+20*3+10*2+20*2+10*2] Cycles * cycles time

= 180 Cycles * cycles time

\\ Speed up = 200 Cycles * cycles time / 180 Cycles * cycles time = 1.1

7. Suppose that we are considering an enhancement to the processor of a server system used for web serving. The new CPU is 10 times faster on computation in the web serving application than the original processor. Assuming that the original CPU is busy with computation 40% of the time and is waiting for I/O 60% of the time. What is the overall speedup gained by incorporating the enhancement?

Fraction enhanced = 0.4

Speedup enhanced = 10

Speedup overall = 1/(0.6+0.4/10) =1/0.64 = 1.56

8. Explain the different types of locality.

Temporal locality, states that recently accessed items are likely to be

accessed in the near future.Spatial locality, says that items whose addresses are near one another tend to be referenced close together in time.

9. What is the function of memory unit? how will you classify it?

The function of the memory unit is to store programs and data, there are two classes of storage, called primary and secondary.

10. Specify the CPU performance equation.

CPU time = Instruction Count x Clock cycle Time x cycles per instruction

11. Explain the hybrid approach for encoding an instruction set?

The hybrid approach reduces the variability in size and work of the

variable architecture but provide multiple instruction lengths to reduce code size.

12. What are the registers used for MIPS processors.

MIPS has 34, 64-bit general purpose registers (GPRs), named R0,

R1R31. GPRs are sometimes called as integer registers. There are also a set of 32 floating point registers (FPRs), named F0,F1.F31, which can hold 32 single precision values and 32 double precision values.

13. Explain the concept behind pipelining.

Pipelining is an implementation technique whereby multiple instructions

are overlapped in execution. It takes advantage of parallelism that exists among actions needed to execute an instruction.

14. Write about pipe stages and processor cycle.

Different steps in an instruction are completed in different parts of different instruction is parallel. Each of these steps is called a pipe stage or pipe segment. The time required between moving an instruction one step down the pipeline is called processor cycle.

15. Explain pipeline hazard and mention the different hazards in pipeline.

Hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the overall performance from the ideal speedup gained by pipelining. The three classes of hazards are,

Structural hazards.

Data hazards.

Control hazards

16. Explain the concept of forwarding.

Forwarding can be generalized to include passing a result directly to the

functional unit that fetches it. The result is forwarded from the pipeline register corresponding to the output of one unit to the input of the same unit.

17. Mention the different schemes to reduce pipeline branch penalties.

a. Freeze or flush the pipeline

b. Treat every branch as not taken

c. Treat every branch as taken

d. Delayed branch

18. what are timing signals?

Timing signals are signals that determines when a given action is to take place.the actual timing signals that govern the transfers are generated by control circuits.

19.how will you compute the SPEC rating?

SPEC stands for system performance evaluation corporation

Running time on the reference computer

SPEC rating=

_________________________________

Running time on the computer under test

20. When do data hazards arise?

Data hazards arise when an instruction depends on the results of a

previous instruction in a way that is expressed by the overlapping of instructions in the pipeline.

PART-B

1.Explain in Detail about the different functional units of a computer.

2.Explain the software performance of a computer.

3.what are the different types of instructions and also explain the instruction sequence.

4. Explain about the memory locations and addresses, memory operations.

5.Define addressing modes. And explain the different types of addressing

modes.

6.Write short notes on generation of computer and give its evaluation of performance

7. Write short notes on the basics of computer architecture?

8.i) Describe about stock organization.

ii) Discuss in detail about some addressing modes.

9.discuss in detail the instruction formats and its types.

10.i) describe stored program organization in detail.

ii) What are the instruction formats available and explain each?

11.Explain briefly about the stack organization. PART-A

1. what are the two approaches to reduce delay in address? To use fastest possible electronic technology in implementing the ripple-carry logic design or variations of it. To use an augmented logic gate network structure

2. What is Instruction Level Parallelism?

Pipelining is used to overlap the execution of instructions and improve

performance. This potential overlap among instructions is called

instruction level parallelism (ILP) since the instruction can be evaluated

in parallel.

3. what is the purpose of fast adder?

A fast adder circuit must speedup the generation of the carry signals.

4. What is the limitation of the simple pipelining technique?

These technique uses in-order instruction issue and execution. Instructions

are issued in program order, and if an instruction is stalled in the pipeline, no later instructions can proceed.

5. Briefly explain the idea behind using reservation station?

Reservation station fetches and buffers an operand as soon as available,

eliminating the need to get the operand from a register.

6. How does propagate function mean?

The propagate function means that an input carry will produce an output carry when either xi is 1 or yi is 1

7.what is booths algorithm?

Booths algorithm is a technique for generating a 2 nbit product. it treats both positive and negative 2s complement n bit operands uniformly..

8. what is bit pair recoding?

Bit pair recoding of multipliers is a technique that halves the maximum number of summands ,it is derived directly from booth algorithm.

on a different pipeline.

9.Give the expression for generate and propagate functions for stage i.

Generate function Gi=XiYi

Propagate function Pi=Xi+Yi

10. What are the techniques used to reduce the time needed to perform multiplication?

Bit pair recoding of multiplier

Carry save addition of summands

Look ahead addition.

11. What are branch-target buffers?

To reduce the branch penalty we need to know from what address to fetch by end of IF (instruction fetch). A branch prediction cache that stores the predicted address for the next instruction after a branch is called a branch-target buffer or branch target cache.

12. Briefly explain the goal of multiple-issue processor?

The goal of multiple issue processors is to allow multiple instructions to

issue in a clock cycle. They come in two flavors: superscalar processors and

VLIW processors.

13. What is speculation?

Speculation allows execution of instruction before control dependences

are resolved.

14. what is chopping?

Chopping is a simple way to truncate or remove the guard bits and make no changes in the retained bits.

15. What are super scalar processors?

Superscalar processors issue varying number of instructions per clock and are either statically scheduled or dynamically scheduled.

16. what is the process involved in von-Neumann rounding?

If the bits to be removed are all 0s they are simply dropped, with no changes to retained bits.however,if any of the bits to be removed are , the least significant bit of retained bit is set to 1.

17. Define a normalized number

A normalized number is one in which the most significant digit of the significant is zero.

18.Give the range of negative numbers in floating point format.

the range of negative numbers in floating point format

(2-2-23) x 2 128 and -2-127

19. Give the range of positive numbers in floating point format.

the range of positive numbers in floating point format

2-127 and (2-2-23) x 2128

20.List the conditions produced during a floating point operation.

during a floating point operation, the conditions produced are Exponent overflow Exponent underflow Significant underflow Significant overflow

PART-B

1.write short notes on fixed point and floating-point numbers of data representation? Explain the instruction and its types with examples?

2.Briefly discuss about fixed-point arithmetic and floating point.

3.Explain with a diagram, the design of a fast multiplier using carry save adder circuit.

4.show how a 64 bit adder can be constructed using 4-bit adder modules and

4-bit carry look ahead generator modules. what is the delay in generating

C64 and S63 here?

5.Discuss any one binary division algorithm and simulate the same for 25/15

6.give the organization of a floating-point adder / subtractor unit and explain its operation.

7.what is booths Algorithm? Explain in detail.

8.Expalin with a diagram, the design of fast adder.

9.Expalin in detail, the arithmetic operations performed on floating point numbers.

10.what are two types of integer division techniques? Explain with an example. UNIT III PART-A

1. What is loop unrolling?

A simple scheme for increasing the number of instructions relative to the

branch and overhead instructions is loop unrolling. Unrolling simply replicates the loop body multiple times, adjusting the loop termination code.

2. When static branch predictors are used?

They are used in processors where the expectation is that the branch

behavior is highly predictable at compile time. Static predictors are also used to assists dynamic predictor.

3. Mention the different methods to predict branch behavior?

Predict the branch as taken Predict on basis of branch direction (either forward or backward) Predict using profile information collected from earlier runs.

4. Explain the VLIW approach?

They uses multiple, independent functional units. Rather than attempting to

issue multiple, independent instructions to the units, a VLIW packages the

multiple operations into one very long instruction.

5. Mention the techniques to compact the code size in instructions?

Using encoding techniques Compress the instruction in main memory and expand them when they are read into the cache or are decoded.

6. Mention the advantage of using multiple issue processor?

They are less expensive. They have cache based memory system.

And More parallelism.

7. What are loop carried dependence?

They focuses on determining whether data accesses in later iterations are

dependent on data values produced in earlier iterations; such a dependence is

called loop carried dependence.

e.g for(i=1000;i>0;i=i-1)

x[i]=x[i]+s;

8. Mention the tasks involved in finding dependences in instructions?

Good scheduling of code. Determining which loops might contain parallelism Eliminating name dependence

9. Use the G.C.D test to determine whether dependence exists in the following loop:

for(i=1;i R ordering

W->W ordering

R->W and R-> R ordering.

18. What is multi threading?

Multithreading allows multiple threads to share the functional uits of the

single processor in an overlapping fashion.

19. What is fine grained multithreading?

It switches between threads on each instruction, causing the execution of

multiple threads to be interleaved.

20. What is coarse grained multithreading?

It switches threads only on costly stalls. Thus it is much less likely to slow

down the execution of an individual thread. PART-B

1.i) what is meant by the dynamic data flow computer and explain it?

ii) List out the differences between RISC and CISC processors.

2.Explain in detail about standard I/O interfaces.

3.Give the advantage of fault tolerant system.

4.Explain the various ways to measure I/O performance?

Throughput versus response time

Little queuing theory

5.i) what is meant by interrupts and explain its types?

ii) Discuss in briefly about IOP.

6.Explain the static and dynamic dataflow design.

7.Explain detail about the direct Access memory.

8.Explain the techniques that are available to access the I/O devices.

9.what are interface circuits? Explain in detail.