COMPUTER ORGANIZATIONR 402 2+1+0

Module 1Introduction: Organization and Architecture – Review of basic operational concepts – CPU- single bus and two bus organization, Execution of a complete instruction – interconnection structures – layered view of a computer system.

Module 2CPU - Arithmetic: Signed addition and subtraction – serial and parallel adder – BCD adder – Carry look ahead adder, Multiplication – Array multiplier – Booth’s Algorithm, Division – Restoring and non-restoring division, floating point arithmetic - ALU Design.

Module 3Control Unit Organization: Processor Logic Design – Processor Organization – Control Logic Design – Control Organization – Hardwared control – Microprogram control – PLA control – Microprogram sequencer, Horizontal and vertical micro instructions – Nano instructions.

Module 4Memory: Memory hierarchy – RAM and ROM – Memory system considerations – Associative memory, Virtual memory – Cache memory – Memory interleaving.

Module 5Input – Output: Printers, Plotters, Displays, Keyboard, Mouse, OMR and OCR, Device interface – I/O processor – Standard I/O interfaces – RS 232 C, IEEE 488.2 (GPIB).

References

Computer Organization - Hamacher, Vranesic and Zaky, Mc Graw HillDigital Logic and Computer Design - Morris Mano, PHIComputer Organization and Architecture -William Stallings, Pearson Education Asia.Computer Organization and Design - Pal Chaudhuri, PHIComputer Organization and Architecture -M Morris Mano, PHIComputer Architecture and Organization - John P Hayes, Mc Graw Hill

Module 1Organization and architecture:

Computer is a fast electronic calculating machine that accepts digitized informaton and processes it according to a list of internally stored instructions and producing the resulting output.

The computer consists of five functionally independent main parts. Input ,memory, arithmetic and logic unit, output and control unit. Computer architecture in computer engineering is the conceptual design and fundamental operational structure of a computer system. It is a blueprint and functional description of requirements (especially speeds and interconnections) and design implementations for the various parts of a computer.

It may also be defined as the science and art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. Computer architecture comprises at least three main subcategories:

• Instruction set architecture, or ISA, is the abstract image of a computing system that is seen by a machine language (or assembly language) programmer, including the instruction set, memory address modes, processor registers, and address and data formats.

• Microarchitecture, also known as Computer organization is a lower level, more concrete and detailed, description of the system that involves how the constituent parts of the system are interconnected and how they interoperate in order to implement the ISA.

• System Design which includes all of the other hardware components within a computing system such as:

1. computer buses and switches 2. memory controllers and hierarchies 3. direct memory access 4. multi-processing.

Basic functional units of computer

Input unitAn input device is any peripheral used to provide data and control signals to an

information processing system. Input and output devices make up the hardware interface between a computer as a scanner Computers accept coded information through input units, which read data. When a key is pressed, corresponding letter or digit is automatically translated into its corresponding binary code and transmitted over a cable to either the memory or the processor

MemoryStore data2 types of memoryPrimary memory and secondary memoryPrimary memory-RAMSecondary Memory-Hard Disk Arithmetic and logic unit

An arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers.ALU sets Flags as the result of operations.

Basic operational concepts

The activity of computer is governed by instruction. To perform a given task, an appropriate program consisting of list of instruction is stored in the memory. Individual instructions are brought from the memory into the processor, which execute the specified operation. Data to be used as operands are also stored in the memory.E.g.: Add LOCA,R0

This instruction adds the operand at memory location LOCA to the operand in register in the processor,R0,and places the sum into register R0.The original content in location LOCA are preserved where as R0 is overwritten.The steps included are1.The instruction is fetched from the memory into the register.2.The operand at LOCA is fetched and added to the contents of R0.3.The resulting sum is stored in the register R0.

This can be also realized by two instruction sequence.

Load LOCA, R1Add R1, R0

Transfers between the memory and the processor are started by sending the address of the memory location to be accessed to the memory unit and issuing the appropriate control signals. The data are then transferred to or from the memory.

In addition to the ALU and the control circuitry, the processor contains a number of registers used for several different purposes. The instruction register (IR) holds the instruction that is currently being executed. Its output is available to the control circuit, which generate the timing signals that controls the various processing elements involved in executing the instruction.

The program counter is another specialized register. it keep track of execution of the program. it contains the memory address of next instruction to be fetched and executed. During the execution of an instruction the contents of PC is updated to correspond to the address of the next instruction to be executed.

Two register facilitate the communication with the memory. These are memory address register (MAR) and memory data register (MDR). The MAR holds the address of the location to be accessed. The MDR contains the data to be written into or read out of the address location. Let us consider some typical operational steps.

Execution of program starts when the PC is set to the point of first instruction of the program

The contents of PC are transferred to the MAR and read signal is sent to the memory.

After the time required to access the memory elapses, the addressed word read out of the memory and loaded into MDR

The contents of MDR transferred to the IR and instruction is ready to be decoded and executed.If the instruction involves an operation to be performed by ALU,it is necessary to obtain the required operands.

If the operand resides in the memory, it has to be fetched by sending its address to the MAR and initiating a read cycle. When the operand has been read from the memory to MDR, its transferred from the memory to ALU

If the result is to be stored in the memory, the result is sent to the MDR.the address of the location where the result is stored is sent to the MAR and write cycle is enabled.

The contents of the PC are incremented so that PC points to next instruction to be executed.

Normal execution of the programs can be preempted by executing interrupt service routine. the device raises an interrupt signal. An interrupt is a request from i/o device for service by the processor.the processor provides the requested service by executing an appropriate interrupt service routine. since such diversions may alter the internal state of the processor,its state must be saved in the memory,before servicing the interrupt. Normally contents of PC,general registers and some control information are stored.

BUS ORGANISATION IN CPUA group of lines that serves as a connecting pathfor several devices is called a

bus.In addition to lines trhat carry data,the bus must hav lines for address and control purposes.The simplest way to interconnect functional units is to use a single bus.• A Bus is a group of electrical conductors suitablefor carrying computer signals from one location toanother• Buses are used to transfer data/instructions amongcomputer peripherals, memory and the CPU• The lines on a bus can be grouped into fourcategories:– Data,– Addressing,– Control, and– PowerDifferent Buses for ConnectingDifferent parts of the Computer• The buses internal to the CPU don’t have a names• The CPU bus, Peripheral Connect Interface (PCI) or Video ElectronicStandards Association (VESA) local bus, and Industry StandardArchitecture (ISA) bus are all part of the Backplane as shown• The PCI, VESA local, also known as VL, and ISA buses are examples ofpopular modern external buses• A bus protocol is an agreement between two or more entities thatestablish a clear, common path of communication and understandingbetween them• Buses can be characterized by:– Throughput (Data Transfer Rate, bit/second),– the Data Width in bits,– the distance between the two end points,– the type of control required,– the type of bus,– the addressing capacity, and– the dedicated line or shared line inside the bus

Single Bus

the simplest and most economical means for interconnecting a number of modulesis to use a single bus. since several modules are connected to the bus and any module can request a data transfer at anytime,it is essential to have an efficient bus arbitrationscheme.

Bus arbitrationThe device that is allowed to initiate the data transfer on the bus at any

given time is called the bus master. bus arbitration is the process by which the next process to become the bus master must take into account the needs of various devices by establishing a priority system for gaining access to the bus.There are two approaches to bus arbitration.

Centralized arbitration, Distributed arbitration.A simple arrangement to connect I/O devices to a computer is to use a single bus arrangement. The bus enables all the devices connected to it to exchange information. Typically it consists of three sets of lines used to carry address, data and control signals. Each I/O device is assigned a unique set of addresses. When the processor places a particular address on the address lines, the devise that recognize the address respond to the commands issued on the control lines. The processor requests either a read or a write operation, and the requested data are transferred over the data lines. When I/O devices and the memory share the same address space, the arrangement is called memory-mapped I/O

Bus

Two-Bus organization

Two bus organisation is a faster solution than one bus organisation.in this case general purpose registers are connected to both buses.Therefore a two operand operation can fetch both operands at same clock cycle.An additional buffer register may be needed to hold the output of ALU,when the two buses are busy.

processor Memory

I/O device1 I/O device n