COMPUTER ARCHITECTURECS 1251 VI SEMESTERCHAPTER - 1UNIT 1 --------BASIC STRUCTURE OF COMPUTERSPART ndash A1Write the basic functional units of computer The basic functional units of a computer are input unit output unit memory unit ALU unit and control unit2Define ALU What are the various operations performed in ALUALU is a part of computer that performs all arithmetic and logical operations It is a component of central processing unitArithmetic operations Addition subtraction multiplication division increment and decrementLogical operations AND OR XOR NOT compare shift rotate-3 Compute the effective CPI for a processor for the following instruction mixInstruction type Clock cycle count FrequencyALU operations 1 40Loads 3 20Stores 2 10Branches taken 3 20Branches untaken 2 10An enhancement to the processor is made by adding a branch prediction unit This decreases the number ofcycles taken to execute a branch from 3 to 2 What is the improvement in performance Speed up =execution time old execution time newExecution time old or CPU time=IC Clk Cycles cycle timeExecution time old =[401+203+102+202+102]Cyclescycles timeThe enhancement decreases the number of cycles taken for branch instruction from 3 to 2Execution time new =[401+203+102+202+102]=180 cycles cycle timeSpeed up = (200cycles time)(180 cycles cycles time) =114What is a bus What are the different buses in a CPUA group of lines that serve as a connecting path for several devices is called bus The different buses in a CPU are1] Data bus2] Address bus3] Control bus5 Why data bus is bidirectional and address bus is unidirectional in most microprocessorData bus

The data bus consists of 8 16 32 or more parallel signal lines These lines are used to send data tomemory and output ports and to receive data from memory and input port Therefore data bus lines arebidirectional This means that CPU can read data on these lines from memory or from a port as well as send dataout of these lines to a memory location or to a port The data bus is connected in parallel to all peripherals Thecommunication between peripherals and CPU is activated by giving output enable pulse to the peripherals Outputsof peripherals are floated when they are not in useAddress busIt is a unidirectional bus The address bus consists of 16 20 24 or more parallel signal lines On these lines theCPU sends out the address of the memory location or IO port that is to be written to or read from Here thecommunication is one-way the address is send from CPU to memory and IO port and hence these lines areunidirectional6 What is meant by stored program concepts DiscussStored program concept is an idea of storing the program and data in the memory7 Define multiprogrammingMultiprogramming is a technique in several jobs are in main memory at once and the processor is switchedfrom job as needed to keep several jobs advancing while keeping the peripheral devices in use8 Define multiprocessingMultiprocessing is the ability of an operating system to support more than one process at the same time9 Define time sharingTime sharing is the process in which the system is designed to allow many users to use the CPU simultaneously10 What is a super computerA computer with high computational speed very large memory and expansive parallel structured hardware isknown as a super computerEX CDC 660011 What is meant by VLSI technologyVLSI is the abbreviation for Very Large Scale Integration In this technology millions of transistors areput inside a single chip as tiny components The VLSI chips do the function of millions of transistors These areused to implement parallel algorithms directly in hardware12 What are the characteristics of Von Neumann computers

The program can data were represented in digital form and stored in the memory The architecture has 5 basic parts -gt the memory the ALU Control Unit Input unit and output unit It uses binary arithmetic There were only fixed point arithmetic and no floating point arithmetic used a special general purpose register called Accumulator The first general purpose machine13 Define parallel processingIt is an efficient form of information processing to exploit the concurrent events in the computing process14 Define pipeliningPipelining is technique of decomposing a sequential process in to number of sub operations and each of thesesub operations are carried out independently in dedicated segments concurrently15 Mention some applications of parallel processing In simulation and Modeling -gt weather forecasting oceanography socio economy Engineering design and automation -gt Aerodynamics finite element analysis AI Medical military and research -gt computer assisted topography genetic engineering etc Energy resource explosion16 In what way hardware and software are equivalent Not equivalentSoftware and hardware are logically equivalent Any operation done by software could be done by hardwareAny instruction executed by hardware can be simulated by software They are not equivalent in the sense thatminimum hardware required to execute software cannot be simulated by software In other words with out thehardware software cannot function whereas with NIL software the hardware function perfectly17 Distinguish between hardware and firmwareThe hardware deals with all electronics and electrical components of a computerEX ICrsquos diodes resistors power supplies tapes etcThe firmware is embedded software of certain electronic circuitsEX ROMBIOS18 What is an operating systemA System software which acts as an interface between the user and the machine19 Define system throughputIt is defined as the number of instructions executed per unit time (sec)

20 What is mainframe computerIt is the large computer system containing thousands of ICrsquos It is a room- sized machine placed inspecial computer centers and not directly accessible to average users It serves as a central computing facilityfor an organization such as university factory or bank21 What is mini computerMinicomputers are small and low cost computers are characterized bybull Short word size ie CPU word sizes of 8 or 16 bitsbull Limited hardware and software facilitiesbull Physically smaller in size2 Define micro computerMicrocomputer is a smaller slower and cheaper computer packing all the electronics of the computerin to a handful of ICrsquos including the CPU and memory and IO chips25 What is workstationThe more powerful desktop computers intended for scientific and engineering applications arereferred as workstations26 Write the features of the third generation computersbull Pipelining concept was introducedbull Cache memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introducedbull Ex IBM 360370 CDC 66007600 Texas Instrumentrsquos ASC (Advanced Scientific Computer) DigitalEquipmentrsquos PDP-8CHAPTER-2UNIT 1 ----------MACHINE INSTRUCTIONS AND ADDRESSING MODESPART-A1 What is load ndash store architectureIn a load store architecture operands must be in registers before they can be processed Theinstructions that refer to memoryLocations are load store and jump branch It supports limited set of addressing modes and use hardwareto execute instructions2 Explain the absolute and auto increment addressing modes with an example instruction

Absolute or direct addressing To fetch an operand the address of the operand in the memory is givenin the instruction This form is called direct addressing This type of addressing mode is used for handlingSTATIC dataAdd B=gt A = A + M [B]Auto-increment addressing mode It is similar to register indirect mode except that register is incrementedafter its value is used to access memoryAdd R1 (R2) + R1 lt- R1 + M [R2]R2 lt- R2 +dThis type of addressing mode is useful for stepping through arrays in a loopR2 ndash start of array d ndash size of an element3 List out the different computer instruction formats4 address instructionOpcode Source operaaddress 1Source operaaddress 2Destination operaaddressNext instructiaddress3 address instructionOpcode Source operand address Source operand address Destination operaaddress2 address instructionOpcode Source destination operaaddressSource operand address 21 address instructionOpcode Source operand address0 address instructionOpcode4 Explain the following addressing modes with an examplea) Register indirect addressingb) Relative addressingRegister indirect addressingThe effective address of the operand is the contents of the register or memorylocation whose address appears in the instructionAdd R1 R2 [R3] R1 = R2+ [R3] Contents of memory pointed by R3Application1 used in pointers

R3MemoryRelative addressingThe effective address is obtained by adding contents of program counter with displacementEffective address = [PC] + displacementEx near far short jump instructions1 mem address instruction displacement1000 near 10EA for next instruction = [PC] + 10= 1001 + 10= 10112 mem address instruction displacement4000 JC 50EA = 4001 + 50= 40515 Define index modeIn this mode the contents of the index register is added to the address part of the instruction to getthe EA of the operand The index register is a special purpose CPU register that contains the index value Theaddress part of the instruction determines the starting address of the data array in the memory Each operand inthe array is stored in the memory relative to the starting address of the array The distance between the startingaddress of the array and the location of the operand in the array is the index value present in the index registerAny operand in the array can be accessed with the same instruction provided that the index register contains thecorrect index value The index register can be incremented to facilitate access to the consecutive operandsSome computers dictate one CPU register to function as index register This register is involved implicitly whenthe index mode instruction is usedUSEThe indexed mode is used to access the array type data structure6What is the role of program counter in addressingIn this addressing mode the contents of program counter is added to the address part of theinstruction in order to obtain the EA When the address part of the instruction is added to the contents of thePC the result produces the EA whose position is relative to the next instruction7What are the different addressing modesDirect addressing indirect addressing immediate addressing base addressing Index addressing

based index addressing based indexed with displacement addressing relative addressing8Compare the stack based architecture with GPR based architectureStack based Vs GPR basedbull Reading a register in GPR architecture does not affect its contents but reading in stack architectureremoves the data form top of the stackbull Lot of over head involved in maintaining temporary variables in the stackbull In stack based architecture the register file stack is invisible to the programmer Only the top of thestack is visible Hence easier to maintain compatibility with future versionsbull Instruction lengths are smaller in stack based ndash because the source and destination specifies are notrequired Hence the code length may be smallerAdd R1 R2 [R3]Operand9Consider a two level indirection instruction such as Mov A [ind] where ind points to the memorylocation that contains the address of the operand that needs to be moved to register A give an application ofsuch two level indirectionPointer implementation is made easy with indirection With two level indirection it is easier tohandle pointer of pointer10What are condition codes Can a processor be designed without any condition codesCondition codes are 1- bit flag that store information regarding the result of various operationsThese are used in conditional branch instructions They give elegant way of handling the conditional controlflowA processor may be designed without condition codes but it must have some other means of handlingchange in flow control ndash may be instructions like compare and branch if equal to zero11 Which data structures can be best supported using (a) indirect addressing mode (b) indexedaddressing mode(a) indirect addressing mode ndash pointer data structure(b) indexed addressing mode ndash array data structure12 What are the four basic types of operations that need to be supported by an instruction setbull Data transfer between memory and the processor register

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

The data bus consists of 8 16 32 or more parallel signal lines These lines are used to send data tomemory and output ports and to receive data from memory and input port Therefore data bus lines arebidirectional This means that CPU can read data on these lines from memory or from a port as well as send dataout of these lines to a memory location or to a port The data bus is connected in parallel to all peripherals Thecommunication between peripherals and CPU is activated by giving output enable pulse to the peripherals Outputsof peripherals are floated when they are not in useAddress busIt is a unidirectional bus The address bus consists of 16 20 24 or more parallel signal lines On these lines theCPU sends out the address of the memory location or IO port that is to be written to or read from Here thecommunication is one-way the address is send from CPU to memory and IO port and hence these lines areunidirectional6 What is meant by stored program concepts DiscussStored program concept is an idea of storing the program and data in the memory7 Define multiprogrammingMultiprogramming is a technique in several jobs are in main memory at once and the processor is switchedfrom job as needed to keep several jobs advancing while keeping the peripheral devices in use8 Define multiprocessingMultiprocessing is the ability of an operating system to support more than one process at the same time9 Define time sharingTime sharing is the process in which the system is designed to allow many users to use the CPU simultaneously10 What is a super computerA computer with high computational speed very large memory and expansive parallel structured hardware isknown as a super computerEX CDC 660011 What is meant by VLSI technologyVLSI is the abbreviation for Very Large Scale Integration In this technology millions of transistors areput inside a single chip as tiny components The VLSI chips do the function of millions of transistors These areused to implement parallel algorithms directly in hardware12 What are the characteristics of Von Neumann computers

The program can data were represented in digital form and stored in the memory The architecture has 5 basic parts -gt the memory the ALU Control Unit Input unit and output unit It uses binary arithmetic There were only fixed point arithmetic and no floating point arithmetic used a special general purpose register called Accumulator The first general purpose machine13 Define parallel processingIt is an efficient form of information processing to exploit the concurrent events in the computing process14 Define pipeliningPipelining is technique of decomposing a sequential process in to number of sub operations and each of thesesub operations are carried out independently in dedicated segments concurrently15 Mention some applications of parallel processing In simulation and Modeling -gt weather forecasting oceanography socio economy Engineering design and automation -gt Aerodynamics finite element analysis AI Medical military and research -gt computer assisted topography genetic engineering etc Energy resource explosion16 In what way hardware and software are equivalent Not equivalentSoftware and hardware are logically equivalent Any operation done by software could be done by hardwareAny instruction executed by hardware can be simulated by software They are not equivalent in the sense thatminimum hardware required to execute software cannot be simulated by software In other words with out thehardware software cannot function whereas with NIL software the hardware function perfectly17 Distinguish between hardware and firmwareThe hardware deals with all electronics and electrical components of a computerEX ICrsquos diodes resistors power supplies tapes etcThe firmware is embedded software of certain electronic circuitsEX ROMBIOS18 What is an operating systemA System software which acts as an interface between the user and the machine19 Define system throughputIt is defined as the number of instructions executed per unit time (sec)

20 What is mainframe computerIt is the large computer system containing thousands of ICrsquos It is a room- sized machine placed inspecial computer centers and not directly accessible to average users It serves as a central computing facilityfor an organization such as university factory or bank21 What is mini computerMinicomputers are small and low cost computers are characterized bybull Short word size ie CPU word sizes of 8 or 16 bitsbull Limited hardware and software facilitiesbull Physically smaller in size2 Define micro computerMicrocomputer is a smaller slower and cheaper computer packing all the electronics of the computerin to a handful of ICrsquos including the CPU and memory and IO chips25 What is workstationThe more powerful desktop computers intended for scientific and engineering applications arereferred as workstations26 Write the features of the third generation computersbull Pipelining concept was introducedbull Cache memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introducedbull Ex IBM 360370 CDC 66007600 Texas Instrumentrsquos ASC (Advanced Scientific Computer) DigitalEquipmentrsquos PDP-8CHAPTER-2UNIT 1 ----------MACHINE INSTRUCTIONS AND ADDRESSING MODESPART-A1 What is load ndash store architectureIn a load store architecture operands must be in registers before they can be processed Theinstructions that refer to memoryLocations are load store and jump branch It supports limited set of addressing modes and use hardwareto execute instructions2 Explain the absolute and auto increment addressing modes with an example instruction

Absolute or direct addressing To fetch an operand the address of the operand in the memory is givenin the instruction This form is called direct addressing This type of addressing mode is used for handlingSTATIC dataAdd B=gt A = A + M [B]Auto-increment addressing mode It is similar to register indirect mode except that register is incrementedafter its value is used to access memoryAdd R1 (R2) + R1 lt- R1 + M [R2]R2 lt- R2 +dThis type of addressing mode is useful for stepping through arrays in a loopR2 ndash start of array d ndash size of an element3 List out the different computer instruction formats4 address instructionOpcode Source operaaddress 1Source operaaddress 2Destination operaaddressNext instructiaddress3 address instructionOpcode Source operand address Source operand address Destination operaaddress2 address instructionOpcode Source destination operaaddressSource operand address 21 address instructionOpcode Source operand address0 address instructionOpcode4 Explain the following addressing modes with an examplea) Register indirect addressingb) Relative addressingRegister indirect addressingThe effective address of the operand is the contents of the register or memorylocation whose address appears in the instructionAdd R1 R2 [R3] R1 = R2+ [R3] Contents of memory pointed by R3Application1 used in pointers

R3MemoryRelative addressingThe effective address is obtained by adding contents of program counter with displacementEffective address = [PC] + displacementEx near far short jump instructions1 mem address instruction displacement1000 near 10EA for next instruction = [PC] + 10= 1001 + 10= 10112 mem address instruction displacement4000 JC 50EA = 4001 + 50= 40515 Define index modeIn this mode the contents of the index register is added to the address part of the instruction to getthe EA of the operand The index register is a special purpose CPU register that contains the index value Theaddress part of the instruction determines the starting address of the data array in the memory Each operand inthe array is stored in the memory relative to the starting address of the array The distance between the startingaddress of the array and the location of the operand in the array is the index value present in the index registerAny operand in the array can be accessed with the same instruction provided that the index register contains thecorrect index value The index register can be incremented to facilitate access to the consecutive operandsSome computers dictate one CPU register to function as index register This register is involved implicitly whenthe index mode instruction is usedUSEThe indexed mode is used to access the array type data structure6What is the role of program counter in addressingIn this addressing mode the contents of program counter is added to the address part of theinstruction in order to obtain the EA When the address part of the instruction is added to the contents of thePC the result produces the EA whose position is relative to the next instruction7What are the different addressing modesDirect addressing indirect addressing immediate addressing base addressing Index addressing

based index addressing based indexed with displacement addressing relative addressing8Compare the stack based architecture with GPR based architectureStack based Vs GPR basedbull Reading a register in GPR architecture does not affect its contents but reading in stack architectureremoves the data form top of the stackbull Lot of over head involved in maintaining temporary variables in the stackbull In stack based architecture the register file stack is invisible to the programmer Only the top of thestack is visible Hence easier to maintain compatibility with future versionsbull Instruction lengths are smaller in stack based ndash because the source and destination specifies are notrequired Hence the code length may be smallerAdd R1 R2 [R3]Operand9Consider a two level indirection instruction such as Mov A [ind] where ind points to the memorylocation that contains the address of the operand that needs to be moved to register A give an application ofsuch two level indirectionPointer implementation is made easy with indirection With two level indirection it is easier tohandle pointer of pointer10What are condition codes Can a processor be designed without any condition codesCondition codes are 1- bit flag that store information regarding the result of various operationsThese are used in conditional branch instructions They give elegant way of handling the conditional controlflowA processor may be designed without condition codes but it must have some other means of handlingchange in flow control ndash may be instructions like compare and branch if equal to zero11 Which data structures can be best supported using (a) indirect addressing mode (b) indexedaddressing mode(a) indirect addressing mode ndash pointer data structure(b) indexed addressing mode ndash array data structure12 What are the four basic types of operations that need to be supported by an instruction setbull Data transfer between memory and the processor register

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

The program can data were represented in digital form and stored in the memory The architecture has 5 basic parts -gt the memory the ALU Control Unit Input unit and output unit It uses binary arithmetic There were only fixed point arithmetic and no floating point arithmetic used a special general purpose register called Accumulator The first general purpose machine13 Define parallel processingIt is an efficient form of information processing to exploit the concurrent events in the computing process14 Define pipeliningPipelining is technique of decomposing a sequential process in to number of sub operations and each of thesesub operations are carried out independently in dedicated segments concurrently15 Mention some applications of parallel processing In simulation and Modeling -gt weather forecasting oceanography socio economy Engineering design and automation -gt Aerodynamics finite element analysis AI Medical military and research -gt computer assisted topography genetic engineering etc Energy resource explosion16 In what way hardware and software are equivalent Not equivalentSoftware and hardware are logically equivalent Any operation done by software could be done by hardwareAny instruction executed by hardware can be simulated by software They are not equivalent in the sense thatminimum hardware required to execute software cannot be simulated by software In other words with out thehardware software cannot function whereas with NIL software the hardware function perfectly17 Distinguish between hardware and firmwareThe hardware deals with all electronics and electrical components of a computerEX ICrsquos diodes resistors power supplies tapes etcThe firmware is embedded software of certain electronic circuitsEX ROMBIOS18 What is an operating systemA System software which acts as an interface between the user and the machine19 Define system throughputIt is defined as the number of instructions executed per unit time (sec)

20 What is mainframe computerIt is the large computer system containing thousands of ICrsquos It is a room- sized machine placed inspecial computer centers and not directly accessible to average users It serves as a central computing facilityfor an organization such as university factory or bank21 What is mini computerMinicomputers are small and low cost computers are characterized bybull Short word size ie CPU word sizes of 8 or 16 bitsbull Limited hardware and software facilitiesbull Physically smaller in size2 Define micro computerMicrocomputer is a smaller slower and cheaper computer packing all the electronics of the computerin to a handful of ICrsquos including the CPU and memory and IO chips25 What is workstationThe more powerful desktop computers intended for scientific and engineering applications arereferred as workstations26 Write the features of the third generation computersbull Pipelining concept was introducedbull Cache memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introducedbull Ex IBM 360370 CDC 66007600 Texas Instrumentrsquos ASC (Advanced Scientific Computer) DigitalEquipmentrsquos PDP-8CHAPTER-2UNIT 1 ----------MACHINE INSTRUCTIONS AND ADDRESSING MODESPART-A1 What is load ndash store architectureIn a load store architecture operands must be in registers before they can be processed Theinstructions that refer to memoryLocations are load store and jump branch It supports limited set of addressing modes and use hardwareto execute instructions2 Explain the absolute and auto increment addressing modes with an example instruction

Absolute or direct addressing To fetch an operand the address of the operand in the memory is givenin the instruction This form is called direct addressing This type of addressing mode is used for handlingSTATIC dataAdd B=gt A = A + M [B]Auto-increment addressing mode It is similar to register indirect mode except that register is incrementedafter its value is used to access memoryAdd R1 (R2) + R1 lt- R1 + M [R2]R2 lt- R2 +dThis type of addressing mode is useful for stepping through arrays in a loopR2 ndash start of array d ndash size of an element3 List out the different computer instruction formats4 address instructionOpcode Source operaaddress 1Source operaaddress 2Destination operaaddressNext instructiaddress3 address instructionOpcode Source operand address Source operand address Destination operaaddress2 address instructionOpcode Source destination operaaddressSource operand address 21 address instructionOpcode Source operand address0 address instructionOpcode4 Explain the following addressing modes with an examplea) Register indirect addressingb) Relative addressingRegister indirect addressingThe effective address of the operand is the contents of the register or memorylocation whose address appears in the instructionAdd R1 R2 [R3] R1 = R2+ [R3] Contents of memory pointed by R3Application1 used in pointers

R3MemoryRelative addressingThe effective address is obtained by adding contents of program counter with displacementEffective address = [PC] + displacementEx near far short jump instructions1 mem address instruction displacement1000 near 10EA for next instruction = [PC] + 10= 1001 + 10= 10112 mem address instruction displacement4000 JC 50EA = 4001 + 50= 40515 Define index modeIn this mode the contents of the index register is added to the address part of the instruction to getthe EA of the operand The index register is a special purpose CPU register that contains the index value Theaddress part of the instruction determines the starting address of the data array in the memory Each operand inthe array is stored in the memory relative to the starting address of the array The distance between the startingaddress of the array and the location of the operand in the array is the index value present in the index registerAny operand in the array can be accessed with the same instruction provided that the index register contains thecorrect index value The index register can be incremented to facilitate access to the consecutive operandsSome computers dictate one CPU register to function as index register This register is involved implicitly whenthe index mode instruction is usedUSEThe indexed mode is used to access the array type data structure6What is the role of program counter in addressingIn this addressing mode the contents of program counter is added to the address part of theinstruction in order to obtain the EA When the address part of the instruction is added to the contents of thePC the result produces the EA whose position is relative to the next instruction7What are the different addressing modesDirect addressing indirect addressing immediate addressing base addressing Index addressing

based index addressing based indexed with displacement addressing relative addressing8Compare the stack based architecture with GPR based architectureStack based Vs GPR basedbull Reading a register in GPR architecture does not affect its contents but reading in stack architectureremoves the data form top of the stackbull Lot of over head involved in maintaining temporary variables in the stackbull In stack based architecture the register file stack is invisible to the programmer Only the top of thestack is visible Hence easier to maintain compatibility with future versionsbull Instruction lengths are smaller in stack based ndash because the source and destination specifies are notrequired Hence the code length may be smallerAdd R1 R2 [R3]Operand9Consider a two level indirection instruction such as Mov A [ind] where ind points to the memorylocation that contains the address of the operand that needs to be moved to register A give an application ofsuch two level indirectionPointer implementation is made easy with indirection With two level indirection it is easier tohandle pointer of pointer10What are condition codes Can a processor be designed without any condition codesCondition codes are 1- bit flag that store information regarding the result of various operationsThese are used in conditional branch instructions They give elegant way of handling the conditional controlflowA processor may be designed without condition codes but it must have some other means of handlingchange in flow control ndash may be instructions like compare and branch if equal to zero11 Which data structures can be best supported using (a) indirect addressing mode (b) indexedaddressing mode(a) indirect addressing mode ndash pointer data structure(b) indexed addressing mode ndash array data structure12 What are the four basic types of operations that need to be supported by an instruction setbull Data transfer between memory and the processor register

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

20 What is mainframe computerIt is the large computer system containing thousands of ICrsquos It is a room- sized machine placed inspecial computer centers and not directly accessible to average users It serves as a central computing facilityfor an organization such as university factory or bank21 What is mini computerMinicomputers are small and low cost computers are characterized bybull Short word size ie CPU word sizes of 8 or 16 bitsbull Limited hardware and software facilitiesbull Physically smaller in size2 Define micro computerMicrocomputer is a smaller slower and cheaper computer packing all the electronics of the computerin to a handful of ICrsquos including the CPU and memory and IO chips25 What is workstationThe more powerful desktop computers intended for scientific and engineering applications arereferred as workstations26 Write the features of the third generation computersbull Pipelining concept was introducedbull Cache memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introduced to close the speed gap between the CPU and main memorybull Multiprogramming was introducedbull Time sharing concept was introducedbull Virtual memory concept was introducedbull Ex IBM 360370 CDC 66007600 Texas Instrumentrsquos ASC (Advanced Scientific Computer) DigitalEquipmentrsquos PDP-8CHAPTER-2UNIT 1 ----------MACHINE INSTRUCTIONS AND ADDRESSING MODESPART-A1 What is load ndash store architectureIn a load store architecture operands must be in registers before they can be processed Theinstructions that refer to memoryLocations are load store and jump branch It supports limited set of addressing modes and use hardwareto execute instructions2 Explain the absolute and auto increment addressing modes with an example instruction

Absolute or direct addressing To fetch an operand the address of the operand in the memory is givenin the instruction This form is called direct addressing This type of addressing mode is used for handlingSTATIC dataAdd B=gt A = A + M [B]Auto-increment addressing mode It is similar to register indirect mode except that register is incrementedafter its value is used to access memoryAdd R1 (R2) + R1 lt- R1 + M [R2]R2 lt- R2 +dThis type of addressing mode is useful for stepping through arrays in a loopR2 ndash start of array d ndash size of an element3 List out the different computer instruction formats4 address instructionOpcode Source operaaddress 1Source operaaddress 2Destination operaaddressNext instructiaddress3 address instructionOpcode Source operand address Source operand address Destination operaaddress2 address instructionOpcode Source destination operaaddressSource operand address 21 address instructionOpcode Source operand address0 address instructionOpcode4 Explain the following addressing modes with an examplea) Register indirect addressingb) Relative addressingRegister indirect addressingThe effective address of the operand is the contents of the register or memorylocation whose address appears in the instructionAdd R1 R2 [R3] R1 = R2+ [R3] Contents of memory pointed by R3Application1 used in pointers

R3MemoryRelative addressingThe effective address is obtained by adding contents of program counter with displacementEffective address = [PC] + displacementEx near far short jump instructions1 mem address instruction displacement1000 near 10EA for next instruction = [PC] + 10= 1001 + 10= 10112 mem address instruction displacement4000 JC 50EA = 4001 + 50= 40515 Define index modeIn this mode the contents of the index register is added to the address part of the instruction to getthe EA of the operand The index register is a special purpose CPU register that contains the index value Theaddress part of the instruction determines the starting address of the data array in the memory Each operand inthe array is stored in the memory relative to the starting address of the array The distance between the startingaddress of the array and the location of the operand in the array is the index value present in the index registerAny operand in the array can be accessed with the same instruction provided that the index register contains thecorrect index value The index register can be incremented to facilitate access to the consecutive operandsSome computers dictate one CPU register to function as index register This register is involved implicitly whenthe index mode instruction is usedUSEThe indexed mode is used to access the array type data structure6What is the role of program counter in addressingIn this addressing mode the contents of program counter is added to the address part of theinstruction in order to obtain the EA When the address part of the instruction is added to the contents of thePC the result produces the EA whose position is relative to the next instruction7What are the different addressing modesDirect addressing indirect addressing immediate addressing base addressing Index addressing

based index addressing based indexed with displacement addressing relative addressing8Compare the stack based architecture with GPR based architectureStack based Vs GPR basedbull Reading a register in GPR architecture does not affect its contents but reading in stack architectureremoves the data form top of the stackbull Lot of over head involved in maintaining temporary variables in the stackbull In stack based architecture the register file stack is invisible to the programmer Only the top of thestack is visible Hence easier to maintain compatibility with future versionsbull Instruction lengths are smaller in stack based ndash because the source and destination specifies are notrequired Hence the code length may be smallerAdd R1 R2 [R3]Operand9Consider a two level indirection instruction such as Mov A [ind] where ind points to the memorylocation that contains the address of the operand that needs to be moved to register A give an application ofsuch two level indirectionPointer implementation is made easy with indirection With two level indirection it is easier tohandle pointer of pointer10What are condition codes Can a processor be designed without any condition codesCondition codes are 1- bit flag that store information regarding the result of various operationsThese are used in conditional branch instructions They give elegant way of handling the conditional controlflowA processor may be designed without condition codes but it must have some other means of handlingchange in flow control ndash may be instructions like compare and branch if equal to zero11 Which data structures can be best supported using (a) indirect addressing mode (b) indexedaddressing mode(a) indirect addressing mode ndash pointer data structure(b) indexed addressing mode ndash array data structure12 What are the four basic types of operations that need to be supported by an instruction setbull Data transfer between memory and the processor register

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

Absolute or direct addressing To fetch an operand the address of the operand in the memory is givenin the instruction This form is called direct addressing This type of addressing mode is used for handlingSTATIC dataAdd B=gt A = A + M [B]Auto-increment addressing mode It is similar to register indirect mode except that register is incrementedafter its value is used to access memoryAdd R1 (R2) + R1 lt- R1 + M [R2]R2 lt- R2 +dThis type of addressing mode is useful for stepping through arrays in a loopR2 ndash start of array d ndash size of an element3 List out the different computer instruction formats4 address instructionOpcode Source operaaddress 1Source operaaddress 2Destination operaaddressNext instructiaddress3 address instructionOpcode Source operand address Source operand address Destination operaaddress2 address instructionOpcode Source destination operaaddressSource operand address 21 address instructionOpcode Source operand address0 address instructionOpcode4 Explain the following addressing modes with an examplea) Register indirect addressingb) Relative addressingRegister indirect addressingThe effective address of the operand is the contents of the register or memorylocation whose address appears in the instructionAdd R1 R2 [R3] R1 = R2+ [R3] Contents of memory pointed by R3Application1 used in pointers

R3MemoryRelative addressingThe effective address is obtained by adding contents of program counter with displacementEffective address = [PC] + displacementEx near far short jump instructions1 mem address instruction displacement1000 near 10EA for next instruction = [PC] + 10= 1001 + 10= 10112 mem address instruction displacement4000 JC 50EA = 4001 + 50= 40515 Define index modeIn this mode the contents of the index register is added to the address part of the instruction to getthe EA of the operand The index register is a special purpose CPU register that contains the index value Theaddress part of the instruction determines the starting address of the data array in the memory Each operand inthe array is stored in the memory relative to the starting address of the array The distance between the startingaddress of the array and the location of the operand in the array is the index value present in the index registerAny operand in the array can be accessed with the same instruction provided that the index register contains thecorrect index value The index register can be incremented to facilitate access to the consecutive operandsSome computers dictate one CPU register to function as index register This register is involved implicitly whenthe index mode instruction is usedUSEThe indexed mode is used to access the array type data structure6What is the role of program counter in addressingIn this addressing mode the contents of program counter is added to the address part of theinstruction in order to obtain the EA When the address part of the instruction is added to the contents of thePC the result produces the EA whose position is relative to the next instruction7What are the different addressing modesDirect addressing indirect addressing immediate addressing base addressing Index addressing

based index addressing based indexed with displacement addressing relative addressing8Compare the stack based architecture with GPR based architectureStack based Vs GPR basedbull Reading a register in GPR architecture does not affect its contents but reading in stack architectureremoves the data form top of the stackbull Lot of over head involved in maintaining temporary variables in the stackbull In stack based architecture the register file stack is invisible to the programmer Only the top of thestack is visible Hence easier to maintain compatibility with future versionsbull Instruction lengths are smaller in stack based ndash because the source and destination specifies are notrequired Hence the code length may be smallerAdd R1 R2 [R3]Operand9Consider a two level indirection instruction such as Mov A [ind] where ind points to the memorylocation that contains the address of the operand that needs to be moved to register A give an application ofsuch two level indirectionPointer implementation is made easy with indirection With two level indirection it is easier tohandle pointer of pointer10What are condition codes Can a processor be designed without any condition codesCondition codes are 1- bit flag that store information regarding the result of various operationsThese are used in conditional branch instructions They give elegant way of handling the conditional controlflowA processor may be designed without condition codes but it must have some other means of handlingchange in flow control ndash may be instructions like compare and branch if equal to zero11 Which data structures can be best supported using (a) indirect addressing mode (b) indexedaddressing mode(a) indirect addressing mode ndash pointer data structure(b) indexed addressing mode ndash array data structure12 What are the four basic types of operations that need to be supported by an instruction setbull Data transfer between memory and the processor register

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

R3MemoryRelative addressingThe effective address is obtained by adding contents of program counter with displacementEffective address = [PC] + displacementEx near far short jump instructions1 mem address instruction displacement1000 near 10EA for next instruction = [PC] + 10= 1001 + 10= 10112 mem address instruction displacement4000 JC 50EA = 4001 + 50= 40515 Define index modeIn this mode the contents of the index register is added to the address part of the instruction to getthe EA of the operand The index register is a special purpose CPU register that contains the index value Theaddress part of the instruction determines the starting address of the data array in the memory Each operand inthe array is stored in the memory relative to the starting address of the array The distance between the startingaddress of the array and the location of the operand in the array is the index value present in the index registerAny operand in the array can be accessed with the same instruction provided that the index register contains thecorrect index value The index register can be incremented to facilitate access to the consecutive operandsSome computers dictate one CPU register to function as index register This register is involved implicitly whenthe index mode instruction is usedUSEThe indexed mode is used to access the array type data structure6What is the role of program counter in addressingIn this addressing mode the contents of program counter is added to the address part of theinstruction in order to obtain the EA When the address part of the instruction is added to the contents of thePC the result produces the EA whose position is relative to the next instruction7What are the different addressing modesDirect addressing indirect addressing immediate addressing base addressing Index addressing

based index addressing based indexed with displacement addressing relative addressing8Compare the stack based architecture with GPR based architectureStack based Vs GPR basedbull Reading a register in GPR architecture does not affect its contents but reading in stack architectureremoves the data form top of the stackbull Lot of over head involved in maintaining temporary variables in the stackbull In stack based architecture the register file stack is invisible to the programmer Only the top of thestack is visible Hence easier to maintain compatibility with future versionsbull Instruction lengths are smaller in stack based ndash because the source and destination specifies are notrequired Hence the code length may be smallerAdd R1 R2 [R3]Operand9Consider a two level indirection instruction such as Mov A [ind] where ind points to the memorylocation that contains the address of the operand that needs to be moved to register A give an application ofsuch two level indirectionPointer implementation is made easy with indirection With two level indirection it is easier tohandle pointer of pointer10What are condition codes Can a processor be designed without any condition codesCondition codes are 1- bit flag that store information regarding the result of various operationsThese are used in conditional branch instructions They give elegant way of handling the conditional controlflowA processor may be designed without condition codes but it must have some other means of handlingchange in flow control ndash may be instructions like compare and branch if equal to zero11 Which data structures can be best supported using (a) indirect addressing mode (b) indexedaddressing mode(a) indirect addressing mode ndash pointer data structure(b) indexed addressing mode ndash array data structure12 What are the four basic types of operations that need to be supported by an instruction setbull Data transfer between memory and the processor register

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

based index addressing based indexed with displacement addressing relative addressing8Compare the stack based architecture with GPR based architectureStack based Vs GPR basedbull Reading a register in GPR architecture does not affect its contents but reading in stack architectureremoves the data form top of the stackbull Lot of over head involved in maintaining temporary variables in the stackbull In stack based architecture the register file stack is invisible to the programmer Only the top of thestack is visible Hence easier to maintain compatibility with future versionsbull Instruction lengths are smaller in stack based ndash because the source and destination specifies are notrequired Hence the code length may be smallerAdd R1 R2 [R3]Operand9Consider a two level indirection instruction such as Mov A [ind] where ind points to the memorylocation that contains the address of the operand that needs to be moved to register A give an application ofsuch two level indirectionPointer implementation is made easy with indirection With two level indirection it is easier tohandle pointer of pointer10What are condition codes Can a processor be designed without any condition codesCondition codes are 1- bit flag that store information regarding the result of various operationsThese are used in conditional branch instructions They give elegant way of handling the conditional controlflowA processor may be designed without condition codes but it must have some other means of handlingchange in flow control ndash may be instructions like compare and branch if equal to zero11 Which data structures can be best supported using (a) indirect addressing mode (b) indexedaddressing mode(a) indirect addressing mode ndash pointer data structure(b) indexed addressing mode ndash array data structure12 What are the four basic types of operations that need to be supported by an instruction setbull Data transfer between memory and the processor register

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

bull Arithmetic and logic operations on databull Program sequencing and controlbull io transfer13 What are the limitations of assembly languagesLimitations of assembly language1 Assembly language is processor dependent hence requires knowledge of internal details of processor towrite a program2 It is less user friendly than higher level languages3 program development is slower than the program development using high level languages14 The memory unit of a computer has 256 K words of 32 bits each The computer has an instructionformat with four fields an operation code field a mode field to specify one of seven addressing modes amemory address Specify the instruction format and the number of bits in each field if the instruction is in onememory wordTotal memory size = 256 K 32 bits= 1024 KbytesAddress bits = 20Mode field = 3 bit 2^3 = 8 gt7Register address field = 6 bits 2^6 = 64gt 60Opcode field = 32 - 20 ndash 3 ndash 6=3 bits15 List the steps involved in the instruction executionbull Fetch the instruction from the memorybull Decode the instructionbull Fetch the operands from the memory for executing the instructionbull Execute the instructionbull Store the results16 Explain the various instruction typesInstructions are of many typesbull Data movement instructionbull Dyadic operationsbull Monadic operationsbull Comparisons and conditional jumpsbull Procedure call instructionbull Loop controlbull Input output17 Explain the various addressing modesThe general subject of specifying where the operands are is called addressingbull Immediate addressingbull Direct addressingbull Register addressingbull Relative addressing

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

bull Indirect addressingbull Register indirect modebull Multilevel indirect addressingbull Indexed address modebull Base register addressing modebull Auto increment or auto decrement modebull Implied addressingbull Stack addressingCHAPTER 3UNIT 2 ---ARITHMETIC UNIT1 Discuss the IEEE format used for representing single- precision floating point numbersIEEE standard signal precision floating point numberSignal Precision 32 bit32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess ndash 1271-signifies - representationValue represented = plusmn1M X 2Ersquo ndash 1272 Discuss the principle of operation of a carry save adderPrinciple of Carry save AdderMultiplication requires addition of several summands Carry-save adder (CSA) speeds up the addition ofsummands Here instead of carry rippling along the rows they are saved and introduced into next row incorrect weight positionFor Example101101 (45) Mx 111111 (63) Q101101 A101101 B101101 C101101 D101101 E101101 F10110001011 Product(2835)3 Define Bit slice ndash ProcessorBit Slice ALU It is a technique for construction an ALU from modules each of which processes 1 bitdata or slice of an operandFor Eg Two 4 bit ALU could be arranged side by side to form an 8 bit ALU4 State the principles of operation of a carry ndash look ahead adder

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

Principles of Carry look ahead adderCarry look ahead adder is a method for speeding up the addition process It is done by eliminating carrydelay rippling through stagesFor ExampleFull adderSi = XiYi + Ci + XiYiCi + XiYiCi + XiYiCi

Ci+1 = YiCi + XiCi + XiYi

= XiYi + (Xi+Yi)Ci

= Gi + PiCi

Gi = XiYi Generate functionPi = Xi + Yi Propagate functions5 Write IEEE standard for Floating point formatThe IEEE standard describes the floating point representations and the way in which the four basicarithmetic operations are to be performed on these floating point operandsThere are two types of representations for floating point numbers1 Single precision2 Double precision32 bitS Ersquo MSign of 8 bit signed 23 bit mantissafractionNumber exponent0-signifies + excess - 1271-signifies - representationSingle precision (32 bit)Value represented = plusmn1M X 2Ersquo ndash 127Double precisionDouble precision representation contains 11 bits excess -1023 exponent Ersquo which has the range 1le Ersquo le2046 for normal values This means that the actual exponent E is in range -1022 le E le 1023 The 53 bitmantissa provides a precision equivalent to about 16 decimal digits64 bitS Ersquo MSign bit 11 Bit excess -1023 52 ndash bit mantissa fractionExponent6 Define overflowOverflow If the result of an arithmetic operation is outside the representable range then overflow issaid to occur7 Define UnderflowIf the result of the arithmetic operation involving n-bit numbers is too small to represent by n- bitsunderflow is said to occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

8 What is the principle of Boothrsquos multiplication techniqueSkipping over of 1rsquos Recording of multipliers such that a whenever a series of 1rsquos occur themultiplication operation corresponding to it can be replaced by an addition of two numbers9 What is the purpose of guard bits used in floating ndash point operationsThe guard bits are the extra bits which is used to retain the intermediate steps to increase the accuracy inthe final resultsExample In 32 bit single precision floating point representation the Mantissa bits are limited to 24 bitincluding leading 1 some operations which results in extra bits are called guard bits10 Give the Boothrsquos recording and bit ndash pair recording of the number 10001111010001011 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-1 0 0 1 0 0 0 -1 1 -1 0 0 1 -1 1 -1Bit pair recoding1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 [0]-2 -1 0 -1 1 0 +1 +111 Draw the symbolic representation of the full adder and gibe the expression for the sumXi Yi

Ci+1 Ci

Si

12 In conforming to the IEEE standard mention any four situations under which a process setsexception flag1 Under flow2 Over flow3 Divide by Zero4 Invalid13 Why floating point number is more difficult to represent and process than integerIn floating point numbers we have to represent any number in three fields sign exponent and mantissaThe IEEE 754 standard gibes the format for these fields and according to format the numbers are to berepresented In case of any process we have to consider mantissa and exponent separately Thereforefloating point numbers are more difficult to represent and process than integer14 Draw a full adder circuit and give the truth tableInputs OutputsA B Cin Carry Sum

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Truth table for full adderCin

ASumBBlock schematic of full ndash adder15 Give any 2rsquo complement multiplier algorithmbull Robertsonrsquos algorithmbull Boothrsquos algorithm16 What is spatial expansion in ALUIn this expansion connect K copies of the m-bit ALU in the manner of a ripple carry adder to form asingle ALU capable of processing Km bit words directly17 What is temporal expansion in ALUIn this expansion use one copy of the m-bit ALU chip in the manner of a serial adder to perform anoperation on Km-bit words in K consecutive steps In each step the ALU processes a separate m-bit slice ofeach operand This processing is also called multi cycle or multi precision processing18 When a ALU is said to be bit slicedAn ALU is said to be bit sliced if each component ALU concurrently process a separate ldquoSlicerdquo of mbits from each Km ndash bit operand19 Give the advanced features of ALU1048729 Floating point arithmetic circuit1048729 Pipelined circuit1048729 Co-processorFullAdder20 What is a co-processorA co-processor a separate instruction set processor that is closely coupled to CPU and whoseinstructions and registers are direct extensions of CPU21 What is a co-processor trapEven if no coprocessor is present Co-processor instructions can be included in CPU programs because

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

if the CPU knows that no Co-Processor is present it can transfer program to a predetermined memorylocation where a software routine implementing the desired co-processor instruction is stored This CPUgenerated interrupt is called a Co-processor trap22 Define Micro operationA micro operation is an elementary operation performed with data stored in the register23 What are the types of micro operationsThere are four types of micro operations1048729 Arithmetic micro operation performs arithmetic operations on the data stored in the register1048729 Logical micro operation performs bit manipulation operations on the data stored in the register1048729 Register transfer micro operation transfers binary information from one register to anotherregister1048729 Shift micro operation performs shift operations on the data stored in the registerCHAPTER 4UNIT 3 ---BASIC PROCESSING UNIT1 What are the advantages and disadvantages of hardwired and micro-programmed controlHardwired controlAdvantages1048729 It is implemented using the gates Flip Flops and hardware circuits High speed operation and henceexecution is faster1048729 Smaller implementation (component counts)1048729 Favored approach in RISC style designsDisadvantages1048729 Complex sequencing and micro operation logic1048729 Difficult to design and test1048729 Inflexible design1048729 Difficult to add new instructionsMicro-programmed controlAdvantages1048729 It stores the control signals in the sequence in control memory1048729 Modification is simple by modifying the micro program in the control memory1048729 Just read from the control memory every clock cycle1048729 Favored approach in CISC style designsDisadvantages1048729 Execution is slow1048729 Separate Control memory is used2 Define hard-wired control

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

Hard Wired control is a implemented with gates f-flips decoders and other digital circuits The goal inhard-wired design control is to minimize the number of components and maximize the speed of operation3 What are the relative advantages and disadvantages of micro-programmed control overhardwired controlAdvantages of micro programmed control over hardware control1048729 It provides considerable flexibility in implementing instruction sets1048729 It facilitates adding new instructionsDisadvantages1048729 Execution is slower1048729 Control memory is needed4 Define MicroinstructionThe individual control words in the micro program are usually referred to as microinstruction5 Faster operations can be achieved by pre-fetching the next micro-instruction while the currentone being executed What are the complexities involved in per-fetching the micro instructionWhenever the status flags need to e checked to determine the next address of the micro instructionComplex hardware is needed to handle such cases6 State the differences between hardwired and micro-programmed control unitHardwired control Micro programmed controlIt is implemented using the gatesFlip Flop and hardwired circuitsNo control memory is usedExecution is fasterModification is difficultRISC MachinesIt will be implemented using themicro program stored in the controlmemoryControl memory is usedExecution is slowerModification is simple by modifyingthe micro program in the controlmemoryCISC Machines7 Why is the Wait-For-memory-Function-Completed step needed when reading from or writing tothe main memory

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

WMFC (Wait-For-memory-Function-Completed) step is required for the write control signalreadcontrol single cause the memory bus interface hardware to issue a write command read command on thememory bus The processor wait in this process until the memory operation is completed and an WMFCresponse is received8 What are the address ndash sequencing capabilities required in a control memory1048729 Incrementing of the control address register1048729 Unconditional branch as specified by address field of the microinstruction1048729 Conditional branch depending on status bits in register of computer1048729 A facility for sub-routines calls and returns9 Discuss the principle of operation of a micro programmed control unitMicroprogramming is a second alternative for designing the control unit of a digital computer Theprinciple of microprogramming is an elegant and systematic method for controlling the micro-operationsequences in a digital computer10 What are the types of control organizations we haveThere are two types of control organizations1048729 Hardwired control organizations1048729 Micro programmed control organization11 What is a control wordA control variable which can be represented by a string of 1rsquos and 0rsquos is called a control word12 What is micro programmed control unitA control unit whose binary control variables are stored in the memory is called a micro programmedcontrol unit13 What is a micro instructionA set of micro operations constitute a micro instruction14 What is a micro programA set of micro instructions constitute a micro program15 What are the differences between the main memory and control memoryMain Memory Control MemoryIt is used storing OS routine and userProgramOrdinary user can access the mainmemory do modificationsThis is larger in sizeIt is used to store the micro programOrdinary user can not access the control

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

memory Only the designers can do thesameThis is smaller in size16 What is micro program sequencerThe next address generator is also called the micro program sequencer This will generate the address ofthe next microinstruction in the sequence17 What is meant by mapping processThe transformation from the instruction code bits to an address in the control memory where the routineis located is referenced to as a mapping process18 Give the micro instruction formatF1 F2 F3 CD BR ADWhereF1 F2 F3 rarrMicro operation fields (3 bits each)CD rarr Condition for branching (2 bits)BRrarr Branch field (2 bits)AD rarr Address field (7 bits)19 What is a hard wired logicIf a computer is designed to operate based on the control gates and other hard ware circuitry then it iscalled hard wired control logic20 What is micro programmingA technique for implementing the control function of the processor in a systematic and a flexible manneris called as micro programming21 What are the advantages and disadvantages of the microprogrammingAdvantages1048729 An instruction set can be changed by changing the micro program1048729 Any up gradation to the existing system require only to modify the micro programs1048729 Less costly compared to hard wired logicDisadvantages1048729 Comparatively slowCHAPTER 5UNIT 3------PIPLINING1 What is the ideal up expected in a pipelined architecture with lsquonrsquo stages Justify your answerIdeal SpeedupPipeliningNo of segments ndash kClock cycle time ndash tp

Tasks ndash nFirst task T1 requires ktp to complete its operations(n-1) tasks rarr (n-1) tp

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

Total time = [k + (n-1)] tpSpeedup S = ntn (k + (n-1))tp

If n is large k + (n-1) becomes n ThereforeS = ntnntp = tntp = k = No of Stages (Since)2 What is parallel processingParallel processing refers to the concept of speeding-up the execution of a program by dividing theprogram into multiple fragments that can execute simultaneously each on its own processor A programbeing executed across n-processor might execute n-times faster than it would be using a single processor3 State the different types of hazard that can occur in a pipelineTypes of hazards in pipelinebull Structural hazardsIt arises from resource conflicts when the hardware cannot support all possible combination ofinstructions in simultaneous overlapped executionbull Data hazardsIt arises when an instruction depends on the result of a previous instructionbull Control hazardsIt arises from pipelining of branches and other instructions that change the program counter4 Define nanoprogrammingMicro instructions are stored in the micro memory (control memory) There is a chance that a groupof micro instructions may occur several times in a micro program As a result the more memory space isneededBy making use of the nano memory we can have significant saving in the memory when a group ofmicro operations occur several times in a micro programThese n micro instructions can be held in a separate memory called the nano memory of size nB bitsEach of these n bits occurs once in the nano memory Each micro instruction in the original microprogram is replaced by the address that specifies the location of the nano memory in which the originalB bit wide micro instructions are heldThe micro program control unit reads an address from the micro program The contents of thisaddress in the nano memory are the desired control word The bits in the control word are used by thecontrol unit to accomplish the desired operation

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

The control unit employing the nano memory (two level) is slower than the one using a conventionalcontrol memory (single memory) This is because the nano memory requires two memory reads (one forthe control memory the other for the nano memory)5 What is pipeliningPipelining is a technique of decomposing a sequential process in to sub processes with each subprocess being executed in a special dedicated segment that operates concurrently with all otherprograms6 How do control instructions like branch cause problems in a pipelined processorPipelined processor gives the best throughput for sequenced line instruction In branch instruction asit has to calculate the target address whether the instruction jump from one memory location to other Inthe meantime before calculating the larger the next sequence instructions are got into the pipelineswhich are rolled back when target is calculated7 What is meant by super scalar processorSuper scalar processors are designed to exploit more instruction level parallelism in user programsThis means that multiple functional units are used With such an arrangement it is possible to start theexecution of several instructions in every clock cycle This mode of operation is called super scalarexecution8 Define pipeline speedupSpeed up is the ratio of the average instruction time without pipelining to the average instructiontime with pipeliningAverage instruction time without pipeliningSpeedup=Average instruction time with pipelining9 What is pipelined computerWhen a hardware is divided in to a number of sub units so as to perform the sub operations in anoverlapped fashion is called as a pipelined computer10 List the various pipelined processors8086 8088 80286 80386 STAR 100 CRAY 1 and CYBER 205 etc11 Classify the pipeline computers1048729 Based on level of processing rarr processor pipeline instructionpipeline arithmetic pipelines1048729 Based on number of functionsrarr Uni-functional and multi functionalpipelines

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

1048729 Based on the configuration rarr Static and Dynamic pipelines and linearand non linear pipelines1048729 Based on type of inputrarr Scalar and vector pipelines12 Give the basic structure of the pipeline processor13 Define efficiency of a linear pipelineEfficiency of a linear pipeline can be defined as percentage of busy time ndashspace plan over the total timendash space span This is equal to sum of all busy and idle time-space spansN = [bkTK[kn + (n-1) T] = nK + (n-1)WhereN rarr number of tasksK rarr number of pipeline stagesT rarr clock period of linear pipeline14 Define reservation table of a pipeline processorReservation table represents the flow of data through pipeline for one complete evaluation of a givenfunction15 Explain the need of an instruction buffer in a pipelined CPUR1S1R2S2R3SnRNIn order to increase the computational speed of the pipeline processor the instructions are fetched inadvance and will be placed in the instruction buffer16 Define arithmetic pipeline Where it is usedA pipeline processor which is designed to perform arithmetic operations (fixed point or floating pointarithmetic pipeline) is called arithmetic pipeline An arithmetic pipeline receives multiple data as inputs andperforms the designated operation on the data Arithmetic pipelines are used in the high-speed computerswhere a same type of operation has to be performed repeatedly on a set of data items17 What is VectorizerThe process to replace a block of sequential code by vector instructions is called vectorization Thesystem software which generates parallelism is called as vectorizing compiler

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

18 Write down the expression for speedup factor in a pipelined architectureThe speedup for a pipeline computer isS = (k + n -1) tpWhereK rarr number of segments in a pipelineN rarr number of instructions to be executedTp rarr cycle time19 Explain the delayed branch conceptWhen a branch instruction is encountered it delays the pipeline operation until the instruction at thebranch address is fetched The method used in most RISC processors is to rely on the compilers to redefinethe branches so that they take at proper time in the pipeline This method is called delayed branch20 What are the problems faced in instruction pipelineResource conflicts rarr Caused by access to the memory by two at the same time Most of the conflicts canbe resolved by using separate instruction and data memoriesData dependency rarr Arises when an instruction depends on the results of the previous instruction but thisresult is not yet availableBranch difficulties rarr Arises from branch and other instruction that change the value of PC (ProgramCounter)CHAPTER 6UNIT 4 ---MEMORY SYSTEM1 Distinguish between the write-through and write-back policies pointing out their merits anddemeritsWhen the CPU finds a word in the cache during a read operation the main memory is not involved in thetransfer however if the operation is a write there are two ways that the system can proceedThe simplest and most commonly used procedure is to update main memory with every memory writeoperation with cache memory being updated in parallel if it contains the word at the specified address Thisis called write-through method This method has an advantage that main memory always contains the samedata as the cache This care is important in systems with DMA transfers This method is simple toimplement This disadvantage is that it requires time to write data in main memory resulting in trafficThe 2nd procedure is called write-back method In this method only the cache location is updated during

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

a write operation The location is then marked by a flag so that later when the block is removed from thecache the changes are copied in to main memory The disadvantage is that main memory may containinconsistent data2 What is the necessary of virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU3 Define hit ratioWhen a processor refers a data item from a cache if the referenced item is in the cache then such areference is called Hit If the referenced data is not in the cache then it is called miss Hit ratio is defined asthe ratio of number of Hits to number of referencesNumber of HitsHit ratio =Total Number of referencesNumber of Hits=Hits + Misses4 What is meant by memory interleaving Show the distribution of addresses for a memory systemconsisting of two banks of four 1k memory modules to form an 8k memory system Give the manmemory address formatThe memory interleaving is a more effective way to address memory modulesThe low order k bits of the memory address select a module and high order m bits name a locationwithin module Here consecutive addresses are located in consecutive modulesM bits K bitsMM AddressTotal memory = 8kNo of address lines = 13Memory Bank 0 Memory Bank 1(Capacity 1K) (Capacity 1K)Since we have 2 banksK bit = 1 (To differentiate bank 0 and bank 1)k bitsFor bank selectionAddress in Module5 What is TLB What is its significance

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

Translation look aside buffer is a small cache incorporated in memory management unit It consists ofpage table entries that correspond to most recently accessed pagesSignificanceThe TLB enables faster address computingIt contains 64 to 256 entries6 What is virtual memoryVirtual memory is an important concept related to memory management It is used to increase theapparent size of main memory at a very low cost Data are addressed in a virtual address space that can be aslarge as the addressing capability of CPU7 What is the necessary for memory hierarchyMemory hierarchy ndash The major objective of designing memory hierarchy system is to provideadequate storage capacity with acceptable level of performance at a reasonable costAddress in Module ModuleModule1ABRModule 0

Module2k - 11k1k1k1k1k1k1k1k12 bits 1 bit8 How cache memory is used to reduce the execution timeIf active portions of the program and data are placed in a fast small memory the average memory accesstime can be reduced thus reducing the total execution time of the program Such a fast small memory iscalled as cache memory9 Define memory interleavingIn order to carry out two or more simultaneous access to memory the memory must be partitioned in toseparate modules The advantage of a modular memory is that it allows the interleaving ie consecutiveaddresses are assigned to different memory module

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

10 In many computers the cache block size is in the range 32 to 128 bytes What would be the mainadvantages and disadvantages of making the size of the cache blocks larger or smallerLarger the size of the cache fewer be the cache misses if most of the data in the block are actually usedIt will be wasteful if much of the data are not used before the cache block is moved from cache Smaller sizemeans more misses11 What is the function of a TLB (Translation Look-aside Buffer)A small cache called the Translation Look aside Buffer (TLB) is interporated into the memorymanagement unit which consists of the page table entries that corresponding to the most recently accessedpaper12 An eight-way set-associative cache consists of a total of 256 blocks The main memory contains8192 blocks each consisting of 128 words1 How many bits are there in the main memory address2 How many bits are there in the TAG SET and WORD fieldsThe main memory contains of 256 blocks and each block consists of 128 wordsTotal words in MM = 8192 X 128 = 1048576To address 32768 words we required (220 = 1048576) 20 bits13 What do you understand by Hit ratioHit ratio is a concept defined for any two adjacent level of a memory hierarchy When information isfound in cache we call it a hit otherwise miss This hit and miss ratio is used to measure the performance ofcache14 Define locality of reference What are its typesDuring the course of execution of a program memory references by the processor for both the instructionand the data tends to cluster There are two types1 Spatial Locality2 Temporal Locality15 List the factors that determine the storage device performanceThe storage device performance based on the following factorsbull Address reference statisticsbull Access time storage capacitybull Block sizebull Allocation algorithm16 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

2 ndash (128 x 8) RAM Chips17 What is memory systemEvery computer contains several types of devices to store the instructions and data required for itsoperation These storage devices plus the algorithm-implemented by hardware andor software-needed tomanage the stored information form the memory system of computer18 Give the classification of memoryThey can be placed into 4 groupsbull CPU registersbull Main memorybull Secondary memorybull Cache19 Define CPU register Main memory Secondary memory CacheCPU registersThese high speed registers in the CPU serve as the working memory for temporary storage ofinstruction and dataMain memoryThis large fairly fast external memory stores programs and data that are in active use Storage locationsin main memory are addressed directly by CPUrsquos load and store instructionSecondary memoryThis is larger in capacity but much slower than main memory Secondary memory stores systemsprograms larger data files that are not continuously required by CPUCacheMost computers have another level of IC memory-sometimes several such levels called cache memorywhich is positioned logically between the CPU registers and main memory20 Give the multilevel hierarchy of storage devicesThe goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance and cost We can achieve these goals by employing several memory types with differentcostperformance ratios-that are organized to provide a high average performance at a low average cost perbit The individual memory units form a multilevel hierarchy of storage devices21 What is Read Access TimeA basic performance measure is the average time to read a fixed amount of information for instance

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

one word from the memory This parameter is called the read access time22 Define Random Access Memory It storage locations can be accessed in any order and access time isindependent of the location being accessed the memory is termed a random-access memory23 What is Serial Access MemoryMemories whose storage locations can be accessed only in a certain predetermined sequence calledserial access time24 What is Semi Random AccessMemory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks Ifeach track has its own read write head the tracks can be accessed randomly but access within each track isserial In such cases the access mode is semi random25 What is ROMMemories whose contents cannot be altered online if they can be altered at all are read only memories26 What are PROMsSemi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs27 What is destructive readoutIn some memories the method of reading the memories destroys the stored information thisphenomenon is called destructive read out memory28 What do you mean by NDROMemories in which reading does not affect the stored data have non destructive read out data29 Define memory refreshingMemory refreshing is defined as the process of regaining the lost charge for this continuous refreshing isneeded30 What is SRAM and DRAMSRAMStatic random access memory It tends to be faster They require no refreshingDRAMDynamic random access memory Data is stored in the form of charges So continuous refreshing isneeded31 What is volatile memoryA memory is volatile if the loss of power destroys the stored information Information can be storedindefinitely in a volatile memory by providing battery backup or other means to maintain a continuous

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

supply of power32 What is cycle time of memoryThe minimum time that must elapse between the start of two consecutive access operations can begreater than Ta this elapsed time is called the cycle time33 What is MTBFMean Time Before Failure It is used to measure reliability Memories with no moving parts have muchhigher reliability than memories such as magnetic disks34 Give the categories of semiconductor memoriesThe semi conductor memories fall into two categories They are1 SRAM2 DRAM35 What is flash memoryA recent semiconductor technology called flash memory of a same non-volatility as a PROM but it canbe done a bit at a time36 Mention the causes of access a block of data in serial access memoryLong access time is due to several factorsbull The read-write head positioning timebull The relatively slow speed at which the tracks movebull The fact that the data transfer to and from the memory is serial rather than parallel37 How will you calculate time Tb to access a block of data in serial access memoryThe time Tb taken to access the block of data isTb = Ts + 12r + nrN38 What is a multilevel memoryA computers memory unit form a hierarchy of different memory type in which each member is in somesense subordinate to next highest member of hierarchy39 What is split cacheA cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is calledsplit cache40 Give the basic structure of cache and what is its useCache and main memory form a district sub hierarchy whose design objective is to support CPU accesswith a minimum of delay Hence hardware controllers that are transparent to both user and system programsusually manage this sub hierarchy41 What is cache data memoryMemory words are stored in cache data memory and are grouped into small pages called cache blocks or

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

lines The contents of the cachersquos data memory are thus copies of a set of main memory blocks42 Mention two system organizations for cachesTwo system organization for caches arebull Look ndash asidebull Look ndash through43 What is associate memoryIn associative memory each unit of stored information is fixed length word Any sub field of the wordcan be chosen as the key The desired key is specified by a mask register whose contents identify the bitpositions that define the key It has a select circuit which enables the data field to be accessed44 Define seek time and latency timeThe average time to move a head from one track is seek time (Ts) of the memory Once the head is inposition the desired cell may be in the wrong part of the moving track Some time is required for the cell toreach the readwrite head so that data transfer can begin The average time for this movement to take placeis the latency time (T1)45 Mention two kinds of address locality to achieve their goalTwo kinds address locality to achieve their goals arebull Associative addressing or content addressingbull Direct mapping46 What is the use of magnetic tape memories in todayrsquos usageThe magnetic tape unit is one of the oldest and cheapest forms of mass memory Its main use today is toprovide backup storage for a computer system in the event of failure of its hard disk sub system47 What is DVDA much denser type of CD digital video has recently been introduced in both read-only and read-writeforms With two recording surfaces and two storage layers per surface a DVD can have a capacity as highas 16GB48 Define magneto optical diskA magneto-optical disk memory uses rotating disks that store information in magnetic form but areaccessed by a laser beam similar to that in a CD-ROM drive Like a magnetic disk a magneto optical diskhas a magnetizable surface coating whose direction of magnetization can be polarizedCHAPTER 7UNIT 5-----INPUT OUTPUT ORGANIZATION

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

1 Distinguish between memory mapped IO and IO mapped IOMemory mapped IOWhen IO devices and the memory share the same address space the arrangement is called memorymappedIO The machine instructions that can access memory is used to transfer data to or from an IOdeviceBushelliphelliphellipSingle-Bus StructureFor example if DATAIN is the address of the input buffer of keyboard the instructionMOVE DATAIN R0 ndash Reads the data from DATAIN and stores them into processor register R0Similarly if DATAOUT is the address of the output buffer of a display unit or printer the instructionMOVE R0 DATAOUT ndash sends the data from R0 to location DATAOUTIO mapped IOHere the IO devices the memories have different address space It has special IO instructions Theadvantage of a separate IO address space is that IO devices deals with fewer address lines2 Consider a computer in which several devices are to be serviced interrupts How do you handlethis it the processor has only one request lineDaisy ChainConsider the problem of simultaneous request from two or more devices The processor has to decidewhich request to be serviced first Polling the status register of the IO devices is the simplest schemePriority is determined by the order in which devices are polled In daisy chain scheme interrupt request lineINTR is common to all devices The interrupt acknowledgement INTA propagates serially through thedevicesWhen several devices raise an interrupt request the processor responds by setting INTA line to 1 Thesignal is received by device 1 Device 1 passes the signal on to device 2 only if it does not require anyservice If device 1 has a pending request for interrupt it blocks the INTA signal and proceeds to put itsdevice identifying code on the data lines Therefore in daisy chain arrangement the device that is closest tothe processor has the highest priorityINTR

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

INTADAISY CHAINProcessorIO Device1MemoryIO Device nProcessorDevice 1 Device 2 Device n3 What is DMADMA (Direct Memory Access) provides IO transfer of data directly to and from the memory unit andthe peripheral4 Define PeripheralsPeripheral refers to any external devices connected to a computer Computer peripherals can be dividedinto two categories according to their functionsbull IO peripherals Keyboard Mouse Video Display Unit Printerbull Storage Function Secondary Memories Mass Storage Devicebull Eg CD Hard disk Magnetic disk Magnetic tape5 Distinguish between a synchronous bus and an asynchronous busIn synchronous bus both the transmitting and receiving devices use same clock for interpretation ofindividual bits Synchronous buses can operate with lower latency and higher bandwithIn an asynchronous bus the sender and the receiver generate their clock signals independentlyIt uses start stop bit for data transmission10Start bit 1 bit 1 or 2Time stop bit6 How does a processor handle an interruptMain program Interrupt service routine (ISR)1 ______________________2 ______________________i ______________________i+1 ____________________________________________m______________________Assume that an interrupt request arises during execution of instruction i steps to handle interrupt by theprocessor is as follow1 Processor completes execution of instruction i2 Processor saves the PC value program status on to stack3 It loads the PC with starting address of ISR

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

4 After ISR is executed the processor resumes the main program execution by reloading PC with(i+1)th instruction address7 Define dumb terminal0LSB

1 2 3 4 5 6 7Early CRT terminals were relatively simple in their functional capability being able to performprimitive IO operations Such terminals are some times called dumb terminals8 Why are interrupt masks provided in any processorInterrupt masks enable the higher priority devices come first and there for lower priority devices comelast This interrupt enable bits as a bit vector is called as interrupt mark which enablesdisables the devicesaccording to the correct configuration of the mask9 How does bus arbitration typically work1 A bus master waiting to use the bus asserts the bus request2 A bus master cannot the bus until its request is granted3 A bus master must signal to the arbiter the end of the bus utilization10 How is DMA operation State its advantagesDMA stands for Direct Memory Access In order to transfer bulk amount of data between memory andIO device without involvement of CPU this technique is used The advantage is fast data transfer11 What is the necessity of an interfaceAny device that has to be connected to a CPU requires an interface which takes care of the mismatch inspeed data and electrical characteristics between the CPU to the device12 Why does DMA have priority over the CPU when both request a memory transferSince the data transfer rate using DMA is quite higher than the CPU and memory transfer rate the DMAhave priority over the CPU when both request a memory transfer13 Define intra segment and inter segment communicationIntra segment communication Communication through a single computer It can communicatethrough a distance of a meter onlyInter segment communication Communication through long distance A set of computers andconnections called buses are involved14 Mention the group of lines in the system bus1 Address lines

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

2 Data lines3 Control lines15 What is bus master and slave masterInput output operations involve data transfers between IO device and Memory In all the precedingoperations Memory is passive or slave device with respect to system bus transactions Where as the CPUcan control the system bus ie serve as a bus master16 What is the use of IO controllerThe magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits called Io controllers That performs series to parallel and parallel to series format conversions andother control functions It can interface many IO devices to system bus17 Differentiate synchronous and asynchronous communicationIn synchronous communication each item is transferred during the time slot know to both the source anddestination Data transfer is slowIn asynchronous communication data transfer is faster and can be used for long distance communicationEach item being transferred is accompanied by the control signals18 What is strobe signalThe data ready request signals are used to load data from the source unit to the bus of from the bus tothe destination unit Such control signals are called strobe signals19 What is bus arbitrationThe possibility exists that several master or slave units connected to a shared bus will request access tothe bus at the same time A selection mechanism called bus arbitration is therefore required to enable thecurrent master which we still refer to as bus controller to decide among such competing requests20 Mention the types of bus arbitrationDaisy chaining Polling and Independent requesting21 What is IO control methodIt refers the data transfer between the IO device and the memory or between the IO device and the CPUEx Testing the status of the device and to determine if they require service by the CPU22 What is DMAThe CPU and IO controller interact only when the CPU yield the control of the memory bus to the IOcontroller in response to the request from the latter This level of IO control is called direct memory accessand the IO device interface control circuit is called as DMA controller

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur

23 Why the DMA does gets priority over CPU when both request memory transferThe CPU can wait to fetch instruction and data from the memory with out any damage occurring exceptthat the loss of time DMA usually transfers data from a device that canrsquot be stopped since informationcontinues to flow so loss of data may occur