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8/20/2019 Complite Report

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CHAPTER 1

INTRODUCTION

1.1 NEED OF NM TECHNOLOGY

• As VLSI technology has progressed to pack smaller, faster and increasing number of

transistors on a single chip .

• Copper/Lowk interconnect technologies for sub!"" nm C#$S ICs are impacting

system performance through increased power dissipation, signal delay, and crosstalk.

•

%ith clock fre&uencies increasing into the '() regime, the parasitic resistance,capacitance and inductance associated with these wires often lead to performance

bottlenecks which ha*e led the semiconductor and the electronic design automation

industries to adopt se*eral technological inno*ations.

• +urthermore, pre*alent high chip temperatures aggra*ated by large power dissipation

of nanometer scale ICs- and increasing current densities in wires make

electromigration in copper a constant threat to VLSI circuits.

o o*ercome all these problems nm technology is used.

1.2 NANOMETER TECHNOLOGY

• anometer is the art and science of manipulating matter at the nano scale down to

!/!,"",""" the width of the human hair - to creat new and uni&ue materials and

products00.with enormous potential to change societry..

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1.3 45 NANOMETER TECHNOLOGY

• Intel is first to reach an important milestone in the de*elopment of 12 nm logic

technology.

• +ully functional !23 #bit S4A# chips ha*e been made with 5 ! billion transistor

each.

• he memory cell si)e on this S4A# is ".316 7m8,almost half the si)e of 62 nm cell.

According to the International echnology 4oadmap for Semiconductors, the 45 nm

technology node should refer to the a*erage halfpitch of a memory cell manufactured at

around the 9"":;9""< time frame.

#atsushita and Intel started mass producing 12 nm chips in late 9"":, and A#= started

production of 12 nm chips in late 9""#, Infineon, Samsung, and Chartered

Semiconductor ha*e already completed a common 12 nm process platform. At the end of

9""#.

#any critical feature si)es are smaller than the wa*elength of light used for lithography i.e.,

!?3 nm and/or 91< nm-. A *ariety of techni&ues, such as larger lenses, are used to make sub

wa*elength features. =ouble patterning has also been introduced to assist in shrinking

distances between features, especially if dry lithography is used. It is e@pected that more

layers will be patterned with !?3 nm wa*elength at the 12 nm node. #o*ing pre*iously loose

layers such as #etal 1 and #etal 2- from 91< nm to !?3 nm wa*elength is e@pected to

continue, which will likely further dri*e costs upward, due to difficulties with !?3 nm

photoresists.

1.4 TECHNOLOGY DOMES

In 9""1, S#C demonstrated a ".9?6 s&uare micrometer 12 nm S4A# cell. In 9""


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• In anuary 9""6, Intel demonstrated a ".316 s&uare micrometers 12 nm node S4A#

cell.

• In April 9""6, A#= demonstrated a ".3:" s&uare micrometer 12 nm S4A# cell.

• In une 9""6, e@as Instruments debuted a ".91 s&uare micrometer 12 nm S4A# cell,

with the help of immersion lithography.

• In o*ember 9""6, B#C announced that it had de*eloped a 12 nm S4A# chip with a

cell si)e of less than ".92 s&uare micrometer using immersion lithography and lowk

dielectrics.

• In une 9"": #atsushita lectric Industrial Co. started mass production of Systemon

achip SoC- for use in digital consumer e&uipment based on the 12nm process

technology.

he successors to 12 nm technology are 39 nm, 99 nm, and then !6 nm technologies.

1.5 COMMERCIAL INTRODUCTION

#atsushita lectric Industrial Co. started mass production of Systemonachip SoC- for use

in digital consumer e&uipment based on the 12nm process technology.

Intel shipped its first 12 nanometer based processor, the Deon 21""series, in o*ember 9"":.

#any details about Eenryn appeared at the April 9"": Intel =e*eloper +orum. Its successor is

called ehalem. Important ad*ancesF9G include the addition of new instructions including

SS1, also known as Eenryn ew Instructions- and new fabrication materials mostsignificantly a hafniumbased dielectric-.

A#= released its Sempron II, Athlon II, urion II and Ehenom II in generally increasing

order of strength-, as well as Shanghai $pteron processors using the 12nm process

technology. he Dbo@ 36" S, released in 9"!", has its Xenon processor in 12 nm process.

he ElayStation 3 Slim model introduced Cell >roadband ngine in 12 nm process.

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1.6 EXAMPLEINTEL!S 45 NM PROCESS

At I=# 9"":, more technical details of IntelHs 12 nm process were re*ealed. Since

immersion lithography is not used here, the lithographic patterning is more difficult. (ence

many lines ha*e been lengthened rather than shortened. A more timeconsuming double

patterning method is used e@plicitly for this 12 nm process, resulting in potentially higher risk

of product delays than before. Also, the use of highk dielectrics is introduced for the first

time, to address gate leakage issues. +or the 39 nm node, immersion lithography will begin to

be used by Intel.

• !6" nm gate pitch :3 of 62 nm generation-

• 9"" nm isolation pitch ?! of 62 nm generation- indicating a slowing of scaling of

isolation distance between transistors

• @tensi*e use of dummy copper metal and dummy gates 32 nm gate length same as

62 nm generation-

• ! nm e&ui*alent o@ide thickness, with ".: nm transition layer

• 'atelast process using dummy polysilicon and damascene metal gate

• S&uaring of gate ends using a second photoresist coating? layers of carbondoped

o@ide and Cu interconnect, the last being a thick JredistributionJ layer

• Contacts shaped more like rectangles than circles for local interconnection

• Leadfree packaging

• !.36 mA/um n+ dri*e current

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• !.": mA/um p+ dri*e current, 2! faster than 62 nm generation, with higher hole

mobility due to increase from 93 to 3" 'e in embedded Si'e stressors

In a recent Chipworks re*erseengineering, it was disclosed that the trench contacts were

formed as a J#etal"J layer in tungsten ser*ing as a local interconnect. #ost trench contacts

were short lines oriented parallel to the gates co*ering diffusion, while gate contacts where

e*en shorter lines oriented perpendicular to the gates.

It was recently re*ealed that both the ehalem and Atom microprocessors used S4A# cells

containing eight transistors instead of the con*entional si@, in order to better accommodate

*oltage scaling. his resulted in an area penalty of o*er 3".

1." PROCESSOR USING 45 NM TECHNOLOGY

#atsushita has released the 12 nm Bniphier .

• %olfdale, Korkfield, Korkfield D and Eenryn are current Intel cores sold under the

Core 9 brand.

•

Intel Core i: series processors, i2 :2" Lynnfield and Clarksfield-.

• Eentium =ualCore %olfdale3# are current Intel mainstream dual core sold under

the Eentium brand.

• =iamond*ille, Eine*iew are current Intel cores with (yperhreading sold under the

Intel Atom brand.

• A#= =eneb Ehenom II- and Shanghai $pteron- uadCore Erocessors, 4egor

Athlon II- dual core processors F!G, Caspian urion II- mobile dual core processors.

• A#=Ehenom II- JhubanJ Si@Core Erocessor !"22-

• Xenon on Dbo@ 36" S model.

• Cell >roadband ngine in ElayStation 3 Slim model ; September 9""?.

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http://en.wikipedia.org/wiki/Nehalem_(microarchitecture)http://en.wikipedia.org/wiki/Nehalem_(microarchitecture)http://en.wikipedia.org/wiki/Intel_Atomhttp://en.wikipedia.org/wiki/Static_Random_Access_Memoryhttp://en.wikipedia.org/wiki/Static_Random_Access_Memoryhttp://panasonic.co.jp/corp/news/official.data/data.dir/en071010-3/en071010-3.htmlhttp://panasonic.co.jp/corp/news/official.data/data.dir/en071010-3/en071010-3.htmlhttp://en.wikipedia.org/wiki/Wolfdale_(microprocessor)http://en.wikipedia.org/wiki/Yorkfield_(microprocessor)http://en.wikipedia.org/wiki/Yorkfield_(microprocessor)http://en.wikipedia.org/wiki/Yorkfield_(microprocessor)#Yorkfield_XEhttp://en.wikipedia.org/wiki/Yorkfield_(microprocessor)#Yorkfield_XEhttp://en.wikipedia.org/wiki/Penryn_(microprocessor)http://en.wikipedia.org/wiki/Penryn_(microprocessor)http://en.wikipedia.org/wiki/Core_2http://en.wikipedia.org/wiki/Core_2http://en.wikipedia.org/wiki/Intel_Core_i7http://en.wikipedia.org/wiki/I5http://en.wikipedia.org/wiki/I5http://en.wikipedia.org/wiki/Lynnfield_(microprocessor)http://en.wikipedia.org/wiki/Clarksfield_(microprocessor)http://en.wikipedia.org/wiki/Pentium_Dual-Corehttp://en.wikipedia.org/wiki/Pentium_Dual-Corehttp://en.wikipedia.org/wiki/Wolfdale_(microprocessor)#Wolfdale-3Mhttp://en.wikipedia.org/wiki/Wolfdale_(microprocessor)#Wolfdale-3Mhttp://en.wikipedia.org/wiki/Pentium_(brand)http://en.wikipedia.org/wiki/Pentium_(brand)http://en.wikipedia.org/wiki/Intel_Atom#Diamondvillehttp://en.wikipedia.org/wiki/Intel_Atom#Pineviewhttp://en.wikipedia.org/wiki/Hyper-Threadinghttp://en.wikipedia.org/wiki/Intel_Atomhttp://en.wikipedia.org/wiki/Advanced_Micro_Deviceshttp://en.wikipedia.org/wiki/Phenom_IIhttp://en.wikipedia.org/wiki/Opteron#Opteron_.2845_nm_SOI.29http://en.wikipedia.org/wiki/Athlon_IIhttp://www.amd.com/us-en/0,,3715_15503,00.html?redir=45nm01http://www.amd.com/us-en/0,,3715_15503,00.html?redir=45nm01http://en.wikipedia.org/wiki/AMD_Turion#Turion_II_Ultrahttp://en.wikipedia.org/wiki/Advanced_Micro_Deviceshttp://en.wikipedia.org/wiki/Phenom_IIhttp://en.wikipedia.org/wiki/Xenon_(processor)http://en.wikipedia.org/wiki/Xenon_(processor)http://en.wikipedia.org/wiki/Xbox_360http://en.wikipedia.org/wiki/Cell_Broadband_Enginehttp://en.wikipedia.org/wiki/PlayStation_3#Slim_modelhttp://en.wikipedia.org/wiki/Nehalem_(microarchitecture)http://en.wikipedia.org/wiki/Intel_Atomhttp://en.wikipedia.org/wiki/Static_Random_Access_Memoryhttp://panasonic.co.jp/corp/news/official.data/data.dir/en071010-3/en071010-3.htmlhttp://en.wikipedia.org/wiki/Wolfdale_(microprocessor)http://en.wikipedia.org/wiki/Yorkfield_(microprocessor)http://en.wikipedia.org/wiki/Yorkfield_(microprocessor)#Yorkfield_XEhttp://en.wikipedia.org/wiki/Penryn_(microprocessor)http://en.wikipedia.org/wiki/Core_2http://en.wikipedia.org/wiki/Intel_Core_i7http://en.wikipedia.org/wiki/I5http://en.wikipedia.org/wiki/Lynnfield_(microprocessor)http://en.wikipedia.org/wiki/Clarksfield_(microprocessor)http://en.wikipedia.org/wiki/Pentium_Dual-Corehttp://en.wikipedia.org/wiki/Wolfdale_(microprocessor)#Wolfdale-3Mhttp://en.wikipedia.org/wiki/Pentium_(brand)http://en.wikipedia.org/wiki/Intel_Atom#Diamondvillehttp://en.wikipedia.org/wiki/Intel_Atom#Pineviewhttp://en.wikipedia.org/wiki/Hyper-Threadinghttp://en.wikipedia.org/wiki/Intel_Atomhttp://en.wikipedia.org/wiki/Advanced_Micro_Deviceshttp://en.wikipedia.org/wiki/Phenom_IIhttp://en.wikipedia.org/wiki/Opteron#Opteron_.2845_nm_SOI.29http://en.wikipedia.org/wiki/Athlon_IIhttp://www.amd.com/us-en/0,,3715_15503,00.html?redir=45nm01http://en.wikipedia.org/wiki/AMD_Turion#Turion_II_Ultrahttp://en.wikipedia.org/wiki/Advanced_Micro_Deviceshttp://en.wikipedia.org/wiki/Phenom_IIhttp://en.wikipedia.org/wiki/Xenon_(processor)http://en.wikipedia.org/wiki/Xbox_360http://en.wikipedia.org/wiki/Cell_Broadband_Enginehttp://en.wikipedia.org/wiki/PlayStation_3#Slim_model


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• Samsung S2EC!!", as known as Hummingbird .

• e@as Instruments $#AE 3 and 1 series.

• I># E$%4: and )!?6

• +uMitsu SEA4C61 VIIIf@ series

• he %ii B JspressoJ I># CEB

C(AE4 9

I4C$C #$=LI' A= AALKSIS I ( #

In this chapter we study the key emerging issues in the domain of interconnect modeling and

analysis. he implications of *arious nanoscale effects on VLSI interconnect performance,

reliabilityN power dissipation and parasitic e@traction are also presented. +inally, promising

new technologies are outlined which ha*e the potential to meet these interconnect challenges

in the nanometer era.

2.1 INTRODUCTION

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As VLSI technology has progressed to pack smaller, faster and increasing number of

transistors doubling e*ery !.< years as per #ooreOs Law- on a single chip than e*er before,

the demands from wires that connect these de*ices ha*e increased tremendously. In fact,

Copper/Lowk interconnect technologies for sub!"" nm C#$S ICs are impacting system

performance through increased power dissipation, signal delay, and crosstalk. %ith clock

fre&uencies increasing into the '() regime, the parasitic resistance, capacitance and

inductance associated with these wires often lead to performance bottlenecks which ha*e led

the semiconductor and the electronic design automation =A- industries to adopt se*eral

technological inno*ations. +urthermore, pre*alent high chip temperatures aggra*ated by

large power dissipation of nanometer scale ICs- and increasing current densities in wires

make electromigration in copper a constant threat to VLSI circuits. #oreo*er, *ariability

issues at the nanometer scale are e*ident in interconnects as they are in de*ices. hus,

interconnects ha*e come to share the centerstage alongside logic de*ices in terms of design

and analysis efforts.

2.2MATERIAL ISSUES

2.2.1COPPERRESISTI#ITY INCREASES AT NM SCALE METAL DIMENSIONS

%ith the aggressi*e scaling of VLSI technology, crosssectional dimensions of onchip

interconnects in current technologies F!G are of the order of the mean free path of electrons in

copper 1" nm at room temperature-. At such dimensions, the increase in Cu interconnect

resisti*ity due to the presence of a highly resisti*e barrier layer which occupies a significant

fraction of the drawn wire width- is further e@acerbated by the increased scattering of

electrons at the surface and grain boundaries F9G. +ig. !a- shows the effecti*e resisti*ity of

Cu interconnects, along with the contributions of different factors for future technology nodes

F3G. A discussion of the models used for these calculations can be found in F9G. It can beobser*ed that the contribution of surface scattering and grain boundary scattering is roughly

the same, but both increases with scaling. he background scattering of the electrons by

phonons, electrons and defects impurities- contributes to the bulk resisti*ity *alue Po- that

remains constant.

2.2.2 THERMAL CONDUCTI#ITY OF LO$ %& DIELECTRIC

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he lowk dielectric materials used for intra and inter metal layer dielectric IL=- in current

VLSI technologies ha*e much lower thermal conducti*ities than silicon dio@ide. +ig. 9.!b-

compares predictions based on the differentialeffecti*emedium =#- and the porosity

weighted simple medium E%S#- models for porous silicate Derogel- films with

e@perimental data for *arious dielectrics from *arious sources in the published literature F3G.

F'(.2.1 )*+ S,*-'n( o me/*- 0e'/''/ o0 /e ITRS 'n/e0me'*/e /'e0 '0e )*/ 377&+ 839.

):+ Co00e-*/'on o /e /e0m*- ,on;,/''/ *n 'e-e,/0', ,on/*n/ o ILD. In/e0


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2.2.3. IMPLICATIONS

2.2.3.1 IMPLICATIONS FOR TEMPERATURE AND RELIAILITY

Alongside the lower thermal conducti*ity of interlayer dielectrics, the scaling of technology

also results in higher current density demands on interconnects F1G. he combined effect of

increasing copper interconnect resisti*ity, decreasing thermal conducti*ity of IL= materials

and rising current densities in onchip wires results in significant rise in interconnect

temperatures, especially at the global metal layers which are furthest away from the heat sink

+ig. 9a--. hese high temperatures will become a maMor concern for interconnect reliability

as the mean time to failure due to electromigration depends e@ponentially on metal

temperature. he ma@imum current density that can be supported by these interconnects will

thus be se*erely limited due to reliability constraints, as shown in +ig. 9.9b- F1G..

2.2.3.2 IMPLICATIONS FOR TEMPERATURE AND PO$ER DISSIPATION

%hile typical local interconnect delay is e@pected to decrease with technology scaling

mainly as a result of the higher packing density of de*ices-, global interconnect delay

increases as seen in +ig. 3a-. In order to keep the delay of global interconnects under control,

repeaters in*erters- are inserted at regular inter*als to dri*e signals faster. As technology

scales, an increasing number of buffers is re&uired for the global interconnection system on a

chip +ig. 9.3b--. hese repeaters can contribute significantly to total chip power dissipation,

which is a critical problem for highperformance ICs .

9


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F'(.2.3 )*+ T=',*- e-* o0 (-o:*- *n -o,*- C; 'n/e0,onne,/ ,om=*0e /o nom'n*-

(*/e e-* 819> * /e,no-o( ,*-e. ):+ N;m:e0 o 0e=e*/e0 'n,0e*e 0*='- '/

/e,no-o( ,*-'n( 8,o;0/e o In/e-9.

F'(. 2.4 )*+ No0m*-'e =oe0 =e0 ;n'/ -en(/ o0 * :;e0e (-o:*- 'n/e0,onne,/

)no0m*-'e /o =oe0 =e0 ;n'/ -en(/ o0 o=/'m*-- :;e0e ,*e+ * * ;n,/'on o e-*

=en*-/ 869. ):+ R*/'o o -o,*- 'n/e0,onne,/ RC e-* )'n,-;'n( 2 ,on/*,/ 2 -o,*- '*+

/o nom'n*- (*/e e-* * =e0 ITRS> * /e,no-o( ,*-e 849.

Increase in effecti*e wire resisti*ity will further increase wire delay resulting in more

numerous repeaters and larger chip power dissipation. (owe*er, it has been shown that when

delay is not of critical importance JpoweroptimalJ repeater insertion F6G can be used toachie*e large power sa*ings. his methodology assumes tremendous importance in the light

of powerlimited technologies of current and future IC generations as the power sa*ings for a

gi*en amount of delay penalty increases as technology scales +ig. 1a--. his is mainly due to

the increasing leakage power dissipation in C#$S de*ices.

#oreo*er, the traditional belief about the decrease in local interconnect delay as a result of

technology scaling also does not remain true for scaled technologies, mainly as a result of the

steep increase in resisti*ity of small dimension local *ias and contacts, which ha*e the

smallest dimensions among all wires on a chip. his effect is e*ident in +ig. 1 b-. It is also

e*ident that the increase in local interconnect delay with scaling is significantly steeper if *ia

and contact- heights are not scaled

2.3 ELECTRICAL ISSUES

Any transient signal carried by an interconnect on a chip, for e@ample, a rising clock edge, is

composed of numerous constituent signals spread across the fre&uency spectrum. he significant

10


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fre&uency the highest fre&uency up to which the amplitude of the corresponding fre&uency

components is significant ; which depends on the signal rise time, is much higher than the fre&uency

of the clock in a digital system as shown in +ig. 9. 2a-. At these fre&uencies, it becomes important to

consider inducti*e effects especially in the unscaled global interconnects F:G. #oreo*er, the skin depth

penetration depth of electromagnetic wa*es- for copper, at these high fre&uencies, is smaller than the

typical crosssectional dimensions of global wires. his, known as the QSkin ffectR, can increase the

effecti*e resistance of wires.

F'(. 2.5 )*+ F0eB;en, ,om=onen/ o * '('/*- #LSI '(n*- */ 'e0en/ /e,no-o(

noe. Te '(n*- 0'e /'me )o:/*'ne 0om SPICE 'm;-*/'on+ *n '(n'',*n/ 0eB;en,

*/ e*, /e,no-o( noe *0e *-o on. ):+ S,em*/', e=',/'n( ,;00en/ en'/

'/0':;/'on ;ne0 'n *n =0o@'m'/ ee,/.

>esides the Skin ffect, the current distribution within the conductors is also altered due to

the presence of pro@imal current carrying conductors at high fre&uencies pro@imity effect-, as

11


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shown schematically in +ig 9.2b-. +ig. 6 shows the impact of these high fre&uency effects

Skin and Ero@imity- on the impedance of a typical interconnect structure as a function of

fre&uency F


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F'(. 2. )*+ In,0e*'n( (*= :e/een =o-'-',on (*/e -en(/ *n -'/o(0*=',

*e-en(/ o0 'e0en/ /e,no-o( noe 8159. ):+ Pe0,en/ *0'*/'on 'n e',e

)#> To@> #T *n Le + *n 'n/e0,onne,/ )$> T> H> + =*0*me/e0 * /e,no-o(

,*-e 8169.

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F'(. 2. Pe0,en/*(e =0e* 'n :;e0e (-o:*- 'n/e0,onne,/ e-* *n -e**(e

=oe0 ''=*/'on o0 'e0en/ =e0,en/*(e *0'*/'on )C*e 1 17J> C*e 2 27J>

C*e 3 37J+ 'n 'e0en/ =*0*me/e0 )# ;==- o-/*(e> L ,*nne- -en(/> T

/em=e0*/;0e> X/- 'n/e0,onne,/ ,0o/*-> 'n/e0,onne,/ '/> / 'n/e0,onne,/

/',ne> 'n/e0


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number and the a*erage lengths of the longest global wires seen in traditional 9= chips by

pro*iding shorter Q*erticalR paths for connection. (owe*er, this technology still needs to

o*ercome difficult challenges such as the thermal management of internal stacked- acti*e

layers, de*elopment of new system architectures and tools, etc. $ptical interconnects F9!G and

radio fre&uency or wireless interconnects F99G are also being considered as alternati*es to

traditional wires for pro*iding chiptochip as well as intrachip communication. heir maMor

benefits are the high propagation speeds and the fact that they are not bandwidth limited like

electrical interconnects. (owe*er, their choice as a replacement technology is limited by the

need for speciali)ed components such as transmitter/recei*er circuits and error correction

circuits which must be placed where*er such interconnects are used.

C*0:on N*no/;:e In/e0,onne,/ Carbon nanotube C- interconnects are possibly the

least disrupti*e of all alternati*es to copper interconnects that ha*e been suggested so far.

Although there are some technological issues that must be resol*ed before C interconnects

can be used in practice, they ha*e the potential to meet interconnect challenges without the

need for paradigm changes in VLSI circuit design techni&ues and tools as in the case of 3=

ICs- or the need for e@tra circuitry as in the case of optical or 4+ interconnects-.

Cs are graphene sheets rolled up into cylinders +ig. !"a-- F93G with diameter of the order

of a nanometer. >ecause of their e@tremely desirable properties of high mechanical and

thermal stability, high thermal conducti*ity and large current carrying capacity F91G, Cs

ha*e aroused a lot of research interest in their applicability as VLSI interconnects of the

future. >undles of metallic singlewalled Cs S%Cs- with electron mean free paths of

the order of a micron are the most suitable candidates for interconnects. +ig. !"bd- shows

different strategies reported in the literature that can potentially be used for forming

interconnects and *ias using carbon nanotube bundles. he performance comparison between

Cu interconnects and interconnects formed from bundles of carbon nanotubes, based on the

performance model described in F9:G, is summari)ed in +ig. !!.

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F'(;0e 2.17 )*+ D'e0en/ ,on'(;0*/'on *n 0e;-/'n( e-e,/0',*- ,on;,/'on /=e o

,*0:on n*no/;:e e=en'n( on /e '0e,/'on *-on( ', /e (0*=ene ee/ *0e 0o--e

;= ),'0*-'/+ 8239. ): , 8259> 8269+.

At the local interconnect le*el, Cbundles do not gi*e much performance impro*ement.

(owe*er, in the case of long intermediate and global interconnects, densely packed C

bundle interconnects show significant impro*ement in performance as compared to copper

interconnects, e*en with imperfect metalnanotube contacts. (ence, if long lengths of densely

packed carbon nanotube bundles with mean free path around !um can be fabricated reliably,

they will pro*ide a *aluable alternati*e to copper interconnections. >esides the performance

benefits of C bundle interconnects, their high thermal conducti*ity makes them *ery

effecti*e in controlling the large backend temperature rise e@pected with metallic

interconnects +ig. 9.!!a--, and hence in impro*ing o*erall interconnect performance and

lifetime F9


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F'(;0e 2.11 R*/'o o 'n/e0,onne,/ =0o=*(*/'on e-* '/ CNT :;n-e 'n/e0,onne,/ /o

/*/ '/ C; '0e o *me 'men'on o0 )*+ -o,*- 'n/e0,onne,/ *n ):+ (-o:*-

'n/e0,onne,/> * * ;n,/'on o 'n/e0,onne,/ -en(/> *n ),+ o0 (-o:*- 'n/e0,onne,/ * *

;n,/'on o CNT me*n 0ee =*/ 82"9.

CHAPTER 3

DESIGN FOR MANUFACTURING

Cooptimi)ation between design and process is re&uired for a highly manufacturable process

technology. his chapter discusses this cooptimi)ation and how it meets the challenges for

maintaining #ooreOs Law while deli*ering new processes and designs capable of fast ramp to

high yields. Eoly is one of the most critical layers for control of *ariation, and it needs the

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most restricti*e rules. %e show the change in poly rules o*er the last few processes to

illustrate how rules ha*e changed to meet manufacturing re&uirements. he *ariation, density,

and yields on the 12nm process show the success of this =esign for #anufacturing =+#-

methodology.

3.1INTRODUCTION

he difficulties in continuing #ooreOs Law with the lack of impro*ement in lithography

resolution are well known F!, 9, 3G. =esign rules ha*e to change and =esign for

#anufacturing =+#- methodology has to continue to impro*e to enable #ooreOs Law

scaling. In this paper we discuss our approach to =+# through cooptimi)ationm across

design and process. %e define the design rules for a new technology early in the definition

process well before the technology de*elopment is complete. his early definition of design

rules allows the design to start in parallel with the technology de*elopment. arly accurate

modeling of the design rules and layout is a key to making this process successful. he design

rules must meet the re&uirements of a highly manufacturable process at the beginning of the

production ramp for the first product.

$ur =+# goals and methodology are different from those of some other manufacturers. he

basic rules for drawing transistors, other layers, and =+# re&uirements are not separate in our

definition process. %e ha*e a few guidelines such as suggesting that designers use redundant

*ias where possible, but most of our =+# re&uirements are included as re&uired rules that all

designs must meet for all layout. Some other companies ha*e simple basic layout rules and

pro*ide other rules that are guidelines or suggestions for changes to layout or design that

would impro*e manufacturability or reduce *ariation. =esigners make tradeoffs for area and

cost to decide if they willimplement these guidelines. Some of their =+# changes are

a*ailable only after analysis of the initial layout. Another difference in our methodology is

that we tend toward adding rules to pre*ent something in layout that might affect design,

instead of depending upon modelling of product layout to find problems. %e build the

re&uirements for manufacturability and low *ariation into the basic design rules as hard

design rule re&uirements.

Eroduct design starts in parallel with technology de*elopment. =esign rules must not be

changed significantly after design work starts. $ur =+# methodology depends upon

modeling to define the rules *ery early in technology de*elopment. herefore, our

methodology ensures that products are ready for rampup in multiple fabs to high*olume and

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highyield manufacturing without changes. his may make our design rules more complicated

than those of some of our competitors, but this methodology ensures that all our

products are capable of high yield when they tape in their first stepping.

Cooptimi)ation across process and design is re&uired to ensure we understand and balance all

re&uirements. >y cooptimi)ing design and process early in the de*elopment cycle, we

arri*ed at a set of design rules that met 12nm process and design re&uirements. he

thoroughness of this early work resulted in these rules being stable through the de*elopment

cycle, which led to the successful insertion of 12nm technology in high*olume

manufacturing, ensuring the continued march of #ooreOs Law.

he poly layer is the most critical layer for control of *ariation. =ue to this need to control

*ariation, the poly layer was the first layer on which restricti*e design rules were used. %e

need to build the re&uirements for minimi)ing *ariation into the rules. (ow the rules ha*e

changed for the poly layer shows how designs ha*e changed. he analysis of the impact of

changes in the poly rule shows how we consider design and process needs in defining design

rules.

3.2 DESIGN FOR MANUFACTURING GOALS

he first re&uirement for a new technology is the continuation of #ooreOs Law. A new

technology should ha*e twice the number of transistors. his is increasingly difficult with the

lack of impro*ement in wa*e length for lithography and in transistor scaling issues. eeping

manufacturing *ariation in check as we impro*e transistor density is a scaling challenge as

discussed in many papers and conferences F1, 2G. ransistor channel length is a maMor focus

for controlling manufacturing *ariation. he *ariation must scale with the poly pitch for the

new process

. he second re&uirement of a new technology is the ability to ramp *ery &uickly to high

*olume with multiple designs in multiple fabs. he design and process ha*e to be

manufacturable at the beginning of the ramp. =esign rules ha*e to be defined early in the

process de*elopment work to allow product design to be done in parallel with the process

de*elopment. here must be no maMor changes to design rules late in process de*elopment or

during manufacturing ramp. Eredicti*e modeling of the rules must be done well before

process de*elopment is complete. he design rules may be conser*ati*e, to ensure that the

design is *ery robust, but they should not be too conser*ati*e, to ensure that we deri*e the

ma@imum benefit from #ooreOs Law scaling. he challenge is in defining this optimum

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robustness. he third re&uirement of a new technology is for its yields to be as good as, or

better than, the pre*iousgenerationtechnologyN and for its learning cur*e to be as fast as, or

faster than, the pre*iousgeneration technology. udgment is re&uired to define the technology

to strike the right balance between the difficulty of the technology and the impact of the =+#

re&uirements on the design. Some breakthroughs may be re&uired to meet design

re&uirements, but these cannot be so difficult that they slow the yield learning goal.

3.3 CO


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design. A solution with no impact is notpossible, howe*er. he need for low costs may result

in changes in design rules for smaller die si)e or better yields to offset concerns about

increased design effort. udgment about manufacturability will take priority o*er

concernsabout increased work for designers.

3.4 DESIGN RULE DEFINITION

#odeling is the cornerstone of todayOs design rule definition process. >uilding predicti*e

models for the new technology is one of the challenges for a new technology.he rule

definition work is frontloaded, with the rules defined before technology de*elopment is

complete. +igure 3.! shows the elements of the design rule definitionErocess

F'(;0e 3.1 De'(n 0;-e e'n'/'on

he transistor density scaling goal dri*es the != pitch re&uirement for the key layers like poly

and #etal! #!-. his != pitch must scale by ".:D per process generation. 9= rules such as

line endtoend space or minimum line length can be more difficult to scale than the != rules.

Isolated and wide lines may ha*e scaling problems. he techni&ues needed to meet the !=

scaling re&uirements may make scaling the 9= rules more difficult. A change in illumination

technology to get good minimum line width and minimum space may not allow the same

scaling of rules for wider lines, or it may make scaling of rules different for D and K

directions. =esign rules are not changed after the beginning of manufacturing ramp. Learning

about difficult process issues feeds forward into the design rule definition of the new process.

Some design guidelines on pre*ious technology may become hard rules on the new

technology. Some structures that caused significant process problems and/or re&uired

significant process changes may be eliminated by new rules. =e*ice or interconnect models

may be simplified by the elimination of parametric *ariables caused by simplified design

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rules. #odeling of design rules starts with e@trapolation of $EC models from the pre*ious

technology. ew lithography tools, illumination techni&ues, enhancement techni&ues,

and resists are e*aluated to determine the best method for != scaling, and to understand the

changes needed in other rules. Learning about the capabilities of the new tools is a

continuous process during rule definition. ypical and worstcase layout topologies are

analy)ed to e*aluate process issues like #ask rror nhancement +actor #+- and depth

of focus. est reticules are created to calibrate the models. Cell studies are done using the

rules generated from the modeling studies. =ata are e@tracted from designs on older

technologies to understand the re&uirements for critical layouts and how rule changes might

affect design. Standard logic cells, register files, S4A# bits, and metal routing are all

included in the layout studies. As rules mature, product groups are included in the e*aluation.

*aluation of the patterning capabilities and the impact on layout is a continuous and iterati*e

process until rules are final. Important layout topologies identified by design are analy)ed by

using the models, and they are included in new test reticules. =esign rules that limit meeting

the transistor density goals are e*aluated with the models to understand if rules need to be

changed or impro*ed. +igure 3.9 shows a typical simulation from a study of a design rule.

his simulation studied the process margin for line endtoend space as a function of line

length. A high #+ is an indication of poor process control. Some line lengths ha*e

insufficient control of the endofline space.

his can create linetoline shorts. $ne option to fi@ this would be to change the illumination

as shown by the different lines on the graph. Another option would be to create a design rule

that does not allow line lengths of ".9 to ".3u. If a rule change is proposed, cell layouts are

done with the new rules to understand the impact on transistor design. A study may be done

on data from designs on pre*ious processes to determine if the design rule being changed is

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commonly used. If the rule change is shown to cause a significant change in area, we would

consider other pattering solutions.

F'(;0e 3.2 Len(/ . MEEF

he main process de*elopment *ehicle is the Dchip test *ehicle that includes large S4A#

designs, process and design test structures, and processsensiti*e circuits. here are earlier

mask sets that include some of the rules and features of the new process, but the Dchip is the

first mask set that has large circuit blocks with all of the rules. he processing of the test chip

is used to *alidate the rules, not define the rules. here may be a few changes in rules

depending on what we learn from the test chip. he number of rules that are added or changed

ha*e to be limited, because product designs will ha*e started before the test chip is processed.

As the de*elopment process continues, the Mustification for design rule changes

becomes more difficult. >y the time production starts, a design rule problem has to be fi@ed

by process unless it is impossible to fi@ that way.

+igure 3 shows our trend in the number of rules o*er time for the 12nm process. he timeline

is relati*e to tapeout of first design on the technology. In addition to added new rules, therewere some minor changes for better and worse rule *alues. he number of rules increased

during the design and layout of the test chip as the modeling work continued and $EC flows

were de*eloped. here was a small increase in the number of rules after processing of the test

chip. hese changes were not all due to patterning issues. ew understanding of the transistor

of metal processing can create the need for new rules. >y the time masks were created for the

first product, the rules were stable. here were only a few changes in design rules after the

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first design started. he 12nm rule stability was good, but there were more changes than

desired. $n the 39nm process we had fewer changes during the test chip design and after the

start of the first product. Erocess de*elopment continued during debug of the first design,

but the rules did not change during this time. Erocess impro*ement continues through the life

of the process to reduce defect density, and cost, but this is done without changing design

rules.

F'(;0e 3.3 C*n(e 'n n;m:e0 o =o- 0;-e

3.5 E#OLUTION OF POLY RULES

he poly layer is one of the most difficult layers to pattern and process. Control of poly C= isone the most critical re&uirements in the process, due to its affect on transistor performance

and *ariation. Eoly C= control must scale for the new technology to keep the percentage

*ariation of the channel length constant. Contacted gate pitch is a big factor in S4A# cell

area and logic transistor density. hese critical re&uirements make poly the first layer to need

new pattering solutions and design rules. In the following sections, we show how poly design

rules ha*e changed o*er the last few processes and how =+# methodology has e*ol*ed and

has been used in the definition work.

3.5.1 137nm P0o,e

$ur !3"nm process had simple rules. here was limited early modeling of layout. Layout had

random combinations of poly widths, spaces, and de*ice orientation. Eroducts had some

issues with poly corner rounding that affected small de*ices. his issue was helped by =+#

guidelines for layout of small de*ices, but the guidelines came after initial design of lead

products. here was limited in*ol*ement from product design engineers in the early design

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rule definition. 4ule definition was primarily simple scaling of rules from pre*ious

technology generations.

3.5.2 7nm P0o,e

he ?"nm process included more restrictions for poly layout, and the number of poly rulesincreased by 1:. All de*ices had to be in the same orientation e@cept for the memory bits.

he difference in printing of shapes parallel and orthogonal to the scan direction was one

reason for this change. Eolyo*erfieldrouting was allowed in the D or K orientation. he

memory bit shown in +igure 3.1 is a uni&ue topology with transistors in both orientations that

could be modeled and characteri)ed to account for any difference due to de*ice orientation.

Eoly corner rounding and modeling were analy)ed and modelled early in the definition

process.

F'(;0e 3.4 7nm SRAM :'/ -*o;/

he main design impact of the onede*ice orientation is that a block of layout cannot be

placed in two orientations, rotated ?"T. I/$ buffers on the top and right edges for the die mustha*e uni&ue layouts, e*en if circuits are identical. his added some layout effort, but had no

affect on die si)e. Since there was no die si)e impact, the rule change was a better solution for

random layout than trying to model differences due to de*ice orientation, as was done for the

memory bit.

3.5.3 65nm P0o,e

he number of poly rules increased by 62 for the 62nm process, and rules were more

complicated. 4ules changed to allow the use of phase shift masks. All de*ices including thememory bit had de*ices in one orientation as shown in +igure 3.2. his layout is almost ideal

for patterning with simple rectangular shapes on all layers

F'(;0e 3.5 65nm SRAM

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here were differences in poly layout rules based upon pitch and poly space and orientation.

he comple@ rules had little effect on transistor density. #any of the new rules affected

special cases that did not occur often or were easy to fi@. +or e@ample, layout of a minimum

width de*ice has some new rules for endcap, but design did not use a lot of minimum width

de*ices. %here they were used, the end cap rules were usually easy to meet due to area being

limited by other rules. Cell layout studies and modeling of layout increased for this generation

for worstcase structures. he layout was random and it was difficult to determine all worst

case layouts.

3.5.4 45nm P0o,e

#eeting the transistor density and process re&uirements of the 12nm technology re&uired

significant changes in design rules. he high metal gate transistors on this technology are

the biggest change in transistors in 1" years F6G. !?3nm patterning tools were needed to

minimi)e cost and risk. Eoly had to be printed using !?3nm dry tools and still had to meet our

need for ".:D scaling of the pitch. Variation could not increase. he early modeling work

increased significantly from the 62nm process. his included earlier in*ol*ement of the $EC

e@perts in the designrule definition and e*aluation phases. $ur goal was a more

comprehensi*e e*aluation of rules and layout topologies through modeling. here were some

changes in poly layout on the ?"nm and 62nm process, but the layout has remained *ery

random. =esign could ha*e used any poly pitch 5U minimum pitch, and any channel length

5Uminimum was allowed. he different channel lengths could be randomly mi@ed.

ransistors were in one orientation, but poly routing could be in either orientation. Corner

rounding of poly close to de*ices could impact transistor performance. arly in the definition

work we asked if poly patterning in logic could be similar to the poly patterning in the S4A#

bit introduced in the 62nm generation. $ne of the big concerns for making poly layout more

regular was limiting the channel layout choices a*ailable to design. =esign had always had

few restrictions on the channel lengths. %e wondered if this freedom was necessary. +igure

3.6 shows the channel lengths used in one 62nm design. #ost of the de*ices at ".!"u and

".!!u are in the S4A# bits. he few de*ices at longer channel lengths were primarily in

analog and I/$ circuits. ?? of the de*ices in random logic had minimum channel length or

minimum ."!u. he main reason for using longer channel length in logic was to reduce

de*ice leakage. Channel lengths can be limited in logic as long as there are options for low

leakage de*ices.

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=e*ice leakage is strongly dependent upon Le, so a *ery small change in Le can reduce

leakage by 3D. (igher *oltage can also be used to reduce leakage. here were some circuits

where a longer Le de*ice had to be replaced by two or more minimum channel length de*ices.

>ased on analysis of data like this and other layout studies, the design was partitioned into

three groupsW logic, analog, and S4A#. Analog and S4A# are treated as special cases.

F'(;0e 3.6 P0o;,/ ,*nne- -en(/ on 65nm e'(n

F'(;0e 3." 45nm SRAM *n -o(', =o- -*o;/

he 12nm process has trench contactedbased local routing. his eliminated the need to use

poly routing orthogonal to the transistor gate and the wide poly used for poly contacts. Layout

studies were done to understand if one poly pitch was possible and how this affected rules for

other layers. he local routing and limitations on transistor channel length had allowed logic

poly layout to be one pitch and one direction as shown in +igure 3.:. he number of layout

rules for logic layout was reduced by 3:. his reduction is not large, as the simple layout

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might indicate, because the poly rules include rules for poly spacing to other layers, and there

are se*eral rules for endcaps and poly endtoend.

3.6 OTHER LAYERS

he regular layout for poly also simplified patterning of contacts and #!. he contact pitch is

the same as the gate pitch. #! parallel to the gates has the same minimum pitch as poly.

Very restricti*e rules similar to poly rules were not needed to meet process or patterning

re&uirements for other layers, but the rules for some other layers are comple@. he metal pitch

choices do not need to be as restricti*e as the poly layer pitches, since metal *ariation

re&uirement is not as tight. he metal *ariation has less impact upon path delay than the poly

C= *ariation. #etal layer design rules ha*e some types of design rule restrictions used on

poly layers on pre*ious technologies. Erinting of isolated metal lines was one of the issues on

12nm technology. 4ules were added to restrict the use of isolated lines. Eroduct layout uses

se*eral metal widths and a range of spaces. It is difficult to limit the width and pitch choices

for metal, due to the need for wide lines and spaces to optimi)e 4C delays, capacitance, and

power deli*ery. CA= tools must change to support the changes in metal rules. $ne of the

learnings from the 12nm technology was that the CA= tool work needs to start earlier.

3." 45NM MANUFACTURAILITY

3.".1 STANDARED CELL AREA SCALLING

he first goal for any new process is to maintain the transistor density scaling trend. +igure <

shows the standard cell area scaling trend. his analysis used a large standard cell library from

our microprocessor designs and is weighted by typical cell usage. ransistor density

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scaling has followed the ".2D density impro*ement per process generation. he 12nm process

meets this trend despite the change to more complicated and restricti*e design rules.

F'(;0e 3. S/*n*0 ,e-- en'/

F'(;0e 3. $'/'n *e0 *0'*/'on o o,'--*/o0 0eB;en, o0 /e 137nm /0o;( 45nm

/e,no-o( (ene0*/'on

3.".2 #ARIATION

$ne of the re&uirements for poly patterning is scaling of *ariation. +igure 3.? shows the

within wafer *ariation of oscillator fre&uency for the !3"nm through 12nm generations. he

*ariation in fre&uency has remained at less than 3. his fre&uency *ariation includes the

affects of poly C=, V, and other sources of de*ice *ariation. Variation has scaled with the

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decreasing poly pitch, despite the changes to new transistors, changes in poly patterning, and

de*ice si)es.

3.".3YIELD LEARNING

he final measure of success of =+# is process yield. $ur yield learning trend history isshown in +igure 3.!". he yield learning rate on 12nm technology is as fast as pre*ious

processes and is trending toward lower defect density than the 62nm process. here is no way

to measure how the =+# rules contributed to this learning. =esign rules, process definition,

process tools, and many other things affect the yield learning rate and final high *olume

manufacturing yields. All of these things are necessary to meet the manufacturing goals.

F'(;0e 3.17 Y'e- /0en

CHAPTER 4

TRANSISTOR RELIAILITY

It has been clear for a number of years that increasing transistor gate leakage with de*ice

scaling would ultimately necessitate an alternati*e to traditional Si$ dielectrics with

polysilicon gates. #aterial systems pro*iding higher dielectric constants, and therefore

allowing physically thicker dielectrics, ha*e been the obMect of e@tensi*e research. Such high

k dielectrics, when combined with metal gate electrodes, ha*e emerged as the leading

alternati*e, demonstrating good transistor performance and offering reductions in gate leakage

of 92D!""D. Achie*ing the re&uired reliability, particularly at the high operating electric

fields at which the performance ad*antages are reali)ed, howe*er, pro*ed much more

difficult. Intel stro*e to o*ercome the reliability obstacles by introducing highk dielectrics

combined with metal gate electrodes (#'- transistors in its 12nm logic process, as it

Mudged the transition to this technology would pro*ide compelling performance ad*antages. In

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this chapter we discuss the general considerations for the reliability of (#' transistors

and specifically we discuss what was achie*ed with IntelOs 12nm process technology.

A particularly e@tensi*e effort was undertaken to characteri)e the reliability physics of this

re*olutionary new transistor and to gather the data to ensure accurate modeling of failure

rates. his entailed accelerated testing and fully integrated test *ehicles, representing o*er

se*en orders of magnitude in the transistor area, at a *ariety of stress conditions, some of

which lasted o*er three months.

he intrinsic transistor reliability fail modes addressed in this paper fall into two basic classes.

+irst we ha*e the integrity of the transistor dielectric itself, which in the course of operation,

can fail, a phenomenon typically referred to as ime =ependent =ielectric >reakdown

==>-. he transistor must be engineered to ensure that components donOt wear out within

their operating lifetimes.

Second, in addition to abrupt failure of the dielectric, transistors can also e@perience

progressi*e parametric degradation. he primary parametric reliability mode for traditional

Si$based transistors is a slowdown of the E#$S de*ices due to progressi*e trapping of

charge, typically referred to as >ias emp Instability >I-. +or (based dielectrics, at their

higher target operating fields, similar degradation is obser*ed on #$S transistors as well as

potentially significant increases in gate leakage with stress, known as Stress Induced Leakage

Current SILC-.

%e discuss these reliability phenomena and illustrate that while they pose large reliability

challenges for (#', these challenges can be o*ercome through refinement of process

architecture and optimi)ation of processing conditions. IntelOs 12nm technology is shown to

achie*e intrinsic ==> and aggregate E- >I performance e&ui*alent to its 62nm

predecessor with negligible SILC at its 3" higher operating electric fields.

4.1 PROCESS AC&GROUND

he 12nm highk dielectrics combined with metal gate electrodes (#'- transistors

studied in this work ha*e a (afniumbased gate dielectric and dual workfunction metal gate

electrodes for #$S and E#$S. he transistor fabrication utili)es a ( first and #' last

process as detailed in F!G. In this flow, ( is deposited using an Atomic Layer =eposition

AL=- process, and polysilicon is used for the gate patterning. After the Interconnect

=ielectric deposition, a polish step e@poses poly gates, and the dummy poly is remo*ed.

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hen, workfunction metal electrodes are deposited followed by a gate fill process. he Si$9

e&ui*alent o@ide thickness $- of the ( plus the Interface Layer IL- that forms between

the ( and the silicon is X!."nm. +igure 1.! describes the gate stack, with its Si$9like

interface layer IL- and the ( dielectric proper.

F'(;0e 4.1 TEM o H'(


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F'(;0e 4.3 G*/e E-e,/0', 'e- 'n,0e*e . /e,no-o( noe. Te *e0*(e E


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F'(;0e 4.4 PMOS NTI . T'me '--;/0*/'n( :o/ e(0**/'on *n 0e,oe0

E#$S >I is recogni)ed in the industry as a maMor reliability mechanism in ad*anced logic

technologies. =egradation of ma@imum operating +re&uency +ma@- and circuit margin, in

particular at #inimum $perating Voltage Vmin-, must be addressed within product design

and testing to ensure an ade&uate margin to specifications o*er operating lifetimes. A

particularly important circuit case is S4A# memory. ransistors within the S4A# cells are

typically amongst the smallest within a technology, and the S4A# Static oise #argin

S#- is highly sensiti*e to de*ice mismatch. he scaling of S4A# memory arrays has

increased the sensiti*ity to >Iinduced transistor VT mismatch, which can degrade Vmin

characteristics o*er time. 6 S4A# cell area has traditionally reduced 9D e*ery two years, as

shown in +igure 1.2, which means bit counts are also increasing at a corresponding rate

F'(;0e 4.5 6T SRAM ,e-- 'e ,*-'n( /0en o'n( 2X ,e-- *0e* ,*-'n( ee0 /o e*0

+igure 1.6 shows an e@ample of Vmin dependence on the S4A# cache array si)e. >oth the

magnitude of Vmin and the Vmin spread increase with cache array si)e due to transistor

*ariations. hus, understanding de*ice *ariability at both time " and o*er time, gi*en >I

effects, has become increasingly important with cache cell/array si)e scaling.

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F'(;0e 4.6 #m'n e=enen,e on ,*,e *00* 'e o0 6I e@perimental data collection

was undertaken in the de*elopment of IntelOs 12nm (#' transistor technology to support

reliability modeling and process optimi)ation work. A summary of these results and a

discussion of the mechanisms responsible for >I in (#' transistors are presented below.%e demonstrate that, with appropriate transistor architecture and processing, net >I

degradation that is comparable to, or better than, that obser*ed with traditional Si$

dielectrics, can be achie*ed for (#' dielectrics operating at X3" higher fields.

4.3 GATE DIELECTRIC REA&DO$N> TIME %DEPENDENT

DIELECTRIC REA&DO$N STRESS % INDUCED Le**(e C;00en/

he transistor gate dielectric pro*ides isolation of the gate electrode from the conducting

channel, pro*iding the high input impedance of C#$S transistors. he reliability of the gate

is, therefore, of primary importance in transistor reliability. #ultiple e*aluation techni&ues

e@ist for assessment of gate dielectric integrity, with ime =ependent =ielectric >reakdown

==>- testing being the standard methodology for de*eloping operating lifetime reliability

proMections. ==> characteri)ation is performed with ele*ated *oltage and temperature, with

either constant *oltage CVS- or constant current CCS- on transistors or capacitors, until a

failure is obser*ed. +ailure is typically based on an increase in gate current Ig, but definitions

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*ary and can significantly impact proMections. ==> can occur on #$S and E#$S under

all operating bias conditions in*ersion, accumulation-N howe*er, the rate of dielectric damage

is *ery strongly modulated by the band structure of the material system and, traditionally,

#$S in in*ersion mode tends to be the limiter for ==> lifetime. Although there is no

rigid consensus in the literature on the e@act physical mechanisms that dominate gate

dielectric breakdown, it is generally attributed to a combination of se*eral mechanismsY

charge inMection, interface, bulk trap state generation, and trapassisted conduction. =uring

operation, the electric field across the gate dielectric causes the generation of electrical defects

or Qtraps.R hese traps modify the local electric field and

enhance leakage current in the dielectric through *arious hopping and tunneling processes.

%ith cumulati*e stress, more trap states are created and, conse&uently, a gradual increase of

the gate current is obser*edW this is known as Stress Induced Leakage Current SILC-

degradation. *entually, a point is reached where a conducti*e QchainR of traps is established

between the cathode and the anode as depicted in +igure 1.:.

F'(;0e 4." Pe0,o-*/'on Teo0 e,0':e /0*= * =e0e o 0*'; 0. ,om=-e/e ,*'n

0om *noe /o ,*/oe> :0e*on )D+ o,,;0. Te /'nne0 /e 'e-e,/0',> /e ee0 /e

/0*= neee /o ,*;e D 8129.

he use of (#' stacks to o*ercome scaling limitations of con*entional Si$9 dielectrics

introduces additional comple@ities in the form of materials, band structure, and interfaces that

can significantly impact the ==> mechanics and performance. Eroblematic ( dielectric

lifetimes. #onitoring of the gate leakage was performed by interrupting the stress with

negligible measurement delay between stress and measurement. Care was taken to ensure that

the measurement phase did not result in additional trap creation or degradation. he monitor

measurements were conducted at two bias conditions corresponding to nominal and low

*oltage of operating conditions of products. he results focus on reliability of the optimi)ed

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process flow, referred to as Final, but the affects of process optimi)ations are illustrated with

results of material from early unoptimi)ed process architectures and flows, referred to as

Initial. 4esults for IntelOs 62nm process are also referenced as benchmarks for mature ultra

thin Si$EolySi de*ices F9G.. he S4A# cache data reported here were collected on a fully

integrated 1.2#bit cache array. Acceleration factors were e@tracted through such testing to

understand the sensiti*ity of the ==> lifetimes to *oltage and temperature. o minimi)e the

e@trapolation uncertainties in ==> models, large sample si)es were accumulated at multiple

stress condition combinations on test structures with a gate area range of o*er se*en decades.

It will be demonstrated that, with an optimi)ed transistor architecture and process flow,

dielectric reliability comparable to that obtained on traditional Si$ dielectrics can be

achie*ed for (#' dielectrics operating at X3" higher fields with negligible SILC

prior to breakdown.

4.4 IN PROCESS CHARGING

It is well understood in the industry that dielectric &uality as well as transistor parametric

characteristics can be degraded due to processcharging induced damage from plasma

processes within the fabrication flow. he charge that may accumulate on interconnect

ZantennaeO connected to transistor gates in the course of these processes can result in

sufficiently high stress to induce unreco*erable changes to the transistor characteristics, or in

e@treme cases, e*en catastrophic de*ice damage. he standard approach to protect against

such plasmainduced damage is to pro*ide a discharge path in the form of diodes or

transistors. he protection needs are a function of the specific antennae connected to a de*ice

as well as the intrinsic leakage of the transistor and the charging characteristics of the

fabrication processes. =esign rules are defined to ensure sufficient protection to pre*ent any

transistor damage during processing.

Erocess charging is one concern that has benefited from traditional dielectric scalingN

increases in gate o@ide leakage ha*e made ultra thin Si$9 dielectrics less susceptible to

damage. %ith the large reduction in gate leakage that ( dielectrics pro*ide, the charging

rules must therefore be tightened to more historical le*els.

4.5 RESULTS

4.5.1INTRODUCTION YO RELIAILITY RESULTS

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he results of reliability characteri)ations of IntelOs 12nm (#' process are presented

below. he first two sections address degradation of the gate dielectric considering

progressi*e increases in leakage current or SILC and dielectric breakdown. he third section

considers degradation in transistor operating characteristics due to charge trapping within the

bulk of the dielectric or at interfaces within the stack. he results reported here are for de*ices

with the process minimum drawnO channel lengths of X1"nm, but de*ices spanning

the permitted layout range were e*aluated with similar results. Bnless stated otherwise, the

data below are for de*ices on the optimi)ed 12nm (#' process flow comparati*e

4.5.2 DIELICTRIC RELIAILATY

ransistor dielectric reliability was assessed for a wide range of transistor structures ranging

from single cache bitcell transistors to 1.2#b S4A# cache test *ehicles. Con*entional CVS

was employed unless otherwise indicated.

4.5.3 DIELICTRIC RELIAILATY TDD

==> is associated with a substantial increase in current through the transistor dielectric. In

the data below, the definition of failure for e@traction of ==> lifetimes is the point where an

abrupt increase in dielectric current is obser*ed or a Qhard breakdownR (>=- occurs.. +igure

1.< compares matched lectric field ==> on Si$EolySi *s. the optimi)ed Intel 12nm

(#' gate F!2G.

F'(;

0e 4. TDD . E-e,/0', 'e- ,om=*0'on o H&MG 819 *n S'ON 829 o'n( /*/ *no=/'m'e H&MG 'e-e,/0', ,*n ;==o0/ 37J '(e0 'e- /*n * m*/;0e S'ON lifetime data collected on the Final optimi)ed process

o*er a much greater rangeW more than 6 #V/cm and more than se*en orders of magnitude in

time. ote, the data e@hibit a clear transition in the acceleration beha*ior that occurs at

X!9#V/cm.

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F'(;0e 4. Lon(

*00* ,e-- *n 4.5M: SRAM ,*,e /e/ e',-e emon/0*/'n( ,on'/en/ TDD ,*-'n(

'/ (*/e *0e* oe0 * 0*n(e o e'(/ e,*e

4.5.4 DIELICTRIC RELIAILATYSTRESS INDUCED LEA&AGE

ransistor dielectrics can e@hibit intrinsic increases in gate leakage prior to dielectric

breakdown that may be large enough in aggregate to noticeably degrade the static power of an

IC e*en where there is no impact on circuit functionality or performance. As discussed

pre*iously, this SILC effect has been reported to be a maMor concern for ( dielectrics.

+igure 1.!! compares early time e*olution of Ig under in*ersion stress of #$S de*ices

fabricated with an early, unoptimi)ed 12nm (#' process flow to that of material from the

Final optimi)ed process flow and for a con*entional Si$ stack.

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F'(;0e 4.11. SILC e(0**/'on on In'/'*- . F'n*- =0o,e -o emon/0*/e

'm=0oemen/ /0o;( =0o,e o=/'m'*/'on. Te S'O2 ,*e ' on o0 0ee0en,e *n

e@':'/ 0e-*/'e- ne(-'(':-e SILC e(0**/'on * e@=e,/e. Te F'n*- =0o,e e@':'/

'm'-*0 -ee- o SILC e(0**/'on * o:e0e on /e S'O2 0ee0en,e.

4.5.5 TRANSISTOR DEGRATION IAS TEMP INSTAILITY )TI+

>ias emp Instability >I- degradation of 12nm (#' transistors was studied o*er a

range of bias and temperature conditions to allow models to be generated and to pro*ide

insight into the physical mechanisms and processing interactions. =uring stress, the transistor

gates were biased at either positi*e or negati*e polarity while all other terminals were

grounded. VT was measured using 2"mV on the drain. he time e*olution of degradation in

transistor dri*e Idsat- for 12nm (#' #$S and E#$S de*ices at accelerated in*ersion

stress conditions is shown in +igure 1.!9.

F'(;0e 4.12 )*+ NMOS PTI /'me e=enen,e. ):+ PMOS NTI /'me e=enen,e o

H&MG /0*n'/o0. T0*n'/o0 *0e 0*n */ $L7.;m7.74;m o0

H&MG =0o,e. Po-S'ON *e $L1;m7.74;m 0*n 'men'on.

Characteri)ation of transistor degradation under =C stresses o*er a range of temperatures

from 6"TC to !!"TC shows Arrhenius time dependence as shown in +igure 1.!3W ime to

gi*en +[VT - X e a/k with a X .:eV for E#$SN #$S shows a lower temperature

dependence of X.16 eV.

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F'(;0e 4.13 NMOS PTI *n PMOS NTI *,/'*/'on ene0( )E*+

+igures 1.!1 and 1.!2 show the dependence of >ias temp Vt degradation on the applied

electrical field for E#$S and #$S de*ices, respecti*ely, as well as comparati*e results for

IntelOs 62nm Si$9 technology.

F'(;0e 4.14 PMOS NTI VT '/ . E-e,/0', 'e-

F'(;0e 4.15 NMOS PTI VT '/ . E-e,/0', 'e-

ransistor ranconductance Gm- can pro*ide useful insights into the nature of the >I

degradation mechanisms. +igure 1.!6 shows the correlation of degradation in Gm to that of

VT , comparing an unoptimi)ed ( film stack from the early de*elopment stage Initial and the

optimi)ed Final process. ote that VT shift is well correlated to the Gm degradation for

both #$S and E#$S for the Initial ( process, while it only correlates well to the E#$S

on the Final ( process.

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F'(;0e 4.16 NMOS *n PMOS TI VT '/ . J Gm e(0**/'on on )*+ In'/'*-

=0o,e . ):+ F'n*- 45nm H&MG =0o,e.

. +igure 1.!:a- shows representati*e 12nm (#' 4$ degradation data with a time slope

of X.9 as e@pected from de*icele*el >I. +igure 1.!:b- shows the 4$ stress data *s. discrete

transistor results showing *ery good agreement..

F'(;0e 4.1" )*+ R'n( O,'--*/o0 )RO+ e(0**/'on ):+ RO /0e */* *(*'n/ TI moe-

:*e on ',0e/e /0*n'/o0

4.5.6 TRANSISTOR DEGRATION FAST TRAPS

Another manifestation of degradation in transistor characteristics due to charge trapping is

rapid shifting in de*ice thresholds upon application of bias. his effect is of particular concern

for ( dielectrics. IntelOs optimi)ed 12nm (#' process has negligible fast trapping, but

the following comparison to early de*elopment process re*isions illustrate that this is a

potential area of concernW +igure 1.!< compares #$S >I VT shift o*er time for the Initial

and Final (#' processes. ote the *ery large, increase in VT \! sec. and the relati*e lack

of dependence of VT degradation on stress *oltage for the Initial process compared to the

mature Final process.

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F'(;0e 4.1 NMOS PTI VT '/ o0 In'/'*- *n F'n*-H&MG =0o,e

4.5." TRANSISTOR DEGRATIONHOT CARRIER

InMection of hot carriers can result in degradation in VT and Gm. he low conduction band

offset for (fbased ( dielectric in contact with a silicon substrate results in a reduced

barrier, and it has been suggested in the literature that this poses a potentially increased risk

for the hot carrier inMection F!:G. +igure 1.!? shows #$S hot electron reliability comparison

between IntelOs 12nm (#' and 62nm Eoly/Si$ transistors F9G. he 12nm (#'

transistors actually show a large impro*ement in lifetime 5:D at same Isub- relati*e to 62nm.

F'(;0

e 4.1 NMOS o/ e-e,/0on =e0o0m*n,e o 45nm H&MG *n 65nm Po-S'ON

/0*n'/o0

4.6 PROCESS CHARGING

Assessment of process charging damage was conducted using speciali)ed test structures with

antennae connected to the gate of Z*ictimO transistors with *arying le*els of charging

protection. he complete structure set e@tends beyond that allowed within the process design

rules. ransistor parametric characteristics at the completion of processing are monitored on

these structures, and transistor reliability stresses are conducted and compared to reference

de*ices with no antennae. hese results confirm no charging degradation on de*ices

compliant to design rule protection re&uirements.

4." DISCUSSION

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==> results show that IntelOs 12nm (#' transistor deli*ers e&ui*alent dielectric

lifetimes for #$S de*ices at a 3" higher electric field. =ue to the band offsets, E#$S

==> has much higher margins. Con*entional 'ate $@ide '$D- modeling formulations are

largely applicable to these de*icesN howe*er, the dependence of + on the applied electric

field is not a constant e@ponentialW the high field regime, abo*e X!9#V/cm, e@hibits a

shallower acceleration slope. his acceleration factor change is obser*ed to occur at an efield

*alue similar to the point of transition in gate leakage from a direct tunneling =- regime to a

+owlerordheim tunneling +- regime, as shown in +igure 1.9".

F'(;0e 4.27. Le/ =-o/ o (*/e -e**(e . :'* o0 H&MG 819 . S'ON 829. A/ '(e0

#G *-;e> DT -e**(e /0o;( S'ON om'n*/e /e ne/ -e**(e> :;/ */ -oe0 :'*e>

-e**(e /0o;( /e H&MG /*, 0o= o 0*='- ;e /o DT /0o;( /e H& -*e0.

R'(/ =-o/ o DT /o FN /0*n'/'on o,,;0 'n /e H&MG /*, */ #G1.5# )/0'*n(-e

*0e e-/* 0om '/ /o *,/;*- -o=e /0*n'/'on e@/0*,/e */ e-/* 7+.

Such a change in the tunneling mechanism is e@pected for bilayer dielectric stacks and has

been predicted for (#' by =unga et al. (owe*er, *ery limited data e@ists in the literature

for such low *oltage ==> data on (#' stacks. +or the Intel (#' process, CVS data

were collected spanning the low and highfield regimesYwith total stress times e@ceeding

three months duration to pro*ide good resolution. he field dependence was found to follow

an e@p- relation in the lowfield regime, and an e@p!/- relation in the highfield regime,

consistent with the results of (u et al. and #cEherson et al. F9", 9!G. (owe*er proper

characteri)ation across this range assumes fundamental importance for (#' where the

typical operating and transistor characteri)ation field span this transition.

he ==> area scaling for IntelOs 12nm (#' follows the con*entional %eibull

formulation. he ] is in line with e@pectations for the thickness of the gate stack and the good

agreement of the model out to productlike areas demonstrates an absence of ZdefectO ==>

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concerns on the Final optimi)ed process flow. he >I results show that with sufficient

optimi)ation, aggregate #$SE#$S degradation le*els e&ui*alent to those achie*ed on

Si$9 can be achie*ed on (#' operating at 3" higher fields. +or the final process,

E#$S >I is matched at 2" higher field, and the E#$S degradation beha*ior on IntelOs

12nm (#' process is found to be *ery similar to that obser*ed on con*entional Si$

with e&ui*alent acceleration and time dependence. he correlation of Gm and VT shifts, the

polarity of the VT shift and charge pumping, and reco*ery data not shown- all support that

E#$S >I is similarly dri*en by positi*e charge trapping near the Si/dielectric interface

=it-. Eb Si( dangling bonds at the interface- defects ha*e been proposed for the E#$S IL

degradation in >I stress F99G.

$n the other hand, the data show that #$S >I is largely dri*en by electron trapping within

the ( bulk on the optimi)ed process with additional contribution from interface traps on the

Initial process. his e@plains the lack of #$S Gm shift on the optimi)ed process and the

lower obser*ed a on #$S E>I due to the direct tunneling of electrons from the substrate

into the ( bulk F93, 91G. #$S SILC degradation is also attributed to bulk traps, and a

strong correlation is obser*ed to trap density measured with charge pumping. lectron

trapping in (fbased o@ides has been attributed to the presence of $@ygen *acancies F92G. he

*ery large initial VT shifts during >I stresses obser*ed on the initial ( process are due to

high densities of pree@isting fast traps associated with =it generation and/or hole trapping F1,

96G. hese traps are *ery shallow, e@plaining the low obser*ed temperature dependence, as

shown in +igure 1.9!b-.

F'(;0e 4.21 )*+ TI moe- '/ e@'/'n( /0*= o0 'n'/'*- =0o,e. ):+ F*/ /0*=

,om=onen/ o e0 e* /em=e0*/;0e ee,/.

his effect is essentially eliminated with reduction in trap densities on the optimi)ed (

process. his is further illustrated by pulsed IV sweeps on the Initial and Final processes that

show large hysteresis on the former shown in +igure 1.99-. +ast traps in ( can lead to large

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instabilities resulting in underestimation of degradation with =C measurements.

F'(;0e 4.22 P;-e I# ,*0*,/e0'*/'on o m*/e0'*- '/ )*+ =oo0 0e-'*:'-'/ *n ):+ (oo

0e-'*:'-'/. P;-e /0/177^e,> '/357^ ;e.

he rate of hot carrier inMection for IntelOs 12nm (#' transistor has been shown to be

substantially lower than for con*entional de*ices at the 62nm node. he reduced degradation

is likely e@plained by the lower inMection rate of the generated charge for the physically

thicker dielectric.

+igure 1.93 shows high temperature AC stressed 4$ data at se*eral different stress *oltages.he powerlaw time dependence slope increased with stress *oltage implying that hot carrier

degradation is contributing to >I degradation during 4$ stress only at biases well in e@cess

of real application conditions, and therefore hot carrier degradation is not a significant

reliability consideration at any realistic use condition for this 12nm technology.

F'(;0e 4.23 45nm H&MG R'n( O,'--*/o0 )RO+

/0ee 'n AC */ '( /em=e0*/;0e

CHAPTER 5

SRAM TECHNOLOGY DE#ELOPMENT

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*ery new generation of process technology at Intel is de*eloped and certified using an

S4A#based QDchip.R D6 is the technology lead *ehicle used for the 12nm technology

ser*ing as a platform for the cooptimi)ation of circuit design and process technology for

S4A#s as well as critical design collaterals for products.

As the workhorse of the embedded memory, S4A#s play an essential role in all Intel

products in achie*ing power performance goals. S4A#s are also ideally suited for process

defect sensiti*ity and detection. he S4A#s on D6 had featured se*eral different S4A#

designs and register files that were indi*idually optimi)ed to take ad*antage of the (i metal

gate process for *arious product applications. IntelOs re*olutionary 12nm technology was

instrumental for aggressi*e S4A# scaling. he tile able S4A# array in D6 was architected

to directly support product applications. he D6 also ser*ed as the *ehicle for se*eral critical

memory circuit technology de*elopments, including secondgeneration dynamic sleep control

and dynamic +orward >ody >ias +>>-. o support process and design learning, D6 includes

an infrastructure of ad*anced test featuresW for e@ample, an rror Correction Code CC-

emulator is designed to &uantify the benefit of error corrections and a Erogrammable >uiltin

Self est E>IS- for highspeed testing with raster capability. +inegranularity In=ie

Variation I=V- oscillators track process *ariation. Critical circuits such as electrically

programmable +use, Ehase Lock Loop ELL-, =igital hermal Sensor =S- and ad*anced

I/$s allowed technologists and designers to work closely to optimi)e the process and circuits

earlier. he D6 test chip successfully met the goals of process and critical collateral

certification to support both process and product de*elopment needs and played an essential

role in IntelOs rapid product ramp at the 12nm technology node

5.1 INTRODUCTION

QDchipsR ha*e been ser*ing the needs of process technology de*elopment at Intel for many

generations. hey ha*e always been based on S4A# building blocks. S4A# has the uni&ue

ad*antages of stressing the most critical design rules of a process technology, pro*iding large

area co*erage that increases defect sensiti*ity, and of pro*iding fine addressable granularity to

enable fault isolation and analysis.

In this chapter we focus on D6, the test chip that was used to certify the (i metal gate

process technology at the 12nm node. $*er the generations, the Dchips ha*e e*ol*ed beyond

the original goal of pro*iding test data needed to identify process defects, to a platform for the

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cooptimi)ation of process technology and critical design collaterals for the products. In the

following section, we pro*ide an o*er*iew of the Dchip.

estability is a key concern with Dchips, and D6 is no e@ception. he testchip must be

sensiti*e to process defects and must e@ercise the critical design rules. A process should not

get certified on the test chip and encounter yield or performance issues when a product is

subse&uently ramped on it. he comple@ity of modern semiconductor processes results in

significant lead time from wafer starts to end of line, while the total time a*ailable to certify a

process remains, at best, the same. +or the process engineer this means only a limited number

of QinfoturnsR during the de*elopment phase. o reduce this information turnaround time, D6

includes a test infrastructure that allows the collection of rele*ant data with reduced test time

and features that aid fault isolation. %e discuss this aspect further in the test features section.

%e now pro*ide descriptions of the critical design collateral content of D6 S4A#s

and some key mi@ed signal circuits that ha*e high process sensiti*ities in the conte@t of

product design. herefore, these classes of circuits are ob*ious choices to be included in the

test chip. %e discuss a productready and tile able common S4A# sub array design along

with performance results. In addition to 6 S4A# arrays, D6 also included multiport

S4A#, a.k.a., register file 4+- memories, for the first time to broaden the process and

product colearning. ew fuse technology is de*eloped with D6 to pro*ide for e@panded

product re&uirements. A significant number of analog elements such as different kinds of

Ehase Lock Loop ELL-, =igital hermal Sensors =S-, and ad*anced I/$ circuits were also

part of the D6 test chip. In the following sections these collaterals are described along with the

key learnings for technology de*elopment and circuit optimi)ation.

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yield due to the tiling of millions of memory bits in product caches. =ue to these reasons it

has been a product design re&uirement for se*eral generations to copy e@actly the memory

bits de*eloped on the D chips.

he S4A# bits are organi)ed into addressable units called sub arrays that ha*e a rectangular

matri@like structure with rows and columns. =uring a read or write operation from the

memory sub array, a specific row and specific columns are acti*ated depending on the

address, and a group of bits called a %ord are read or written. A subarray is designed to be

*ery compact since it is tiled many times to form an ondie cache in a real product. he

compactness can be achie*ed by e@ercising the tightest design rules. $nce a subarray design

is complete, large portions of the Dchip area can be tiled with these subarrays with minimal

additional effort. hus, the S4A# on the Dchips has always pro*ed to be sensiti*e to many

different kinds of process defects. he fine granular addressability of the compact subarrays

allows rapid isolation of the defect location.

$n the test infrastructure side Dchips ha*e always carried an I/$ interface that can

communicate at the desired speeds with all the different tester platforms. A Erogrammable

>uiltin Self est E>IS- has also been an integral part of Dchips to allow highspeed, on

die testing and burnin tests. Among the mi@edsignal collaterals, Dchips ha*e always

included the ELL. his also ser*es as a clock multiplier for ondie, highspeed S4A# testing.

Dchip design faces some uni&ue challenges compared to product design. All the key

electrical parameters of the transis

complite report

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