Comparisons of Different Control Strategies for 20kVA Solid State Transformer

Gangyao Wang, Xu She, Fei Wang, Arun Kadavelugu, Tiefu Zhao, Alex Huang

Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC

wang.gangyao@gmail.com

Wenxi Yao Department of Electrical Engineering

Zhejiang University Hangzhou, China

Abstract—This paper presents and compares different control strategies for 20kVA silicon IGBT based solid state transformer (SST). The SST has a cascaded seven level rectifier stage, three output parallel Dual Active Bridge (DAB) DC/DC stage and an inverter stage. The voltage of the three high voltage capacitors must be balanced for the safe operation of the IGBTs, however, the mismatch of power devices parameters and variance of high frequency transformer leakage inductance of the DAB stage will cause voltage unbalance for these capacitors as well as the power unbalance of the three output parallel DAB stages. This paper analyzed these effects and discussed the limitations and merits for several different control strategies. The newly proposed control strategy for the SST has been determined as the most suitable strategy in terms of performance and simplicity. Simulation and experiment results are presented to validate the analysis.

I. INTRODUCTION Solid State Transformer is an energy router which

provides interface between medium voltage power grid and low voltage residential utility port, it also includes a 400V dc bus which can be the connecting port for renewable energy source like PV, Fuel Cell etc. [1]-[3], and consequently the inverter stage can be eliminated for the grid connection of these sources, as a result the system efficiency will be improved. Due to the voltage rating limitation of the currently available silicon IGBT which has maximum 6.5kV blocking voltage, the proposed 20kVA SST (Fig.1) needs to use three stages topology: seven level cascaded H-bridge AC/DC rectifier to support high input voltage, three output parallel Dual Active Bridge (DAB) DC/DC stage, and a three wire two phase DC/AC inverter stage. With the 7.2kVac input voltage, the three high voltage dc buses have been selected operate at 3.8kV; the low voltage dc bus is 400V. In order to extend the ZVS range for the DAB stage, its high frequency transformer terms ratio has been chosen as the primary secondary voltage ratio 9.5. The switching frequency for rectifier stage is 1080Hz and 3 kHz for DAB stage.

Fig.1. 20kVA Solid State Transformer Topology [2]

Fig.2 gives the sample block diagram of the SST. Under safe operation mode, the three high voltage dc buses need be balanced, that is V1=V2=V3. And power for three input series output parallel DAB stages need be balanced in order to avoid one DAB stage overload, so Pdab1=Pdab2=Pdab3 need be assured.

Fig.2. 20kVA Solid State Transformer block diagram

This work was supported by ERC Program of the National Science Foundation under Award Number EEC-0812121.

978-1-4577-0541-0/11/$26.00 ©2011 IEEE 3173

II. SST MODEL The AC/DC rectifier consists of three cascaded H-bridges, its differential equations are:

321~ VdVdVdinV

dtdiL cba

L ⋅−⋅−⋅−= ...... (1)

11

1 loadLa iiddt

dVC −⋅= ...... (2)

22

2 loadLb iiddt

dVC −⋅= ...... (3)

33

3 loadLc iiddt

dVC −⋅= ...... (4)

Where, L is the input inductor, Li is the input inductor

current, inV~ is the input voltage, 1V

, 2V

and 3V

are three DC bus voltages,

1C ,

2C and

3C are DC buses capacitor

capacitance, ad ,

bd and cd are the rectifier PWM duty cycle

for three H-bridges. Based on the equitation (1)-(4), the AC/DC rectifier stage average model equivalent circuit can be represented as in Fig.3.

Fig.3. Three H-bridge cascaded rectifier average model

The DC/DC DAB stage has the advantages like wide range ZVS for all switches, low voltage stress and bi-directional power flow capability which determined by the phase shift angel between the two H-bridges, its transferred power is given in equation (5) if neglecting losses:

)1(2

ϕϕπ

−⋅⋅⋅⋅⋅

=Lf

ngm

Fig.4. Single DAB Average Model

LfVnV

P outindab ⋅⋅

−⋅⋅⋅⋅=

ππϕϕ

2)/1(

...... (5)

Where, L is the high frequency transformer leakage inductance reflected to the primary,

inV is the input voltage,

outV is the output voltage, n is the transformer turns ratio, f is the switching frequency, and ϕ is the phase shift angle between primary and secondary. Let

Lfn

gm ⋅⋅−⋅⋅

=π

πϕϕ2

)/1(

...... (6)

Then outmindabin VgVPI ⋅== /

...... (7)

inmoutdabout VgVPI ⋅== /

...... (8) So the average model of one DAB stage can be represented as in Fig.4. The DC/AC inverter stage can be analyzed similarly as the rectifier stage. Combine all three stages together, we can get the final average model for the SST as shown in Fig.5.

)/1(2 11

11 πϕϕ

π−⋅⋅

⋅⋅⋅=

Lfngm

)/1(2 22

22 πϕϕ

π−⋅⋅

⋅⋅⋅=

Lfngm

)/1(2 33

33 πϕϕ

π−⋅⋅

⋅⋅⋅=

Lfngm

Figure 5: 20kVA Solid State Transformer average model As we can see from Fig.1, in order to keep three high

voltage DC buses voltage V1, V2 and V3 constant, following equations should be fulfilled:

11 dabrec PP = ...... (9)

22 dabrec PP = ...... (10)

33 dabrec PP = ...... (11) From Fig.5, power equation for each stage can be expressed as:

11 VdiP aLrec ⋅⋅= ...... (12)

22 VdiP bLrec ⋅⋅= ...... (13)

32 VdiP cLrec ⋅⋅= ...... (14)

1

1111 2

)/1(Lf

VnVP Ldab ⋅⋅

−⋅⋅⋅⋅=π

πϕϕ ...... (15)

2

2222 2

)/1(Lf

VnVP Ldab ⋅⋅

−⋅⋅⋅⋅=π

πϕϕ ...... (16)

3

3333 2

)/1(Lf

VnVP Ldab ⋅⋅

−⋅⋅⋅⋅=π

πϕϕ ...... (17)

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Assume321 VVV == , from equations (12)-(14) we can

get: cbarecrecrec dddPPP :::: 321 = ...... (18)

3

33

2

22

1

11321

)/1(:)/1(:)/1(::LLL

PPP dabdabdabπϕϕπϕϕπϕϕ −⋅−⋅−⋅= (19)

Now let’s first examine the power unbalance caused by the rectifier stage. Considering the gating signals sent by the controller are exactly the same (except 120 degrees phase shift between each two modules), but the actual duty

ad , bd and cd may still be different due to different IGBT turn on/off speed and variance of the time delay for gating signals through optic fiber. Assume a 4us worse case difference between each bridge for the gating signals, then the PWM duty difference for ad , bd and cd will be

%5.0/4 ≈sTus for 1080Hz switching frequency, According to equation (18), the loss difference will be around 0.5%, which is a very small portion. However, for the DAB stage, due to the characteristics of magnetic material and transformer manufacture process, it is common for the transformer leakage inductance has a 10-20% variance. If we apply the same phase shift angle for three DAB stages, the power transferred by each stage will be 10-20% different with the assumption that

321 VVV == . And if there is no control strategy to guarantee

321 VVV == , one high voltage dc bus will keep increasing and exceed the IGBT voltage rating, let’s consider the simplest situation. Assume cba ddd == , 321 ϕϕϕ == and 321 LLL ≠≠ , from equation (9)-(19) we can get:

3

3

2

2

1

1321321 ::::::

LV

LV

LVVVVPPP recrecrec == ...... (20)

Consider 321

1:1:11:1:1dabdabdab LLL

≠

...... (21)

In order to make equation (21) valid, two of

1V , 2V ,

3Vneed to be zero, and the other one will be 3 times of its normal value which will definitely cause the IGBT failure. So three high dc voltages balance control is critical to the safe operation of SST.

III. VOLTAGE AND POWER BANLANCE CONTROL Since the three dc buses voltage

1V , 2V ,

3V can be regulated either by the rectifier stage or the DAB stage, there are two types of control method, one is utilizing rectifier stage to regulate three dc buses voltage equal to each other, the DAB stage regulate the power balance, the other type is on the contrast, using the DAB stage to regulate the three dc buses voltage equal to each other, while the rectifier stage regulate the power balance. The analysis in the next part shows this rectifier power balance

can be removed for the reason of DC/DC stage voltage balance control can provide good voltage balance control at the same time.

A. Rectifier stage regulate voltage balance To achieve the control target

321 VVV == , we can either change duty for the rectifier stage or change the phase shift angle for the DAB stage, in paper [4], the author proposed a rectifier PWM duty modulation based voltage balance strategy and analyzed it in detail. The basic idea is changing PWM duty for each H-bridge separately to regulate the high voltage dc buses equal to each other. In paper [5], a 3D space modulation based multilevel rectifier dc buses voltage balance method has been proposed. Unlike above duty modulation method, the new method define three switching pairs (F1,F2,F3) to form a three-dimensional representation of the system, according to the previous switch status and dc bus voltage feedback, the most suitable switching pairs will be selected for the next cycle to achieve voltage balance. For both of the above method, the maximum power unbalance can only be 37% as analyzed in [4], which is only 4% more comparing with balanced power load 33%. Since the DAB stage transformer leakage inductance may have 10-20% variance[6], if just use one DAB regulate the low voltage DC bus, the other two DAB stages share the same phase shift angle as the first one but with 120 and 240 degrees delay, then the power unbalance will be 10-20% percent, the rectifier stage will not be able to ensure

321 VVV == , so separate power balance control has to be added to the DAB stages. As proposed in [4], the control block is shown in fig.6, the average power for each output parallel DAB will be calculated and compared with the reference to determine the phase shift angle for each DAB.

Fig.6. DAB stage power balance control [4]

The above methods will achieve both power balance and power balance, but the DAB output current has to be sensed for the controller which will need three more current sensors. In order to reduce system complexity, following DAB stage voltage balance strategy is proposed.

dcLV

_dcL refV1ϕ1

1i

pKKs

+

1DABI

22

ip

KKs

+refP

2DABI

3DABI

2ϕ22

ip

KKs

+

3ϕ22

ip

KKs

+

1dcHV

1/ 3 _DAB refP

2dcHV

3dcHV

3175

B. DAB stage regulate voltage balance

Unlike above methods, we can let the rectifier stage only regulate the total voltage of the three high voltage DC buses, while the DAB stage regulate

321 VVV == . In this case, from equation(18), the rectifier stage power unbalance will be only caused by the difference of PWM duty which is about 0.5% as stated in section II, with a constant dc bus voltage, and the Prec=Pdab for each horizontal stage, the overall power unbalance can be ignored if the DAB stage can regulate

321 VVV == successfully. There are two methods for DAB stage voltage balance control; the first one is letting the three high voltage DC buses voltage track the output voltage with a constant proportion coefficient as Fig.7 shows.

Since

kV

kV

kVVL

321 === , so 321 VVV == . One obvious

characteristic for this control strategy is that the low voltage dc bus will have the 120Hz low frequency ripple as the same as the high voltage dc bus.

+ − LV

1ϕ

2ϕ

3ϕ

sKK i

p1

1 +

kV 1

+ −

sKK i

p3

3 +

sKK i

p2

2 +

+ −

LV

LVkV2

kV3

Figure 7: DAB stage voltage balance control strategy

The second DAB stage control strategy is shown in

Fig.8. It regulates both refLL VV _= and

321 VVV == . Neglecting the small portion power unbalance caused by the

rectifier stage, the DAB stage can be considered as three input series and output parallel dc/dc converters, it will achieve power balance automatically once you have input voltage balance[7]-[11].

In summary, all above four control strategies can achieve voltage balance, while the first two can get power balance with the sacrifice of putting three extra current sensors, the last two can still get acceptable power balance level with much simpler control. These four control strategies and their control objective for each stage are listed in Table 1.

+ −

+−

+ −

+

−

+−

+

++ +

1V

2V

LVrefVL _

1ϕ

2ϕ

3ϕ

sKK i

p1

1 +

sKK i

p2

2 +

sKK i

p0

0 +

3)( 321 VVV ++

1ϕΔ

2ϕΔ

3ϕΔ3

)( 321 VVV ++

Figure 8: DAB stage voltage balance control strategy

IV. SIMULATION AND EXPERIMENT RESULT To verify the proposed control strategies, circuit simulation has been carried out with Matlab/simulink tool. The deadtime of IGBTs for rectifier stage has been set as 8us, 10us and 12us for each H-bridge, the transformer leakage inductance for DAB stage has been set as 40mH, 45mH and 50mH separately.

Table 1 SST Control Strategies

Control Strategy Rec.(a) Rec.(b) Rec.(c) DAB(a) DAB(b) DAB(c)

I PWM based method

3/1 totaldab PP = 3/1 totaldab PP = 3/1 totaldab PP =

refLL VV _= refVV =1

refVV =2

refVV =3

II 3D Space Modulation based method

refVV =1

refVV =2

refVV =3

III refi

i VV ⋅=�=

33,2,1

cba ddd ==

LVkV ⋅=1

LVkV ⋅=2

LVkV ⋅=3

IV refLL VV _= 321 VVV ==

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Fig.9 shows the simulation wavefcontrol strategy I; it includes three high vvoltage, one low voltage DC bus voltage stages primary current. Control strategy II waveform as Control strategy I which is not

Figure 9: Simulation Waveforms for Stra Fig.10 shows the simulation wavefcontrol strategy III, the low voltage DC bus120Hz frequency ripple which is in phasvoltage DC bus voltage, 120Hz pulsitransferred to secondary instead of constant

Figure 10: Simulation Waveforms for Stra

forms by using oltage DC buses and three DAB

has very similar t repeated here.

ategy I forms by using s voltage has 10V se with the high ing power was power.

ategy III

Fig.11 shows the simulation wastrategy IV, it can be seen that thebeen regulated at 400V, three hvoltage are equal, and the powsecondary is constant.

Figure 11: Simulation Waveform A 20kVA SST prototype hashows. Control strategy IV has beSST system and tested at a lower vhigh voltage dc buses have been svoltage dc bus is 60V.

Figure 12: Prototype test waveforms(Ch1:V Fig.12 shows the VL and threeof the DAB stage, it can be seen thabeen achieved.

Figure 13: 20KVA SST Prototype

veforms by using control e low dc bus voltage has high voltage DC buses wer transferred to the

ms for Strategy IV

as been built as Fig.13 een implemented for the voltage rating. The three set at 620V and the low

VL; Ch2:V1, Ch3:V2; Ch4:V3)

e high voltage dc buses at the voltage balance has

3177

Figure 14: Prototype test waveforms(Ch1:VL; Ch2-Ch4: DAB currents)

Fig 14 shows the VL and three currents of the DAB stage, they are well balanced which means power balance has been achieved.

V. CONLUSIONS This paper analyzed the voltage balance and power balance control issue for the 20kVA SST, four different control strategies has been analyzed and their limitations or advantages has been pointed out which give the conclusion that the proposed control strategy is the best choice in term of performance and complexity. Simulation and experiment results validated the analysis.

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