© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

phys. stat. sol. (c) 5, No. 12, 3854–3857 (2008) / DOI 10.1002/pssc.200780142 p s scurrent topics in solid state physics

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Comparison of two analog buffers implemented with low-temperature polysilicon thin-film transistors for active matrix displays applications

Ilias Pappas*,1, Stilianos Siskos1, Gerard Ghibaudo3, and Charalambos A. Dimitriadis2

1 Electronics Lab., Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece 2 Solid State Section, Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece 3 Institute of Microelectronics, Electromagnetic and Photonics (IMEP – MINATEC), INPG, 3 Parvis Louis Néel, 38054 Grenoble,

France

Received 18 November 2007, revised 5 June 2008, accepted 10 June 2008

Published online 16 September 2008

PACS 85.30.De, 85.30.Pq

* Corresponding author: e-mail ilpap@auth.gr, Phone: +30 2310 998254, Fax: +30 2310 998094

© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction Low-Temperature Polysilicon Thin-Film Transistors (LT poly-Si TFTs) have been widely in-vestigated due to their potential applications in large area electronics [1], such as flat displays, memories and optical devices [2, 3]. Recently, improvement of their electrical properties, such as increase of the carrier mobility, resulted in realization of the Systems on Glass (SoG). But, despite the improvement of their characteristics, they still exist some disadvantages in the use of LT poly-Si TFTs. The main disadvantage is the variation of the threshold voltage from device to device. This threshold voltage shift is caused due to the random distribution of the grain bounda-ries within the channel, even if the devices are imple-mented on the same wafer [4, 5]. Therefore, the analog cir-cuit design by using LT poly-Si TFTs becomes difficult, since threshold voltage variation has to have negligible ef-fect on the circuit performance.

The conventional column driver for a voltage driven

AMD consists of a shift register, a data latch, a digital to

analog converter (DAC) and an output analog buffer. The

architecture of the conventional AMD column driver is

shown in Fig. 1. The output analog buffer is used to trans-

fer the data voltage to the liquid crystal of the pixel. If the

analog buffer performance is sensitive to the threshold

voltage, the supplied data voltage to the liquid crystal will

not be well-controlled, leading to non-uniformity of the

pixel array. Thus, the analog buffer has to be designed in

such away that the threshold voltage variations to have

negligible effect in its performance.

In this paper, two topologies of analog buffers are pre-

sented. The two buffers present high immunity to threshold

voltage variations and they are capable to drive large ca-

pacitance. Also, the performances of the buffers are ex-

tracted by simulations with HSpice. Finally, a comparison

of the performance of the two buffers is presented.

2 Analog buffer topologies The two analog buffers are presented in Figs. 2(a) and (b).

The operation of both buffers is divid\ed on applying

the value of the input voltage Vin to the load capacitance.

Therefore, the gate voltage of the driver transistor, the

voltage at node A in both buffers, needs to be: VA = Vin +

VTH, where VTH is the threshold voltage of the drive tran-

sistor. The operation of the both drivers, are divided into

three phases [6, 7].

In this paper a comparison in the performance of two analog

buffers for Active Matrix Displays (AMDs) applications is

presented. The two buffers are implemented by using low-

temperature polysilicon thin-film transistors (LT poly-Si

TFTs) presenting high immunity to the threshold voltage

variations of the TFTs devices. The verification of their func-

tionality and performance was made through simulation with

Synopsys HSpice. In order the simulations to be realistic and

the performance as close to reality as possible, parameters ex-

traction was made from fabricated LT poly-Si TFTs.

phys. stat. sol. (c) 5, No. 12 (2008) 3855

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Figure 1 Conventional column driver of the pixel array.

Figure 2 (a) and (b): the two analog buffers and their timing

signal diagrams.

The main difference between the two buffers is the

method that was used in the design in order to produce the

proper voltage at node A. In the first buffer, Fig. 2(a), the

voltage at node A is produced by the combination of the

bias voltage, Vbias, which has to be equal to three times the

input voltage, Vin, and the ratio of the channel widths of

transistors M1 and M2. The channel width of M2 (W2) has

to be four time larger than the channel width of M1 (W1)

(W2 = 4W1).

In the second buffer, Fig. 2(b), the input voltage has

three different voltage levels: the “high” level which is

equal to the supply voltage Vdd, the input voltage level,

equal to the data voltage and the “low” level, equal to zero.

During the first operation phase, the “high” level is applied

to the input voltage and node A is charged to “high” volt-

age level through M1. During the second phase, the data

voltage is applied to the input voltage and node A is dis-

charged through M2. Since, M2 is diode-connected, the

node A will be discharged until the voltage of node A be

equal to VA.

3 Simulation set-up The verification of the func-

tionality of the two buffers was made through simulations

using Synopsys HSpice, version Y-2006.03-SP1. The poly-

Si TFT model that was used for the simulations was the

RPI polysilicon TFT model, level 62, version 2, developed

by Renssalaer Polytechnic Institute [8]. The supply voltage

of the first buffer is 21 V and 15 V for the second buffer.

In both buffers, the load capacitance is 20 pF. All transis-

tors have channel length equal to L = 10 µm. The channel

width (W), expressed in micrometer (µm), of each transis-

tor is shown in Table 1.

Table 1 Channel width (W) of the transistors, expressed in µm.

M1 M2 M3 M4 M5 M6

1st

buffer 20 80 70 100 10 -

2nd

buffer 10 20 70 100 10 10

In order to ensure that the simulation results are realis-

tic, the values of the RPI model parameters were extracted

from fabricated low-temperature poly-Si TFTs using the

Silvaco ATLAS tool [6]. The dimensions of the fabricated

TFTs were the same as the dimensions of the transistors

used in the design of the buffers. First, the transfer and the

output characteristics of the fabricated TFTs were meas-

ured experimentally. By using Silvaco’s ATLAS program

[9], the cross-section of the transistors were described.

Then, the measured characteristics were inserted into AT-

LAS program. Optimization of the parameters was per-

formed in order to achieve good correlation between the

measured characteristics and the characteristics reproduced

with ATLAS. The basic parameters, among other, which

are extracted from the fabricated TFTs, are the threshold

voltage and the electron mobility. The threshold voltage

(parameter VTO in HSpice) of the transistor with size W/L

= 10 µm/10 µm was found to be 1.87 V and its high field

mobility (parameter MUO in HSpice) was found to be 130

cm2/Vs. For the transistor with size W/L = 100 µm / 10 µm,

the same parameters were found to be 1.91 V and 107

cm2/Vs, respectively.

The default values of the RPI model parameters were

replaced from the extracted values and the characteristics

of each transistor were reproduced again. The measured

and simulated characteristics were in good agreement, with

a deviation between them by about 2%. The good correla-

tion between the measured and the simulated characteris-

3856 I. Pappas et al.: Comparison of two analog buffers implemented with polysilicon thin-film transistors

© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-c.com

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tics confirms that HSpice simulations are realistic and, thus,

the functionality of the buffers can be ensured.

4 Simulation results and comparison The simu-

lation results of the two buffers are shown in Fig. 3. Offset

voltage is the difference between the input voltage and the

output voltage, applied on the storage capacitance Cs. As it

can be seen from Fig. 3, the offset error of the buffers is up

to 402 mV for the first buffer and 235 mV for the second.

Furthermore, the offset error increases as the data voltages

increases. The simulations have shown the good function-

ality of the two buffers.

The performance parameters of the two buffers is sum-

marized in Table 2.

Figure 3 (a) and (b) The offset voltage of the two buffers for dif-

ferent data voltages.

Table 2 Parameters for the two buffers.

Parameter 1st Driver 2

nd Driver

Number of TFTs 28 TFTs 22 TFTs

Offset Error up to 4 %

(402 mV)

up to 2.35 %

(235 mV)

Response Time 9 µs 7 µs

Supply Voltage (Vdd) 21 V 15 V

Power Consumption 68 nW 36.5 nW

Additional Signals

one bias voltage

(Vbias = 3 Vin)

and one control

signal (select)

two control sig-

nals (select and

discharge)

Additional changes in

column driver archi-

tecture

one voltage ge-

nerator for pro-

ducing Vbias

three levels data

voltage

Operation Phases three three

Model Carlo Results up to 7 % up to 4.5 %

Capacitor for storing

the Vth

no no

The comparison was made for the most important pa-

rameters of the buffers performance. The first examined

parameter is the silicon real estate. The silicon real estate

was estimated with the number of the unit TFTs that are

used in each topology. The dimensions of the unit TFT was

considered to be: W/L = 10 µm/10 µm. 28 unit TFTs are

needed for the first buffer and 22 for the second, causing to

a 20 % reduction of the silicon real estate. The offset error

is up to 4 % for the first buffer and up to 2.35 % for the

second buffer. The offset error of the two buffers is almost

the same when the input data voltage is small (from 2 V

until 5 V) and there is a significant difference for higher

input data voltages. The offset errors of the two buffers sat-

isfy the specifications of an AMLCD [10]. Furthermore,

the response time of the first buffer is 9 µs and 7 µs for the

second. The response time is the time needed for the output

voltage to reach the 90 % of the data voltage. One of the

most important parameters in the buffers design is the sup-

ply voltage. The supply voltage of each buffer has to be

carefully chosen because it has to ensure that all transistors

will be working in the saturation region and at the same

time increase of the supply voltage causes increase of the

power consumption. The supply voltage and the power

consumption of the first buffer are 21 V and 68 nWatts and

15 V and 36.5 nWatts, respectively. The power consump-

tion was calculated from HSpice simulations for the three

operation phases when the data voltage is 5 V. Apart from

the higher supply voltage, another reason, causing the

higher power consumption of the first buffer exists. During

the second phase of operation, transistors M1 and M2 are

turned “ON” at the same time, resulting a high current

flowing from the supply voltage direct to the ground. In the

second buffer, all transistors are working as switches or

they are used for sampling the threshold voltage. Thus, in

the second buffer, small current is flowing only during the

transmission of the signal and for charging capacitances.

Conclusively, the second buffer exhibits 41 % less power

consumption.

For the right operation of the first buffer, one bias volt-

age, equal three times the input data voltage, and one con-

trol signal (Select) are needed. On the other hand, two con-

trol signals (Select and Discharge) are needed for the sec-

ond buffer. The additional signals cause changes in the ar-

chitecture of the conventional column and row drivers. The

control signals will be produced from the row driver. In

real applications, the bias voltage levels that are needed for

the first buffer are exactly as many as the input levels are.

The bias voltage levels can be generated with a voltage

generator, which is designed for TFT-LCD flat panels. The

voltage generator can be implemented by using operational

amplifiers [11] or a charge pump [12]. The bias voltage

generator will share the same control signals as the input

voltage generator, since the two voltages will be supplied

together at the proposed driver. Thus, the voltage generator

can be easy inserted in the column driver architecture.

Monte Carlo analysis of the buffers, for the different

input voltage levels, was performed in order to determine

the effect of the threshold voltage variations in the buffers

performance. For Monte Carlo analysis, we assumed Gaus-

sian distribution of the threshold voltage of the transistor

M2 and the drive transistor, with standard deviation of the

threshold voltages ± 20% from their nominal values of

1.87 V and 1.91 V. Such a distribution for the threshold

voltage was found from the statistical analysis of the de-

vice parameters, obtained from measurements in a large

phys. stat. sol. (c) 5, No. 12 (2008) 3857

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number of TFTs of the same technology [13]. The varia-

tion of the threshold voltages of these two transistors was

considered, because identical value for the threshold volt-

ages is crucial for the functionality of the proposed buffer.

This is the worst case scenario, since the threshold voltage

of both transistors is varied up to 40% (VTH,M1 ± 20%

and VTH,M5 ± 20%). The second buffer has shown better

immunity in the threshold voltage variations, since the off-

set voltage was measured to be up to 4.5 % (451 mV) for

input data voltage equal to 10 V, compared to the first

offset voltage which was measured to be up to 7 %

(697 mV).

5 Conclusion In this paper two analog buffers for Active Matrix Displays (AMDs) applications are presented. The two buffers are specially designed for exhibiting high immunity to the threshold voltage variations of the TFTs. The verification of their functionality was made through simulations with HSpice. In order the simulations to be re-alistic, parameters extraction of fabricated poly-Si TFTs was made. Both buffers’ performance satisfied the specifi-cations required for AMDs applications. Finally, a com-parison of their performance was carried out, based on simulations results. The comparison has shown that the second buffer has better performance in all examined as-pects.

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