comparison of hybrid asymmetric and conventional...

Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications

Master of Science Thesis in the Master’s programme Electric Power Engineering

AMIR SAJJAD BAHMAN Department of Energy and Environment Division of Electric Power Engineering CHALMERS UNIVERSITY OF TECHNOLOGY Göteborg, Sweden 2011

MASTER’S THESIS 2011

Comparison of Hybrid Asymmetric and

Conventional Multilevel Inverters for Medium Voltage Drive Applications

Master’s Thesis in the Master’s Programme Electric Power Engineering

AMIR SAJJAD BAHMAN

Department of Energy and Environment Division of Electric Power Engineering

CHALMERS UNIVERSITY OF TECHNOLOGY

Göteborg, Sweden 2011

Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications Master’s Thesis in the Master’s Programme in Electric Power Engineering

AMIR SAJJAD BAHMAN

© AMIR SAJJAD BAHMAN, 2011

Department of Energy and Environment

Division of Electric Power Engineering

Chalmers University of Technology

SE-412 96 Göteborg

Sweden

Telephone: + 46 (0)31-772 1000

Cover: A medium-voltage frequency converter, the ABB PCS 6000 Wind,

Reference: http://www.windpowerengineering.com/tag/abb

Göteborg, Sweden 2011

I

Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications

Master’s Thesis in Master’s Programme in Electric Power Engineering AMIR SAJJAD BAHMAN Department of Energy and Environment Electric Power Engineering

Chalmers University of Technology

ABSTRACT

Power electronic converters are becoming more and more popular for various industrial applications. To overcome the limitation of semiconductors current and voltage ratings in high power applications, series and parallel connection of switches is often considered an effective solution. In addition, stepped waveform in the output of inverter has better harmonic spectrum than 2-level waveform in low switching frequencies. So, in recent years multilevel inverters have gained great interest in industry. Among the different solutions available for multilevel converters, the asymmetric topologies allow to generate more voltage levels with less number of semiconductors and thus increase of output performance and system reliability. For these reasons, this kind of topology has attracted a lot of attention both from the customers and from the manufacturers. Application of appropriate semiconductor switches in the different cells of the inverter leads to increase of inverter efficiency. This inverter is typically known as hybrid inverter.

In this work, different topologies of multilevel inverters consisting cascaded symmetric, diode-clamped, flying-capacitor, and hybrid asymmetric are investigated. It will be shown that hybrid asymmetric inverter has more reliable topology than others, due to less number of power semiconductor switches and higher voltage levels. Also different multilevel modulation techniques will be studied form voltage waveforms and harmonic spectra aspects. This study proves that Phase Disposition Pulse Width Modulation shows less harmonic distortion than other techniques.

Comparison of hybrid asymmetric inverter with conventional multilevel inverters will be lead in two states of constant frequency and constant efficiency. The results indicate that, hybrid asymmetric topology has better performance in power losses, total harmonic distortion and first distortion factor than other topologies that leads to energy saving, better power quality and reduce in size, weight and volume of its LC filter.

Key words: Hybrid asymmetric multilevel inverter, medium voltage drive, modulation techniques, power losses.

III

Acknowledgment This work has been carried out at the Division of Electric Power

Engineering, Department of Energy and Environment at Chalmers University of Technology, Gothenburg, Sweden.

I would like to thank first and foremost my examiner Dr. Massimo Bongiorno for his valuable and constructive suggestions during this work and advices in revising the thesis manuscript extensively to give it a better shape.

I would also like to express my deep and sincere gratitude to my supervisor Dr. Ghasem Aghdam for his patience, encouraging, stimulating and critical comments regarding the work.

I express my sincere appreciation to Mohammadreza Derakhshanfar, Mehdi Javdani Erfani, Shahab Shariat Torbaghan, Ali Mehdipour, and Saeid Haghbin my dear friends at division for their help, suggestions, and friendship throughout my time at Chalmers and for all the great memories away from the research.

Finally, I’d like to dedicate this work to the love of my life, Mona, for her deep love, patience, and encouragement from a long distance and my dear family, my parents, Manouchehr and Nafiseh, my sister and brother, Sara and Ali, for their encouragement, support, and love which always warms my heart in the darkest moment.

Göteborg March 2011

Amir Sajjad Bahman

V

Contents ABSTRACT I

ACKNOWLEDGMENT III

CONTENTS V

1 INTRODUCTION 1

1.1 High-power medium-voltage drives classification 2

1.2 Multilevel inverters, features, advantages and applications 4

1.3 Hybrid and asymmetric multilevel inverters 6

1.4 Thesis topics 7

2 MULTILEVEL INVERTER TOPOLOGIES 8

2.1 2-level and 3-level voltage source inverters 9

2.2 Multilevel inverters 10

2.2.1 Symmetric multilevel inverters 10

2.2.2 Asymmetric multilevel inverter 15

2.3 Hybrid multilevel inverters 17

2.4 Conclusions 19

3 MODULATION TECHNIQUES 20

3.1 Carrier based PWM 21

3.1.1 2-level PWM 21

3.1.2 Multilevel PWM 23

3.2 Conclusion 34

4 DRIVE SYSTEM AND PERFORMANCE INDEXES 36

4.1 Inverter specification 36

4.1.1 Dc-link voltage 37

4.1.2 Power semiconductor selection 38

4.2 Performance indexes 38

4.2.1 THD 38

4.2.2 DF1 39

4.2.3 Semiconductor power losses 40

4.2.4 Efficiency 43

4.3 Conclusion 44

5 COMPARISON OF DIFFERENT MULTILEVEL INVERTERS 45

5.1 Simulation environment 45

5.2 Simulation results 48

VI

5.2.1 Comparison at constant carrier frequency 48

5.2.2 Comparison at constant efficiency 51

6 CONCLUSION AND FUTURE WORK 54

6.1 Results 54

6.2 Future work 54

7 REFERENCES 56

CHALMERS, Electric Power Engineering, Master’s Thesis 2011 1

1 Introduction The increasing demand for electrical energy, depleting fossil energy

reserves and the increase in energy prices have necessitated to use the current energy resources more efficiently. Power electronic converters as the essential equipments to convert and control of electrical power in the wide range of milliwatts to gigawatts with the help of semiconductor devices are finding increased attention. Hence, highly efficient power electronic technologies and reliable control strategies are needed to reduce the waste of energy and to improve power quality. One of the most significant potentials to improve the efficiency of electrical energy in industry is electric motor drive systems.

Today, medium voltage drives have found extensive application in various industries, such as oil, gas and petrochemical industry, the cement industry, water pumping stations, metal industry, rolling mills, traction applications, wind power generation, marine drives, reactive power compensation, high voltage direct current (HVDC) transmission as well as many other applications [1]. On the other hand, several industries have increased their power-level needs, urged mostly by economy of scale (production levels and efficiency), causing the development of new power semiconductors, converter topologies, and control methods. Currently, medium voltage drives cover a power range of 0.2 MW to 40 MW at voltage level of 2.3 kV up to 13.8 kV [2].

However, at present 97% of the currently installed medium voltage motors operate at fixed speed; and only 3% of these are controlled by variable-speed drives [1]. One of the major markets for medium voltage drives is retrofit applications. For instance, when fans or pumps are driven by fixed speed motor, air or liquid flow are controlled normally by conventional mechanical methods, such as throttling control, inlet dampers, and flow-control valves, resulting in large amount of energy loss [3].

Therefore, there is a huge scope for developing adjustable speed drives for industrial applications. The installation of controlled medium voltage variable-speed drives reduces the energy loss and leads to a significant savings on energy cost and improving the power quality [2]. The power quality of medium voltage drives is affected by the applied converter topology, the load characteristics, the size and the type of the utilized filter, the level of switching frequency, and the control method [1].

Nevertheless, the design of these drives is faced with a number of challenges related to topologies and control of power line side converter (e.g. power quality, resonance, and power factor) and motor side converter (e.g. dv/dt, torque ripples, motor derating caused by generated harmonics and travelling wave reflections), as well as power semiconductor devices (semiconductor losses)[1]. Essential requirements for medium voltage drives are high efficiency, high reliability, low cost, small size and in some applications, high dynamic performance and regeneration capability [1].

2

1.1 High-power medium

Fig. 1.1 shows a simplified classification of converters used in highmedium-voltage applications, which have a main division into direct and indirect connections of power supply and load. The formerthe load to the source directly through power semiconductors and suitable control method. The latter transfers the power indirectly in two stages of rectification and inversion via an energy

For direct conversion, power applications, which use a series of semiconductor switches to connect directly the high power supply to the load. Cycloconverters convert a threephase ac voltage with a fixed magnitude and frequencyvoltage with variable magnitude and variable frequency. Matrix converters are included in this category but they are not listed in classification, since the technology is not available for highkVA [4].

In the other side of this classification, indirect converters are divided basically into current-source and voltagedc-link energy-storage component.

Fig. 1.1 Classi

Voltage Drives

Direct conversion

ac-ac

Cycloconverter Current Source

CHALMERS, Electric Power Engineering, Master’s Thesis 2011

power medium-voltage drives classification

Fig. 1.1 shows a simplified classification of converters used in highvoltage applications, which have a main division into direct and

indirect connections of power supply and load. The former usually connects the load to the source directly through power semiconductors and suitable control method. The latter transfers the power indirectly in two stages of rectification and inversion via an energy-storage component [3].

For direct conversion, cycloconverters are the most used topology in high power applications, which use a series of semiconductor switches to connect directly the high power supply to the load. Cycloconverters convert a threephase ac voltage with a fixed magnitude and frequency to a threevoltage with variable magnitude and variable frequency. Matrix converters are included in this category but they are not listed in classification, since the technology is not available for high-power ranges, reaching only up to 150

In the other side of this classification, indirect converters are divided source and voltage-source topologies, depending on the

storage component.

Classification of converters topologies for high-power drives

Medium-Voltage Drives

Indirect conversion (DC-Link) ac-dc-ac

Current Source

PWM Current Source Inverter

Load Commutated

Inverter

Voltage Source

Multilevel Inverters

Single DC source

NPC

Flying Capacitor

Multiple Isolated DC

sources

Cascaded

H-Bridge

Symmetric (Equal DC sources)

Asymmetric (Unequal DC

sources)

High Power

, Master’s Thesis 2011

voltage drives classification

Fig. 1.1 shows a simplified classification of converters used in high-power voltage applications, which have a main division into direct and

usually connects the load to the source directly through power semiconductors and suitable control method. The latter transfers the power indirectly in two stages of

storage component [3].

cycloconverters are the most used topology in high power applications, which use a series of semiconductor switches to connect directly the high power supply to the load. Cycloconverters convert a three-

to a three-phase ac voltage with variable magnitude and variable frequency. Matrix converters are included in this category but they are not listed in classification, since the

power ranges, reaching only up to 150

In the other side of this classification, indirect converters are divided source topologies, depending on the

power drives

Voltage Source

Multiple Isolated DC

sources

Cascaded

Bridge

Symmetric (Equal DC sources)

Asymmetric (Unequal DC

sources)

High Power

2-level VSI


Fig. 1.2 shows a typical view of an indirect medium-voltage drive. Depending on the system demands and the type of converters applied, the line and motor side filters are optional. A phase shifting transformer with multiple secondary windings is often utilized mainly for the line current distortions. The rectifier converts the power supply voltage to a dc voltage with a fixed or variable magnitude. The generally used rectifier topologies include multi-pulse diode or thyristor rectifiers and pulse width modulation (PWM) rectifiers. The dc link can simply be a capacitor that supplies a stiff dc voltage in voltage-source inverters or an inductor that smoothes the dc current in current-source inverters [3].

Fig. 1.2 Typical block diagram of medium voltage variable speed drives

For current-source drives, two topologies have found industrial applications in high power ranges: the load-commutated inverter (LCI) and the PWM-CSI. The LCI has been utilized for many years presenting simple converter topology, low manufacturing cost, and reliable operation. Its main problems include low input power factor and distorted input current waveforms, which these problems are overcame by the newer technology of PWM-CSI [5].

On the other hand, high-power voltage-source inverters (VSI), have attracted more markets and developed significantly over the last decades, compared to current-source topologies. The voltage-source drives are divided in two groups of high-power two-level and multilevel inverters. The simplest topologies of VSIs are single-phase half-bridge inverter which generates a 2-level square-wave voltage and full-bridge inverter which generates 3-level waveform. These classical inverters were limited to low or medium power applications due to the limitations on the power semiconductor voltages and currents. The series connection of semiconductor switches enabled high two-level VSIs for high-power applications.

However, the addition of some other power components, like diodes or capacitors, and utilization of more complex switching methods permitted a more interesting use of these additional components to enhance the quality of input and output currents and voltages, originating the family of multilevel VSI technology.

Although multilevel inverters were basically developed to reach higher voltage operation, before being restricted by semiconductor limitations, the extra switches and dc sources (supplied by dc-link capacitors) could be used to generate different voltage levels, enabling the generation of stepped


waveform with less harmonic distortion, reducing dv/dt and common-mode voltages. These characteristics have made them popular for high-power medium-voltage applications but the large number of semiconductor switches in these inverters, result in a reduction both of the reliability and efficiency of the drive [18]. Therefore, many power electronic researchers have made great effort in developing multilevel inverters with the same benefits and less number of semiconductor devices.

1.2 Multilevel inverters, features, advantages and applications

In 80s, many power electronics researches were focused on increase of the current and voltage ratings of semiconductor devices. To obtain higher voltage levels, a group of researchers started to study new inverter topologies that were able to operate at high voltages. In 1981, A. Nabae, I. Takahashi and H. Akagi presented a new inverter topology, which was named “neutral-point-clamped PWM inverter (NPC-PWM)”. In fact, this topology was an improved circuit of the classical 2-level inverter [13]. Although the new topology was just 3-level inverter, it had the potential to be extended to N-levels. Today, this inverter is known as “diode-clamped multilevel inverter” [15].

Currently, in terms of topology, multilevel inverters can be mainly divided into three major groups:

• “Cascaded multilevel inverters”: These inverters include several H-

bridge cells (Full-bridge inverters) connected in series. One leg of a

cascaded multilevel inverter is shown in Fig. 1.3. In the same figure, it

is possible to observe the structure of one individual cell.

1Cell

2Cell

3Cell

4Cell

4

dcV

4

dcV

4

dcV

4

dcV

aV

Fig. 1.3 Cascaded multilevel inverter


• “Diode-clamped multilevel inverters”: These inverters use clamped

diodes and dc capacitors in order to generate ac voltage. This inverter

is manufactured in 3, 4 and 5-level structures. The 3-level structure is

known as “neutral-point clamped (NPC)” and is widely used in

medium voltage, high power drives. One leg of an NPC inverter can be

seen in Fig. 1.4.

1SW

2SW

3SW

4SW

5D

6D

aV2

dcV

2

dcV

Fig. 1.4 NPC inverter

• “Flying-capacitor multilevel inverter”: In this topology, semiconductor

devices are in series and their connecting points are clamped by extra

capacitors, as it can be seen in Fig. 1.5.

1SW

2SW

3SW

4SWaV

2

dcV

2

dcV

5C

Fig. 1.5 Flying-capacitor inverter


Together with the converter topology, great effort has been addressed from the research community in investigating different switching methods for these inverters. This is mainly due to the fact that the adopted switching strategy impacts the harmonic spectrum of output waveforms as well as the switching and the conduction power losses. In case of multilevel converters, three switching methods are usually used [14]:

• “Selective Harmonic Elimination”. In this method, each switch is

turned on and turned off once in a switching cycle and switching

angles are usually chosen based on specific harmonics elimination or

minimization of output voltage Total Harmonic Distortion (THD).

• “Carrier-Based PWM”. In this method, drive signals of switches are

derived from comparison of reference signal with carrier signals.

• “Space-Vector PWM”. The space vector modulation technique is based

on reconstruction of sampled reference voltage with help of switching

space vectors of a voltage source inverter in a sampling period.

1.3 Hybrid and asymmetric multilevel inverters

The topologies mentioned before are typically called “symmetric multilevel inverters”, because the dc link capacitors have the same voltages. Asymmetric multilevel inverters have the same topology as symmetric ones; the only difference is in the dc link voltages. However, the asymmetric multilevel inverters can generate higher number of output voltage levels with the same number of semiconductor switchers in symmetric ones. Therefore, in these inverters the efficiency is improved by using less semiconductor devices and more complicated switching algorithms; while, output filters are very small or even removed [14, 15]. One leg of an asymmetric multilevel inverter is shown in Fig. 1.6.

1Cell

2Cell

4

dcV

aV

4

3 dcV×

Fig. 1.6 Asymmetric multilevel inverter

Since the different cells of asymmetric inverter work with different dc link voltages and different switching frequencies, it is more efficient to use appropriate semiconductor devices in different cells. For example, using IGCT (Integrated Gate-Commutated Thyristor) switches which are suitable for high voltage low frequency applications, in higher voltage cells decreases the


power losses. These inverters are called “hybrid multilevel inverters”. A hybrid inverter which uses several types of semiconductors has many advantages [17, 18]. Active power is transferred by semiconductors with low losses and high reliability and the output harmonic spectrum is improved by other semiconductors.

1.4 Thesis topics

This thesis investigates hybrid asymmetric multilevel inverters for medium voltage drive applications. In addition, it presents some comparisons of this type of inverters with conventional multilevel inverters in terms of harmonic distortion, power losses and efficiency. The inverter consists of a main cell with IGCT switches and a sub cell with IGBT (Insulated-Gate Bipolar Transistor) switches. Main and sub cells are connected in series in each phase [19]. IGCT is a device with high reverse voltage, high reliability and low losses which is used in the main cell [20-22], while IGBT is a device with high switching frequency which is used in the sub cell to obtain low harmonic spectrum in the output of inverter.

In the second chapter of this thesis, a brief overview of different multilevel inverter topologies and new research topics in this field are presented and their advantages and disadvantages are discussed briefly. In addition, these topologies are compared in different aspects. At the end, the hybrid asymmetric multilevel inverter topology is derived.

In Chapter 3, different modulation techniques in voltage source inverters are explained. Also, the carrier-based multilevel PWM, which is applied in hybrid asymmetric multilevel inverters extensively, is analyzed briefly and different multilevel PWM techniques are compared from voltage waveforms and harmonic spectra aspects and the most appropriate modulation technique is derived.

In Chapter 4, the inverter specifications, semiconductor devices, and the performance indexes consisting power losses, harmonic distortions, and efficiency that will be compared in different topologies will be studied.

In Chapter 5, the simulation environment and results of comparison between hybrid asymmetric and conventional multilevel inverters in two methods of constant carrier frequency and constant efficiency will be presented.

In the last chapter, a summary of works which have been done on multilevel inverters in this work are presented; finally, future works that can be followed in continue of this thesis, are mentioned.


2 Multilevel Inverter Topologies In recent years, industry has demanded for high power equipments, which

today reaches to megawatts. Adjustable ac drives which operate in high power range are usually connected to the medium voltage network. Hence, medium and high voltage ac drive systems have been considered widely. Today, due to limitation of semiconductor devices to operate in high current and voltage ratings, it is difficult to connect a semiconductor switch directly to medium voltage networks (2.3 – 6.9 kV). To achieve this problem, a family of multilevel inverters has been emerged for working in medium and high voltage levels [23].

Multilevel inverters consist of a series of power semiconductor devices and capacitors, which generate voltages with stepped waveforms in the output. Fig. 2.1 shows one phase leg of multilevel inverters. In this schematic diagram, operations of semiconductors are shown by an ideal switch with several states. The switching algorithms of switches and commutation of them allow the addition of the capacitor voltages as temporary dc voltage sources, whereas the semiconductors should withstand limited voltages of capacitors.

a

aV

CV

CV

CV

0 Fig. 2.1 One phase leg of a multilevel inverter

The large number of semiconductors in the multilevel inverters has a negative impact on the reliability and on the overall efficiency of these types of converters. On the other hand, using inverters with the low number of semiconductors needs large and expensive LC filters to limit insulation stress of motor windings or can be applied for motors that can withstand this stress [6-12].

In this chapter, first the structure of inverter is briefly explained and then different topologies of multilevel inverters, their advantages, disadvantages and comparison in different aspects are discussed. In this case, first the topologies of symmetric multilevel inverters are investigated and then asymmetric multilevel inverters are discussed. Finally, based on these inverters, the topology of hybrid asymmetric multilevel inverter is derived.


2.1 2-level and 3-level voltage source inverters

Generally inverters can be divided in two major groups: “single-phase inverters” and “three-phase inverters”. The simplest inverter structure is half-bridge single-phase inverter which generates 2-level square waveform, whereas output waveform of a full-bridge single-phase inverter is 3-level square waveform. Full-bridge inverters are known as H-bridge inverter due to their structure shape. These two structures are shown in Fig. 2.2 and Fig. 2.3.

In half-bridge single-phase inverter, two switches are needed which should not be turned on simultaneously to prevent short-circuit of the dc source. In first half-cycle, �� is on and �� is off, so load voltage is equal to ��/2. In second half-cycle, �� is off and �� is on so load voltage is equal to ��/2. In full-bridge inverter when (��, ��) are on and (��, � ) are off, load voltage is equal to �� whereas, in the case of (��, ��) are off and (��, � ) are on, �� is seen on load. To apply zero voltage on load, (��, � � should be on and (��, ��) should be off or vice versa.

Similar to the half-bridge case, in full-bridge inverter the pairs of (��, ��) and (��, � ) should not be on simultaneously. The output voltage waveforms of half-bridge and full-bridge inverter are shown in Fig. 2.4 and Fig. 2.5.

1S

2S

oi

2/dcV

2/dcV

ov

Fig. 2.2 Half-bridge inverter power circuit

1S

2S

oi

ov

4S

3S

dcV

Fig. 2.3 Full-bridge inverter power circuit (H-bridge)


2/dcV

ov

2/dcV−

Fig. 2.4 Half-bridge inverter output voltage waveform

ov

dcV

dcV−

Fig. 2.5 Full-bridge inverter output voltage

2.2 Multilevel inverters

Multilevel inverters are being used widely in static VAr compensators, active power filters and adjustable speed drives (ASDs) for medium voltage induction motors [23]. Usually the inverters which generate more than two phase potentials are known as multilevel inverters. By increase of the voltage levels to infinite value, THD of voltage waveform decreases to zero, since the waveform will be more sinusoidal; but, in practice the accessible voltage level is limited because of voltage unbalancing problems and power losses [23]. In this part, the most important topologies of multilevel inverters and their characteristics will be discussed.

2.2.1 Symmetric multilevel inverters

There are three decades that multilevel inverters are being used in the world of power electronics [8]. They are named by the number of voltage levels that generate and different topologies they have. Usually the number of output voltage levels is odd instead of even. It means that the definition of a zero voltage level in the output of inverter like in 3-level or 5-level inverters makes it more sinusoidal and less harmonics are made. This issue will be discussed later in this chapter. As discussed in the introductory part of this


thesis, the most conventional topologies of multilevel inverters are listed below [23]:

• Cascaded H-Bridge multilevel inverter

• Diode-clamped multilevel inverter

• Flying-capacitor multilevel inverter

These inverters are known as symmetric multilevel inverters, since their DC link capacitors have the same voltages and all the semiconductor devices should be able to block these voltages in the off state.

2.2.1.12.2.1.12.2.1.12.2.1.1 Cascaded HCascaded HCascaded HCascaded H----bridge multilevel ibridge multilevel ibridge multilevel ibridge multilevel inverternverternverternverter

Fig. 2.6 shows the power circuit of a 5-level cascaded H-bridge inverter [6, 10, 24]. For clarity of the figure, only one phase is shown in the figure. In this topology power cells are in series and the number of phase voltage levels that can be obtained at the converter terminals is proportional to the number of cells. In other words, in this topology the number of phase voltage levels at the converter terminals is 2� � 1, where � is the number of cells or dc link voltages.

In this topology, each cell has separate dc link capacitor and the voltage across the capacitor might differ among the cells. So, each power circuit needs just one dc voltage source. The number of dc link capacitors is proportional to the number of phase voltage levels.

The ground point shown in Fig. 2.6 is a common reference point and all phases are connected in this point. Each H-bridge cell may have positive, negative or zero voltage. Final output voltage is the sum of all H-bridge cell voltages and is symmetric with respect to neutral point, so the number of voltage levels is odd.

Cascaded H-bridge multilevel inverters typically use IGBT switches. These switches have low block voltage and high switching frequency. Cascaded H-bridge inverters have excellent input current and output voltage waveforms. Output voltage has smooth steps, so the output filter is usually not needed or in the case of necessity it can be very small [12].

The most important problems with the drives using this inverter are the high number of devices to rectify ac to dc voltage, complex switching patterns to command all the switches and need of multi-pulse input transformer that affect the efficiency, reliability and system costs [16].

aV4

dcV

4

dcV

Fig. 2.6 Cascaded H-bridge 5-level power circuit


2.2.1.22.2.1.22.2.1.22.2.1.2 DiodeDiodeDiodeDiode----clamped multilevel inverterclamped multilevel inverterclamped multilevel inverterclamped multilevel inverter

Fig. 2.7 shows the power circuit of a 5-level diode-clamped inverter [9, 13]. For clarity of the figure, only one phase is shown. In this topology, semiconductor devices are connected in series and dc link is divided to smaller capacitors and connects to switches by clamp diodes. The clamp diode connections are necessary to block the current and their numbers in each leg are selected in such a way to have the same block voltages like the switches.

DC link capacitors are the same for all phases, so one dc voltage source is needed for the dc link. The number of capacitors in each phase is proportional to the number of phase voltage levels.

The ground point shown in the figure is the common reference point and is connected to the middle of dc link. To generate N voltage levels by the aim of the diode-clamped inverter, N-1 capacitors are needed on the dc bus [25]. For example, in a 5-level inverter shown in fig 2.7, dc bus voltage consists of four capacitors: ��, ��, �� and � . If they are being fed by a dc link voltage of ��, the capacitors voltages will be ��/4. Table 2.1 presents switching pattern of a 5-level diode-clamped inverter. “1” indicates that the switch is ON and “0” indicates that the switch is OFF. It is obvious from this table that in each cycle just four switches should be ON.

1S

2S

3S

4S

5S

6S

7S

8S

1C

2C

3C

4C

aV

4

dcV

4

dcV

4

dcV

4

dcV

Fig. 2.7 Diode-clamped 5-level inverter power circuit


Table 2.1 Diode-clamped 5-level inverter switch states

Output Switch state S� S� S� S S� S� S� S� V��/2 1 1 1 1 0 0 0 0 V��/4 0 1 1 1 1 0 0 0

0 0 0 1 1 1 1 0 0 V��/4 0 0 0 1 1 1 1 0 V��/2 0 0 0 0 1 1 1 1

Since in Diode-clamped multilevel inverter topology switches should withstand the dc link voltage, this topology uses HV-IGBT (High Voltage IGBT) switches, but IGCT switches seem to be more suitable for this application. Diode-clamped multilevel inverter has a simple circuit but generates high and steep voltage steps which may impact the life time of the motor windings; therefore, an additional filtering stage is needed to reduce the ripple in the inverter output voltage. Theses filters are usually heavy and expensive in comparison with the filters used in cascaded H-bridge inverters [25].

2.2.1.32.2.1.32.2.1.32.2.1.3 FlyingFlyingFlyingFlying----capacitor multilevel invertercapacitor multilevel invertercapacitor multilevel invertercapacitor multilevel inverter

Fig. 2.8 shows one phase leg of the power circuit for a flying-capacitor 5-level inverter [23]. In this topology semiconductor devices are connected in series and their connecting points are clamped by extra capacitors. In this topology series connections of clamped capacitors are necessary to block the current and their numbers in each leg are selected in such a way that all the capacitors store the same energy. In this way large and heavy capacitors will not be needed.

The ground point shown in the figure is the common reference point and, similarly to the diode-clamped topology described in the previous section, is connected to the middle point of the dc link. The output voltage is symmetric with respect to the neutral point. When using this kind of inverter topology, if the system generates even voltage levels, the number of dc link capacitors will be odd. In other words, to generate N-level output voltage, N-1 dc link capacitors are needed [25]. It is clear in Fig. 2.8 that there is not any connections in the three interior loops between balancing capacitors (��, ��, ��) to the dc link sources for each phase, like the diode clamped topology. Table 2.2 presents switching pattern of a 5-level flying-capacitor inverter.

Large number of clamped capacitors makes this inverter bulky and expensive. Also, to balance the capacitors voltages, specific controls and accurate measurements should be considered.


1S

2S

3S

4S

5S

6S

7S

8S

1C

2C

3C

4C

cC

cC

cC

bC

bC

aC

4

dcV

4

dcV

4

dcV

4

dcV

aV

Fig. 2.8 Flying-capacitor 5-level inverter power circuit

Table 2.2 Flying-capacitor 5-level inverter switch states

Output Switch state S� S� S� S S� S� S� S� V��/2 1 1 1 1 0 0 0 0 V��/4 1 1 1 0 1 0 0 0

0 1 1 0 0 1 1 0 0 V��/4 1 0 0 0 1 1 1 0 V��/2 0 0 0 0 1 1 1 1

2.2.1.42.2.1.42.2.1.42.2.1.4 Required components for different topologiesRequired components for different topologiesRequired components for different topologiesRequired components for different topologies

Totally, considering the cost of semiconductors and passive components, converter losses and simplicity of modulation schemes, cascaded H-bridge and diode-clamped inverters are more used in large motor drive applications. Flying capacitor inverters can be used in DC/DC converters since their phase voltage looks like that of a full-bridge phase shift modulated DC/DC converters [23]. In Table 2.3, required components of different N-level topologies discussed till now are brought together [23].


Table 2.3 Required components of multilevel inverters (N-level) form different aspects

Topology A B C D E F g

Cascaded

H-bridge 6(N-1) 0 0

Even:

(3N/2)-

1.5

Even:

(3N/2)-1.5 ��/(N-1) 2N-1

Odd:

(3N/2)-2

Odd:

(3N/2)-2

Diode-

clamped 6(N-1) 6(N-2)

3

(N-1)

(N-2)

N-1 N-1 ��/(N-1) 2N-1

Flying-

capacitor 6(N-1) 0 0 3N-5 �� 1�� 3 � �!"�

#$� ��/(N-1) 2N-1

A: switches (including free-wheeling diodes)

B: required diodes (with different reverse voltages)

C: required diodes (if the same reverse voltage distribution on them is targeted)

D: required capacitors

E: required capacitors (if the same voltage distribution across the capacitors is targeted)

F: maximum voltage applied for each cell/dc link capacitor

G: line-to-line output voltage levels

2.2.2 Asymmetric multilevel inverter

As mentioned earlier, symmetric multilevel inverters are characterized by the fact that the voltages across the different dc link capacitors are equal. One interesting alternative is to have different capacitor voltages. This topology of inverters is known as asymmetric multilevel inverter. Although the focus for this kind of inverters has been mainly addressed in the direction of cascaded H-bridge asymmetric multilevel [14-18], asymmetric inverters can also be derived from diode-clamped and flying-capacitor inverters or a combination of them either [16, 18].

Asymmetric multilevel inverters have the same circuit configuration as symmetric ones. The only difference is the dc link capacitor voltages. Using different dc link voltages in different power cells and application the appropriate switching methods, the number of output voltage levels increases. Therefore, with less number of H-bridge cells, more output voltage levels can be obtained.

In Fig. 2.9 and Fig. 2.10 two types of 9-level symmetric and asymmetric inverters are shown. According to these figures, in the symmetric inverter,


four cells are needed to generate 9-level voltage, whereas in the asymmetric inverter two cells are enough to generate the same number of voltage levels. The operation method of asymmetric inverters will be explained in Section 2.2.2.1.

The number of phase voltage levels in asymmetric multilevel inverter is calculated by equation 2.1:

2. � V�& � 1'&$� �2.1�

where N is the number of inverter cells and ��# is the normalized dc voltage of each cell with respect to the dc link capacitor voltage. This equation can easily be obtained by considering the derivation of asymmetric topology from cascaded symmetric inverter. For example, for the asymmetric inverter shown in Fig. 2.10 the number of output voltage levels is 2.(1+3)+1=9.

It of importance to mention that the switches applied in the symmetric inverter have the same off-state voltage, but in the asymmetric inverter, due to different voltage levels of dc link sources, the size of switches can be different.

dcVdcVdcVdcV aV

Fig. 2.9 9-level symmetric inverter power circuit

dcVdcV3 aV

Fig. 2.10 9-level asymmetric inverter power circuit

2.2.2.12.2.2.12.2.2.12.2.2.1 Inverter states and vInverter states and vInverter states and vInverter states and voltagesoltagesoltagesoltages

In a cascaded H-bridge asymmetric multilevel inverter, each cell has four switching states. Output voltages are: ��, �� and 0 (two times). So, there are three different states with different voltages. If the voltage of �()cell is named �*, this voltage is defined as the following: �* + ,*�-*, ,* / 01, 0, �12 �2.2� where ,* is the switching state and �-* is the cells capacitor voltages.


If multilevel inverter is constituted by N cells, then the output voltage with respect to the neutral point is give by,

�*3 + � �#!

#$� �2.3� From (2.3) it can be seen that the final output voltage is the sum of each cell voltage.

According to the discussion above, a graph is formed and inverter states and output voltages are specified, Fig. 2.11. It is obvious that the starting point of this graph is the neutral point and the voltage is zero in this point. The nodes in this graph indicate the possible voltages for each cell. It is clear from this figure that each cell can generate three voltage levels. Therefore, by applying different dc link voltage levels to different cells and combination of them, more voltage levels can be obtained in the output of inverter terminals. This combination can be done up to the �()cell. Each branch of this graph indicates a switching state of each cell, therefore

each route of these graph shows a switching state of the inverter. It should be mentioned that it is possible for different routes to arrive in a same output voltage.

(a) (b)

Fig. 2.11 Inverter states and output voltages for each phase (a) 9-level symmetric inverter, (b) 9-level asymmetric inverter

2.2.2.22.2.2.22.2.2.22.2.2.2 Cell voltages, switching power and fCell voltages, switching power and fCell voltages, switching power and fCell voltages, switching power and frequencyrequencyrequencyrequency

In the symmetric multilevel inverters, all cells have the same voltages, whereas in asymmetric multilevel inverters different cells may have different voltages. In chapter 4, it will be shown that how the different dc link voltages affects the switching power losses and frequency.

2.3 Hybrid multilevel inverters

In previous sections, symmetric inverters, asymmetric inverters and their characteristics were discussed. In this section these topologies are synthesized and another topology that is called “hybrid multilevel inverter” is derived.


This topology has a simple circuit with high reliability, power quality and efficiency.

According to Section 2.1, in multilevel inverters two topologies are more applied in medium voltage industrial applications especially in electric drives: cascaded H-bridge inverter and diode-clamped inverter. In addition, both topologies have some advantages and disadvantages. In fact, the important matters are compromise in power quality of converter in both line and motor sides, circuit complexity that affects efficiency, reliability and cost of inverter. H-bridge cascaded inverter has excellent input current and output voltage waveforms but it requires many devices to rectify the ac voltage to the dc voltage, many control equipments and complexity multi-pulse transformer design. Diode-clamped multilevel inverter has a simple circuit but needs LC filter to drive the motor.

This compromise can be done by using asymmetric multilevel inverter. Using asymmetric method in cascaded H-bridge inverter increases the number of output voltage levels. As a result, by using an asymmetric multilevel inverter, power semiconductors should withstand high reverse voltage in the off-state. So, if the voltage ratio of cell supplying voltages is selected 3 to 1 or more, the semiconductor switches should not be the same in all cells. In this case, depending on the voltage level, it is suggested that an appropriate switch used. In other words, larger cells which work in higher voltages, transfer high active power and operate in low switching frequencies [16-19]. HV-IGBT or IGCT switches with reverse voltages more than 4.5 kV are used in these cells. IGCT switches works with high reliability; high reverse voltage and low off-state power losses [20-22]; whereas smaller cells which have lower voltages operate in higher switching frequencies. LV-IGBT switches are used in these cells; because this switch operates in high switching frequency and shows good performance in lower voltages.

By combination of IGBT and IGCT in a hybrid asymmetric multilevel inverter, all the advantages of multilevel inverters can be achieved [17, 18]. This inverter is named hybrid since it uses two different types of semiconductor devices. Since, this inverter uses different voltage levels in the dc link capacitors, it can generate more voltage levels in the output and since, it uses two types of semiconductors in each cell, the power losses decreases either. This inverter is shown in Fig. 2.12.

dcVdcV3aV

1S

2S

3S

4S

5S

6S

7S

8S

Fig. 2.12 9-level hybrid asymmetric cascaded H-bridge inverter power circuit


Fig. 2.13 shows the drive power circuit of a 3-phase hybrid asymmetric inverter. The inverter is composed of two parts: IGCT inverter or main inverter and IGBT inverter or sub inverter and they are connected in series in each phase. Usually in hybrid asymmetric multilevel inverters, the ratio of 3 to 1 is used between main and sub inverter capacitors in order to achieve maximum output voltage level; so finally the output phase voltage is 9-level [25].

Fig. 2.13 3-phase 9-level hybrid asymmetric inverter power circuit for drive applications

2.4 Conclusions

In this chapter, conventional topologies of multilevel inverters have been investigated. First, different topologies of multilevel inverters, their advantages and disadvantages have been discussed. Then, based on symmetric multilevel inverter, asymmetric and hybrid multilevel inverter have been derived. Finally, the structure of the hybrid asymmetric multilevel inverter that is appropriate for high power, medium voltage drive applications has been described.


3 Modulation Techniques In many industrial applications, the output voltage of inverters should be

controlled to overcome input voltage changes and meets the need of voltage/frequency control. It is obvious that output voltage harmonics are depended on the selected modulation technique. A high number of semiconductor devices and switching redundancies bring a higher level of complexity in multilevel topologies compared with a two-level inverter. However, this complexity can be used to improve the modulation technique, such as, reducing the switching frequency, minimizing the common-mode voltage or balancing the dc link voltages.

Today, there are many modulation techniques for multilevel applications and they can be classified in two main groups, depending on their switching frequency: 1) fundamental switching frequency, where each inverter has only one commutation per cycle, and 2) high switching frequency, where each inverter has several commutations per cycle. These techniques are shown in Fig. 3.1[14-16] and can be defined as the following:

Fig. 3.1 Conventional modulation techniques in multilevel inverters

• Selective Harmonic Elimination (SHE): In this technique, the switching

angles are computed offline and are calculated in such a way that

arbitrary harmonics, usually low order, up to m-1 harmonics are

eliminated, where m is the number of switching angles. This

modulation operates at a very low switching frequency to reduce the

semiconductor losses. To minimize harmonic distortion and to achieve

adjustable amplitude of the fundamental component, the most

significant low-frequency harmonics are chosen for elimination by

properly selecting angles among different level inverters.

• Space-Vector PWM (SVM): Each multilevel inverter has several

switching states which generate different voltage vectors and can be

used to modulate the reference. In SVM, the reference signal is

generated from its closest signals. Some vectors have redundant

switching states, meaning that they can be generated by more than one

Multi-Level Inverter Modulation Techniques

Fundamental Switching Frequency

Selective Harmonic Elimination (SHE)

High Switching Frequency

Space Vector PWM (SVM)

Carrier-Based PWM


switching state. This feature is used for balance of capacitor voltages.

Multilevel SVM must manage this behavior to optimize the search of

the modulating vectors and apply an appropriate switching sequence.

• Carrier-Based PWM: This highly conventional technique is based on

the comparison of a sinusoidal reference with carrier signals which are

usually selected triangular and modified in phase or vertical positions

to reduce the output voltage harmonic content. Due to simplicity and

popularity of this technique, it will be analyzed in this chapter in

details and will be used as the modulator of the multilevel topologies.

3.1 Carrier based PWM

In this part, first fundamentals of PWM for 2-level converters and its characteristics will be explained. Then, this modulation will be investigated for multilevel inverter applications.

For all of inverters (2-level or multilevel) minimum and maximum values of output voltages will be normalized to -1 and +1 with respect to the input dc voltage. For 2-level inverter which has two states, this is simply understandable, but for multilevel inverters depending on the number of output voltage levels, other states which are equally between the minimum and maximum, will be added.

3.1.1 2-level PWM

Inverter gain can be defined as the ratio between the output ac voltage and the input dc voltage. There are different methods to change the inverter gain. The most effective method to control the gain and the output voltage of inverter is using PWM method in inverters.

Fig. 3.2 shows 2-level PWM fundamentals. In this figure a reference signal which is usually a sinusoidal waveform, is compared with a carrier signal which is usually a triangular waveform. Based on this figure, if we assume that the average output voltage in switching cycle 45 is 6, we have: 4�6� � 4�6� + 456, 4� � 4� + 45 (3.1) where 4� is the switching time where the reference signal is lower than the carrier. 6� is the minimum voltage and is generated by subtraction of reference and carrier signals when the reference is lower than carrier. 4� is the switching time where the reference signal is higher than the carrier and 6� is the maximum voltage and is generated by subtraction of reference and carrier signals when the reference is higher than carrier.

If we solve the above equation for two switching times, 4� and4�, we have: 4� + 78"797:"79 45 , 4� + 78"7:79"7: 45 (3.2) The equation (3.2) shows a linear relation between switching times and average of output voltage.


The previous equations can be rewritten based on duty cycles (;<), i.e. the ratio of conduction times (4<) and total switching period (45): ;< + (=(> , ? + 1,2 (3.3) ;�6� � ;�6� + 6, ;� � ;� + 1 (3.4) ;� + 78"797:"79, ;� + 78"7:79"7: (3.5)

1d 2d

1v

2v

1t 2t

v

carrier

1

reference

0

st Fig. 3.2 PWM modulation fundamentals

From equation 3.5, it can be concluded that duty cycles can be stated as normalized form of average voltages. For example, duty cycle ;� corresponds to average voltage 6@ for mapping A6�, 6�B C A0,1B. Also, according to equation 3.2 switching times can be calculated and detected by using a timer. In addition, desired output voltage can be compared with a linear ramp wave in the switching period. Thus, if desired voltage is higher than ramp, higher level of output voltage is selected; otherwise lower level is selected.

There are different methods to generate modulation signals [27]. All these methods can be presented by similar graphic diagrams: a reference signal is compared to a carrier signal and output state is selected based on which signal is higher at any moment. In selection of carrier and reference signals there are some points which are mentioned below:

• Carrier signal is usually a symmetric triangular wave, but a saw tooth

wave can be used either. Important fact is that the symmetric signal

generates fewer harmonic [27].

• The reference signal can be continuous or sampled synchronous with

carrier signal. The second method usually generates fewer harmonics.

Since today digital controllers are used, this method is preferred [28].

Fig. 3.3 shows an example of 2-level PWM.


(a)

(b)

Fig. 3.3 (a) Reference signal (�DEF) and carrier signal (��GGH#G), (b) output voltage of 2-level PWM

3.1.2 Multilevel PWM

Multilevel PWM is a generalized form of the 2-level PWM, described in the previous section, applied to multilevel inverters. In this part, multilevel PWM, its characteristics and advantages are presented.

Considering 2-level PWM, the average output voltage (6@) is generated by switching of voltages 6�…* in the switching cycle (45). In addition, considering this modulation, to determine switching times, carrier signals are used. According to Fig. 3.2, for each modulation band one carrier signal is needed. Therefore, for an inverter with N output levels, N-1 modulation bands and therefore N-1 carrier signals are needed [28].

Considering 2-level PWM, there are several methods to generate modulation signals. Carrier signals in multilevel applications can be in the form of level-shifted to each other or phase-shifted [23, 27, 30, 31]. In level-shifted PWM, the carrier signals have the same phase and pick-to-pick amplitude and they are in vertical positions to each other. In phase-shifted PWM the phase of each carrier shifts in a proper angle to reduce the harmonic content of the output voltage. The arrangement that is used generally is triangular waveforms which are level-shifted to each other. Some examples of 5-level and 9-level PWM are shown in Fig. 3.4 and Fig. 3.5. In this figures, all the carrier signals have the same frequency, amplitude and phase.

0 0.005 0.01 0.015 0.02-1

0

+1

0 0.005 0.01 0.015 0.02

-1

0

+1


(a)

(b)

Fig. 3.4 5-level inverter: a) reference and carrier signals, b) output voltage

(a)

(b)

Fig. 3.5 9-level inverter: a) reference and carrier signals, b) output voltage

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1


The above PWM technique is called Phase Disposition PWM (PD-PWM). Moreover, the other two modulations are defined in below:

• Alternate Phase Opposition Disposition PWM (APOD-PWM) – each

carrier signal is out of phase with its neighbors by 180°. • Phase opposition Disposition PWM (POD-PWM) – all the carrier

signals above zero are in phase and are 180° out of phase with those

below zero.

In the following, each technique is explained briefly. Also it should be mentioned that depending on the topology of multilevel inverter, the applied modulation may be different.

For description of the three modulation techniques mentioned above, we consider a 5-level symmetric cascaded H-bridge inverter. Also we consider these definitions:

• Amplitude Modulation ratio (K�), defined as K� + LM/L�, where LM is

the amplitude of the reference signal and L� is the pick-to-pick

amplitude of carrier signal. (For a N-level inverter, this ratio is defined

as K� + LM/�� 1�L�.

• Frequency modulation ratio (KN), defined as KN + O�/O7, where O7 is the

reference signal frequency and O� is the carrier signal frequency.

• P angle that the relative phase displacement between the carrier and

the reference signal and in this analysis it is assumed to be zero.

3.1.2.13.1.2.13.1.2.13.1.2.1 Alternate phase opposition dAlternate phase opposition dAlternate phase opposition dAlternate phase opposition disposition (APODisposition (APODisposition (APODisposition (APOD----PWM)PWM)PWM)PWM)

In this modulation, carrier signals are out of phase with their neighbours

by 180° . The voltage at the output of a 5-level inverter which uses APOD-PWM control method is as the following

• The inverter switches to ��/2 if the reference signal is higher than all

of carrier signals.

• The inverter switches to ��/4 if the reference signal is lower than

two above carrier signals and higher than two below carrier signals.

• The inverter switches to ��/4 if the reference signal is lower than

two below carrier signals and higher than two above carrier signals.

• The inverter switches to ��/2 if the reference signal is lower than all of

carrier signals.

Fig. 3.6 shows the APOD-PWM control technique for a 5-level inverter K� + 0.85 and KN + 39. In particular, it can be seen that APOD modulation does not produce a first carrier harmonic. Instead the dominant harmonics are channelled into the sidebands around the first carrier harmonic. Therefore, since only the triple sidebands away from the carrier frequency cancel in a


three phase system, APOD modulation contains some considerable harmonic energy in the line voltage spectrum. In addition, output voltage has quarter-wave symmetry, if KN is even. If KN is odd, then the output waveform has odd symmetry.

(a)

(b)

(c)

(d)

Fig. 3.6 APOD-PWM technique: a) reference and carrier signals, b) output phase voltage waveform, c) Harmonic spectrum of output phase voltage, d) Harmonic spectrum of output line voltage

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Magnitu

de (

pu)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Outp

ut V

olta

ge (

pu)

0 20 40 60 80 100 120 1400

5

10

15

20

25

Harmonic order

Fundamental (50Hz) = 0.8499 , THD= 36.05%

Mag (

% o

f F

undam

enta

l)

0 20 40 60 80 100 120 1400

5

10

15

20

25

Harmonic order


Mag (

% o

f F

undam

enta

l)


3.1.2.23.1.2.23.1.2.23.1.2.2 Phase position dPhase position dPhase position dPhase position disposition PWM (PODisposition PWM (PODisposition PWM (PODisposition PWM (POD----PWM)PWM)PWM)PWM)

In POD-PWM control technique the carrier signals which are above the zero level are in phase and the carrier signals which are below the zero level

are in phase of each other and out of phase by 180° to above signals. Fig. 3.7 shows the POD-PWM technique for a 5-level inverter with K� +0.85 and KN + 39. In POD, the output phase voltage has quarter-wave

symmetry, if KN is even. If KN is odd, then the output waveform has odd symmetry.

In this modulation, dominant harmonics are on the sideband of the first carrier (KN S 1) and the phase voltage harmonic at the carrier frequency is not considerable. Hence, similar to APOD-PWM, POD modulation contains significant harmonics in the line voltage spectrum, especially in the first carrier band. Comparing to APOD, this modulation has more harmonic distribution along the harmonic orders. This is because, as long as both APOD and POD channel the harmonic energy into the carrier sidebands, the APOD technique still places more harmonic energy into the multiples of three away from the carrier multiples than POD. These triple sideband harmonics cancel on a three-phase system, hence improving the performance of the APOD compared to the POD [35].

(a)

(b)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Mag

nitu

de (

pu

)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Ou

tpu

t V

olta

ge

(p

u)


(c)

(d)

Fig. 3.7 POD-PWM technique: a) reference and carrier signals, b) output phase voltage waveform, c) Harmonic spectrum of output phase voltage, d) Harmonic spectrum of output line voltage

3.1.2.33.1.2.33.1.2.33.1.2.3 Phase dPhase dPhase dPhase disposition PWM (PDisposition PWM (PDisposition PWM (PDisposition PWM (PD----PWM)PWM)PWM)PWM)

In PD-PWM modulation, as already shown in Fig. 3.4 and Fig. 3.5, all the carrier signals are in phase.

Fig. 3.8 shows the PD-PWM modulation technique for a 5-level inverter with K� + 0.85 and KN + 39. In this modulation, main harmonics are at the first carrier frequency. In this technique, the odd sidebands around the even carrier multiples, and the even sidebands around the odd carrier harmonics can be easily seen in the output phase voltage spectrum. Also, as with all carrier-based PWM techniques, only the multiples of three away from the carrier multiples cancel in the line voltage. This cancelation is independent of the absolute carrier frequency and proves that integer/triple carrier to fundamental ratios do not affect the harmonic performance of the modulation algorithm [35].

In PD-PWM modulation technique, the major feature of the phase voltage spectrum is the significant first carrier harmonic. This feature gives the PD-PWM excellent line voltage performance, since this carrier harmonic is a common-mode component across the phase voltages of a three phase inverter, and therefore cancels in the output line voltage. Consequently, with concentration of harmonics in the first carrier, the harmonic sidebands which of course do not fully cancel between the three phase legs have less energy [35]. This is in contrast to the APOD- and POD-PWM techniques, which have

0 20 40 60 80 100 120 1400

5

10

15

20

25

Harmonic order


Mag (

% o

f F

undam

enta

l)

0 20 40 60 80 100 120 1400

5

10

15

20

25

Harmonic order


Mag (

% o

f F

undam

enta

l)


considerable harmonics in their line voltage spectra. In addition, when this technique is used, an even KN will lead to both odd and even harmonics in the output phase voltage and in the case of odd KN, the output phase voltage spectrum will only contain odd harmonics.

(a)

(b)

(c)

(d)

Fig. 3.8 PD-PWM technique: a) reference and carrier signals, b) output phase voltage waveform, c) Harmonic spectrum of output phase voltage, d) Harmonic spectrum of output line voltage

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Ma

gnitu

de

(p

u)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Outp

ut

Volt

age (

pu)

0 20 40 60 80 100 120 1400

5

10

15

20

25

30

Harmonic order


Mag (

% o

f F

undam

enta

l)

0 20 40 60 80 100 120 1400

5

10

15

20

25

Harmonic order


Mag (

% o

f F

undam

enta

l)


As for the symmetric multilevel inverter case, APOD-PWM, POD-PWM and PD-PWM modulations can be used in asymmetric multilevel topology. The PD-PWM technique for the 9-level asymmetric inverter shown in Fig. 3.9, the output phase voltage, its harmonic spectrum and line-to-line voltage are shown in Fig 3.9. It is clear from this figure that the harmonic contents are decreased, because the number of voltage levels is increased.

(a)

(b)

(c)

(d)

Fig. 3.9 PD-PWM technique for a 9-level asymmetric inverter: a) reference and carrier signals, b) output phase voltage, c) Harmonic spectrum of output phase voltage, (d) Harmonic spectrum of output

line voltage

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Magnitu

de (pu)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Outp

ut V

olta

ge (pu)

0 20 40 60 80 100 120 1400

5

10

15

20

25

Harmonic order


Ma

g (

% o

f F

un

da

me

nta

l)

0 20 40 60 80 100 120 1400

5

10

15

20

25

Harmonic order


Ma

g (

% o

f F

un

da

me

nta

l)


Fig. 3.10 shows the firing signals of inverter switches shown in Fig. 2.11. Observe that the switches in the IGBT inverter (sub inverter) are turned on and off more frequently than the switches in the IGCT inverter (main inverter).

(a)

(c)

(b)

(d)

Fig. 3.10 Switching signals for 9-level asymmetric inverter: (a) ��, ��, (b) ��, � , (c) ��, ��, (d) ��, �� The output voltage waveforms of the IGBT inverter (solid lines) and IGCT

inverter (dashed lines) can be observed in Fig 3.11. It can be seen that the maximum voltage of IGCT inverter is three times larger than the voltage of the IGBT inverter and by adding these voltages a 9-level voltage waveform is obtained.

Fig. 3.11 output voltages of IGBT inverter (solid lines) and IGCT inverter (dashed lines)

As it was mentioned before, APOD-, POD- and PD-PWM techniques can be used for asymmetric inverter. In asymmetric inverter, harmonic spectrum of output voltage depends on the frequency modulation ratio (KN) that can be odd or even. Fig. 3.13 and 3.14 shows THD of output voltage KN + 24 and

0 0.005 0.01 0.015 0.02-0.5

0

0.5

1

1.5

0 0.005 0.01 0.015 0.02-0.5

0

0.5

1

1.5

0 0.005 0.01 0.015 0.02-0.5

0

0.5

1

1.5

0 0.005 0.01 0.015 0.02-0.5

0

0.5

1

1.5

0 0.005 0.01 0.015 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1


KN + 39 in operating range of 0.8 T K� T 1.6. Total Harmonic Distortion (THD) is defined as below:

VWX73Y(�ZH + [∑ �)�∞)$�� 3.6� where h is the harmonic order.

It is clear that for K� T 0.8 some of carrier signals will not be compared with the reference signal and the firing signal will not be applied to some of switches; in addition using K� ] 1 results in overmodulation and increase of THD.

Fig. 3.12 THD of output voltages for different modulation techniques, (KN + 39�

Fig. 3.13 THD of output voltages for different modulation techniques, (KN + 24�

Moreover it is obvious from Fig. 3.13 and 3.14 that there are very small differences of THDs between modulations for KN + 39, whereas in KN + 24 the differences are considerable. More discussions about even and odd KNs are presented in [25].

All these modulation techniques are classified in the group of pure sinusoidal PWM (SPWM), where the triangular carrier waveforms are compared with a sinusoidal reference known as modulating signal. The other method to improve the gain of pulse width modulator in a multilevel inverter is Switching Frequency Optimal PWM (SFO-PWM). This modulation is similar to previous modulations and applicable for three-phase systems but

0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.60

2

4

6

8

10

12

14

16

18

20

ma

TH

D (%

)

PD-PWM

POD-PWM

APOD-PWM

0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.60

2

4

6

8

10

12

14

16

18

20

ma

TH

D (%

)

PD-PWM

POD-PWM

APOD-PWM


the zero sequence (3rd harmonic) of voltage is injected to each reference signals [29, 30]. This technique calculates the average value of maximum and minimum of instantaneous reference voltages ��, �� , �� and for all the modulation waveforms subtract this value from the reference voltage:

�3NN5H( + ^_`��, �� , �� ^ a��, �� , ��2 , �3.7� ��cde + �� 3NN5H( �3.8� ��cde + �� 3NN5H(, �3.9� ��cde + �� 3NN5H(, �3.10� The analogue circuit to make the reference signal of SFO-PWM is shown in

Fig. 3.14 [30].

Fig. 3.14 Analogue circuit to make the reference signals in SFO-PWM technique

Fig. 3.15 shows the SFO-PWM with K� + 1.15 and KN + 39. Injection of a third-harmonic into the reference waveforms would obviously achieve a 15% increase in modulation index over Sinusoidal PWM before overmodulation nonlinearities occur. It is simply because of the reduced height of the three-phase reference envelope that is achieved by third-harmonic injection [35]. In this technique, the 3rd harmonic is cleared in three-phase system.

(a)

(b)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Magnitu

de (pu)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Time (s)

Outp

ut Volta

ge (pu)


(c)

Fig. 3.15 SFO-PWM technique for a 9-level asymmetric inverter: a) reference and carrier signals, b) output phase voltage waveform, c) output line voltage waveform

Fig. 3.16 shows the harmonic spectrum for phase and line voltages of SFO-PWM. The results indicate that the third-harmonic injection offers minimal harmonic advantage for PWM of multilevel inverters, since the harmonic distribution of line voltage spectrum is not improved significantly. Therefore, this optimization only has the value to increase the available linear modulation region if this is required.

(a)

(b)

Fig. 3.16 SFO-PWM technique for a 9-level asymmetric inverter: a) Harmonic spectrum of output phase voltage, b) Harmonic spectrum of output line voltage

3.2 Conclusion

After full description of different topologies of multilevel inverters in chapter 2, the conventional modulation techniques which are used in these inverters, discussed in this chapter. In this thesis the focus is on the carrier- based PWM. The different operating techniques of this modulation which are

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04-2

-1

0

1

2

Time (s)

Outp

ut V

olta

ge (

pu)

0 20 40 60 80 100 120 1400

5

10

15

20

Harmonic order


Mag (%

of Fundam

enta

l)

0 20 40 60 80 100 120 1400

1

2

3

4

5

Harmonic order

Fundamental (50Hz) = 2 , THD= 7.70%

Mag (%

of Fundam

enta

l)


PD-PWM, APOD-PWM, POD-PWM and the optimized form of these modulations, SFO-PWM, were applied to symmetric and asymmetric multilevel inverters, described briefly and compared with each other. It was shown that the PD-PWM, due to the less THD and less harmonic distortions around the carrier frequency shows better performance than other techniques. Moreover, the injection of third harmonic in the optimized PWM increases the available linear modulation region to reduce the THD in three-phase systems.


4 Drive System and Performance Indexes

As mentioned earlier in this thesis, voltage source inverters have widespread application in medium voltage drives. Fig. 4.1 shows the block diagram of a medium voltage drive that consists of multi-pulse transformer, rectifier, dc link capacitor, inverter and the load. In Table 4.1 an example of commercial medium voltage drives that are manufactured in industry are listed [32, 33]. Note that the semiconductor switches applied in the inverter of these drives are often IGBT or IGCT. The medium voltage drive here selected is the ACS 5000 drive by ABB, which has a cascaded H-bridge inverter and supplies a 9-level phase voltage. This inverter will be compared with a hybrid asymmetric 9-level inverter which uses IGCT switches in the main inverter and IGBT switches in the sub inverter and a 3-level diode-clamped inverter. It should be mentioned that today the voltages of 2.3 kV, 3.3 kV and 4.16 kV are used in medium voltage drives; although in recent years due to development of power semiconductor switches working in the range of 6 kV-7.2 kV, the voltages of 6.2 kV and 6.9 kV are commercially used in medium voltage applications. In this chapter first the converter specifications used in different multilevel topologies, are selected and then performance indexes which are compared in different topologies will be described.

si

3

3

3

3Li

Fig. 4.1 Block diagram of medium voltage drive

4.1 Inverter specification

In this part both the inverter rating and specifications are chosen close to that of commercially available medium voltage applications. Table 4.2 summarizes the basic inverter data for the design of the main power part components. The drive system is designed to supply an induction motor with line-to-line voltage of 4.16 kV, apparent power of 500 kVA, frequency of 50 Hz and power factor 0.85. The modulation technique used in drive system is SFO-PWM, since it shows better harmonic spectrum for 3-phase systems [29].


Table 4.1 Commercial medium voltage drives

Manufacture

Company

Drive

Model

Power

(MVA)

Voltage

(KV) Topology Semiconductor

Robicon Perfect

Harmony 0.3 – 0.31 2.3 – 13.8

Cascaded H-

Bridge MLI LV IGBT

Allen

Bradley

Power Flex

7000 0.15 – 6.7

2.3, 3.3,

4.16, 6.6 CSI IGCT

Siemens

Masterdrive

MV 0.66 – 9.1

2.2, 3.3,

4.16, 6.6

Diode-

Clamped-3L HV IGBT

Masterdrive

ML2 0.66 – 9.1 3.3

Diode-

Clamped-3L IGCT

ABB

ACS 1000 0.3 – 5 2.3, 3.3, 4 Diode-

Clamped-3L IGCT

ACS 5000 5.2 – 2.4 4.16, 6, 6.6,

6.9

Cascaded H-

Bridge MLI IGCT

ACS 6000 3 – 27 3, 3.3 Diode-

Clamped-3L IGCT

Alstom

VDM 5000 1.4 – 7.2 2.3, 3.3, 4.2 VSI-2L IGBT

VDM 6000 0.3 – 8 2.3, 3.3, 4.2 Flying-

Capacitor-3L IGBT

VDM 7000 7 – 9.5 3.3 Diode-

Clamped-3L GTO

General

Electric

Dura-Bilt5

MV 0.3 – 2.4 4.16

Diode-

Clamped-3L IGBT

MV-GP Type

H 0.45 – 7.5 3.3, 4.16

Cascaded H-

Bridge MLI IGBT

4.1.1 Dc-link voltage

The minimum dc-link voltage to achieve an output line-to-line voltage of 4.16 kV using SFO-PWM can be calculated by, ��,f&g + √2 i ��,�,Dfj + √2 i 4.16 kV + 5883 �4.1� To determine the nominal dc-link voltage of the inverter, a voltage reserve

of 8% is assumed (for the imperfections of the real system, control reserve, device voltage drops, etc.) [26], i.e. ��,g + 1.08 i ��,f&g + 1.08 i 5883 V + 6353 V �4.2�


Table 4.2 Basic inverter specification

Inverter line-to-line voltage V��,�,Dfj 4.16 kV

Phase current Imn,�,Dfj 60 A

Apparent inverter output power S 500 kVA

Inverter output frequency fp 0-100Hz

(fp q 100Hz possible depending on topology, ft,fuv, modulation and control scheme)

Inverter efficiency 99%

Nominal dc-link voltage V��,g 6353 V

Modulation SFO-PWM

Carrier frequency ft 450 - 1050 Hz

Maximum junction temperature Tx,fuv (IGBT, IGCT, diode)

125y

4.1.2 Power semiconductor selection

Table 4.3 summarizes the design of the power semiconductors for the inverter specification in Table 4.2 assuming a carrier frequency of ft + 600 Hz in all topologies. The voltage ��3z describes the commutation voltage of the corresponding commutation cells. ��{f@�}}~�� is an index for the maximum voltage that the semiconductor switch can withstand and is defined by the nominal voltage of semiconductor for which a cosmic ray withstand capability of 100 FIT (one FIT is equivalent to one failure in 10� operation hours) [26]. The ratio of ��{f ��{f@�}}~�� ⁄ represents a measure of the device voltage utilization in different topologies.

4.2 Performance indexes

The performance indexes used in the comparative analysis are: THD, first-order distortion factor (DF1), semiconductor power losses and efficiency.

4.2.1 THD

As was mentioned in Chapter 4, the THD of a signal is the sum of the powers of all harmonic frequencies above the fundamental frequency to the power of the fundamental frequency, and it can be calculated as


VWX% + 100�� )��

)$�,�,… �4.3� where �� is the power of fundamental harmonic of the signal analyzed, � is the harmonic order, and �) is the harmonic of order �. Table 4.3 Inverter voltage and semiconductor specifications for a constant inverter power and carrier

frequency (��,�,Dfj + 4.16 ?�; �mn,� ,Dfj + 60 L; � + 500 ?�L; Ot + 600 Hz; Vx,fuv + 125y� TopoTopoTopoTopologylogylogylogy 3L3L3L3L----DC MIDC MIDC MIDC MI 9L9L9L9L----CHB MICHB MICHB MICHB MI

9L9L9L9L----HA MIHA MIHA MIHA MI

Main Inverter

(IGCT)

Sub Inverter

(IGBT-Modules)

Semiconductor Semiconductor Semiconductor Semiconductor devicesdevicesdevicesdevices

FZ200R65KF2

INFINEON

6.5 kV/200 A

BSM200GB170DLC

EUPEC

1.7kV/200A

IGCT5SHX04D4502 /Diode5SDF03D4502

ABB

4.5 kV/340 A

BSM200GB170DLC

EUPEC

1.7 kV/200 A

Nominal dcNominal dcNominal dcNominal dc----link voltage link voltage link voltage link voltage

6353 V 794 V 2382 V 794 V

Rated device Rated device Rated device Rated device voltage voltage voltage voltage

6.5kV IGBT 1.7kV IGBT 4.5kV IGCT 1.7kV IGCT

Commutation Commutation Commutation Commutation voltage voltage voltage voltage

3176 V 794 V 2382 V 794 V

��@�� 3600 V 900 V 2700 V 900 V

��/��@�� 0.88 0.88 0.88 0.88

4.2.2 DF1

In ac motor drive applications, the first distortion factor (DF1) which is the weighted total harmonic distortion (WTHD) is another considerable index [34]. DF1 is a measure of the impact of harmonic frequency on the output voltage.

Considering the voltage harmonic distortion described in 4.2.1, one can state the current harmonic distortion in the same manner by,

VWX# + ��}� � � �)��)$�,�,… �4.4�

Since the current waveform is dependent upon the load impedance, it cannot be predicted or characterized in advance. However, in many applications, such as electrical machines, the load can be characterized by an


inductance (L) with relatively small resistance [35]. In this case, the harmonic current magnitude can be approximated by,

�* � �*a�� a + 2,3,4 �4.5� where �� is the angular frequency of the fundamental component of the current waveform. If DC component do not exist, the THD of current can be stated by,

VWX# + 1�� )� ��)$�,�,… �4.6�

If this expression is normalized with respect to the quantity �� ⁄ � the DF1 becomes defined as

X�1% + 100�� )� �� )$�,�,… �4.7�

It should be mentioned that the inductance L in the normalizing expression is taken to be the total motor leakage inductance (stator plus rotor) in the case of an electrical machine load.

4.2.3 Semiconductor power losses

As mentioned earlier, nowadays dc to ac converters (inverters) are used widely in speed control of induction motors, uninterruptable power supplies, flexible ac transmission systems, dc transmission systems, induction furnaces, etc. Usually a large portion of the cost of the inverter is related to switches used in its construction. So, accurate calculation of semiconductor losses to design a reliable system that uses small switches and has the low power losses leads to decrease the final cost of the inverter.

Although in recent years the semiconductors technology has developed significantly, there is not a specific device that has at the same time low on-state voltage and resistance, large breakdown voltage, fast turn-off and turn-on and large power dissipation capability. So there should be a trade-off between breakdown voltages and on-state losses and for switches a trade-off between on-state losses and switching speeds [16]. By considering these trade-offs, the type of device that is appropriate for a specific application is determined. Semiconductor devices considered in this work were defined from their characteristics and were introduced in 4.1.2. In this part, the method of calculation of power losses based on datasheets of semiconductors is explained.


4.2.3.14.2.3.14.2.3.14.2.3.1 Method of calculation the power lossesMethod of calculation the power lossesMethod of calculation the power lossesMethod of calculation the power losses

The semiconductor power losses can be calculated from the curves �65�( ` �Y3�� and �� ` �Y3��, given in datasheet of each device. In these curves the parameters are defines as [16]: 65�(: the on-state saturation voltage (6�H for the IGBT, 6� for the IGCT and 6d for the diode); �: the switching energy losses in one commutation (�3* for a turn-on commutation, �3NN for a turn-off commutation and �GH� for reverse recovery process)

�Y3��: the load current. These curves are used in Matlab script to calculate power losses. Matlab

uses the mathematical models that represent the functions 65�( � Y3�� and �� Y3�� for each semiconductor. These mathematical models are obtained by using the points extracted from datasheets of each device and using the curve- fitting toolbox (cftool) of Matlab[16]. This toolbox imports the points from an actual curve and finds the simulated curve by using mathematical models to fit the points, exports the fitted curve. After using mathematical models to evaluate the goodness of fit, the quality-of-fit statistics should be examined. In this work Sum of Squares Due to Error (SSE) is examined [36]. This statistic measures the total deviation of the response values from the fit to the response values. It is also called the summed square of residuals and is obtained by [36]:

�� + �� *#$� �4.8�

where n is the number of response values, �� is the response value and �� is the predicted response value. A value closer to 0 indicates that the model has a smaller random error component, and that the fit will be more accurate.

For example, in Fig. 4.2 voltage-current curve of IGBT/BSM200GB170DLC from datasheet and its fitted curve from cftool are shown.

(a)


(b)

Fig. 4.2 Voltage-current curve of IGBT (a) actual curve from datasheet, (b) fitted curve from cftool

The mathematical models found for semiconductor curves used in this work are given by,

IGBT/BSM200GB170DLC [37], 6�H + �2.197. �}.}}��.� ¡¢£ 1.822. �"}.}��.� ¡¢£� �4.9� 6d + �1.456. �}.}}��.� ¡¢£ 1.415. �"}.}��.� ¡¢£� �4.10� �3* + 3.104. �"�. �Y3�� 1.878. �"�. �Y3�� 0.000358. �Y3�� 0.0007119�4.11� �3NN + 0.0003271. �Y3�� 0.0008491 �4.12� �GH� + 1.906. �"�. �Y3�� 1.636. �"�. �Y3�� 0.0005078. �Y3�� 0.000305�4.13�

IGBT/ FZ200R65KF2 [38], 6�H + �3.754. �}.}}��.� ¡¢£ 2.733. �"}.}��.� ¡¢£� �4.14� 6d + �2.437. �}.}}��.� ¡¢£ 2.176. �"}.} � .� ¡¢£� �4.15� �3* + 2.148. �"�. �Y3�� 4.347. �"�. �Y3�� 0.006946. �Y3�� 0.1622 �4.16� �3NN + 0.00593. �Y3�� 0.003563 �4.17� �GH� + 1.311. �"�. �Y3�� 1.207. �"�. �Y3�� 0.00426. �Y3�� 0.07322 �4.18�

IGCT/5SHX04D4502 and diode 5SDF03D4502 [39, 40], 6� + 0.004706. �Y3�� 1.818 �4.19� 6d + 0.006919. �Y3�� 2.419 �4.20� �3* + 2.311. �"�. �Y3�� 0.004573. �Y3�� 0.05617 �4.21� �3NN + 2.311. �"�. �Y3�� 0.004573. �Y3�� 0.05617 �4.22� �GH� + 1.63. �"�. �Y3�� 0.001659. �Y3�� 0.2226 �4.23�


Based on these mathematical models, the conduction and switching losses are calculated for each semiconductor device. The sum of switching and conduction power losses gives the total power losses.

4.2.3.24.2.3.24.2.3.24.2.3.2 Conduction power lossesConduction power lossesConduction power lossesConduction power losses

Conduction power losses are those losses that occur when the semiconductor is conducting current and there will be an on-state voltage on its terminals, which is 6�H for IGBT, 6� for IGCT and 6d for the diode. The conduction power losses are calculated by (4.24) for the main switch and by (4.25) for the diode [16],

¤�3*�¥¦ + 1V5§ ¨ 65�(�4��>©} . Y3��4�. 6�z�¥¦ª�4�. ;4 �4.24�

¤�3*�« + 1V5§ ¨ 6d�4��>©} . Y3��4�. 6�z�¥¦ª�4�. ;4 �4.25�

where, V5§ is the switching cycle and 6�z�¥¦ª�4� is the command signal of switch �¬` that can be 1 or 0. The total conduction power losses are calculated by (4.26), ¤�3*�®¯° + ¤�3*�±²³/±²´ � ¤�3*�« �4.26�

4.2.3.34.2.3.34.2.3.34.2.3.3 Switching power lossesSwitching power lossesSwitching power lossesSwitching power losses

The switching power losses are obtained by knowing turn-on and turn-off energy losses of devices during one period (Vcµ). Therefore, the turn on, turn off and reverse recovery losses are given by (4.27) to (4.29) [16],

¤3* + 1V � �3* ¶ Y3��4�·. O5§ �4.27� ¤3NN + 1V � �3NN ¶ Y3��4�·. O5§ �4.28� ¤GH� + 1V � �GH� ¶ Y3��4�·. O5§ �4.29� The total switching power losses are calculated by (4.30), ¤5§®¯° + ¤3* � ¤3NN � ¤GH� �4.30� The total power losses are the sum of all conduction and switching power

losses and computed by (4.31), ¤Y355 + ¤�3*�®¯° � ¤5§®¯° �4.31�

4.2.4 Efficiency

The efficiency of converter is obtained by (4.32),


¸% + ¤3¹(¤3¹( � ¤Y355 i 100 �4.32� where ¤3¹( is the output power of inverter and ¤Y355 is the power loss of inverter.

4.3 Conclusion

In this chapter, the inverter specifications which consist of the dc link voltage, switching frequencies, and semiconductor devices were described. Moreover, the different terms that will constitute the comparison parameters of different topologies were defined. These quantities which are power losses, THD and DF1, will be used as performance indexes in the next chapter, where the simulation results will be presented.


5 Comparison of Different Multilevel Inverters

In the previous chapters, different topologies, modulation techniques and inverter specifications of multilevel inverters were explained in details. In this chapter first simulation environment where the multilevel inverters are implemented, is presented and then the simulation results are analyzed and compared. It is of importance to mention that in the simulated model the filtering stage between the converter and the machine has not been included.

5.1 Simulation environment

Fig. 5.1 shows an overview of the simulation model utilized in this work. The model includes the following subsystems: inverter blocks which are defined in blue, the 500KVA, 4160V induction motor as the load of inverter which is defined in yellow, and the measurement and scope blocks. The induction motor starts at no-load and ends to full-load at the end of simulation.

Fig. 5.1 Overview of simulation model for medium voltage drive

Fig. 5.2 shows the multilevel inverter block for phase A; the other phases have the same model. This block consists of a hybrid asymmetric 9-level inverter with switching signal generator block to command the switches. This inverter includes two full-bridge converters; the upper full-bridge converter consists of 4 IGBT modules and the lower full-bridge consists of 4 IGCT switches with reverse recovery diodes. These two full-bridge converters are connected in series and connect to one phase of the induction motor.


Fig. 5.2 Hybrid asymmetric multilevel block

Fig. 5.3 shows the switching signal generator block of hybrid asymmetric 9-level inverter. This block consists of reference signals which enter multicarrier PWM blocks. In multicarrier PWM block (see Fig. 5.4), the reference signals are compared with carrier signals and generate pulses which have the values of 0 or 1. Then, the pulses are entered in math operation blocks and generate signals to drive the gate of inverter switches. These switching patterns form a 9-level voltage as the output of inverter.

Fig. 5.3 Switching signal generator block of hybrid asymmetric 9-level inverter


Fig. 5.4 Multicarrier PWM block

Fig. 5.5 shows the cascaded symmetric 5-level inverter block for one phase. This inverter includes two full-bridge converters; both converters consist of 4 IGBT modules. The command signals of switches come from switching signals generator block. The full-bridge converters are connected in series and connect to one phase of the induction motor.

Fig. 5.5 Cascaded symmetric 5-level inverter block

Fig. 5.6 shows the diode-clamped 3-level inverter block for one phase. Each cell consists of 4 HV-IGBT switches with reverse diodes, 2 diodes to block the current path, 2 dc link capacitors to divide the input voltage, a dc voltage source, and the switching signal generator block.


Fig. 5.6 Diode-clamped 3-level inverter block

5.2 Simulation results

The model shown in Fig. 5.1 is simulated for these multilevel inverters:

• Hybrid asymmetric 9-level inverter

• Cascaded symmetric 9-level inverter

• Diode-clamped 3-level inverter

As mentioned in previous chapters, the basis of selection these topologies is comparison of hybrid asymmetric topology with conventional multilevel inverters in medium voltage drive applications.

The comparison for drive system explained in the previous chapter will be made with two methods:

• Comparison in the state of constant carrier frequency (600 Hz)

• Comparison in the state of constant efficiency (99%)

5.2.1 Comparison at constant carrier frequency

According to the previous chapter, conventional medium voltage drives work in carrier frequencies between 450 and 1050 Hz [26]. In this section the carrier frequency of 600 Hz is considered in different topologies. The performance indexes are listed in Table 5.1 and the power losses distributions for each topology are shown in Fig. 5.7.


Table 5.1 Comparison results of multilevel inverters, f� + 600 Hz ComparisonComparisonComparisonComparison Constant Carrier frequency (600 Hz)Constant Carrier frequency (600 Hz)Constant Carrier frequency (600 Hz)Constant Carrier frequency (600 Hz)

TopologiesTopologiesTopologiesTopologies Hybrid Asymmetric

9-Level

Cascaded Symmetric

9-Level

Diode-Clamped

3-Level

Total number of Total number of Total number of Total number of devices/phasedevices/phasedevices/phasedevices/phase

4 IGBT Modules +

4 IGCT/Diodes 16 LV-IGBT Modules

4 HV-IGBT

Modules +

2 Diodes

Number of phaseNumber of phaseNumber of phaseNumber of phase----voltage levelsvoltage levelsvoltage levelsvoltage levels

9 9 3

Number of lineNumber of lineNumber of lineNumber of line----voltage levelsvoltage levelsvoltage levelsvoltage levels

17 17 5

Carrier frequency Carrier frequency Carrier frequency Carrier frequency [Hz][Hz][Hz][Hz]

600 600 600

THD of phaseTHD of phaseTHD of phaseTHD of phase----currcurrcurrcurrent [%]ent [%]ent [%]ent [%]

5.09 5.21 15.36

THD of lineTHD of lineTHD of lineTHD of line----voltage voltage voltage voltage [%][%][%][%]

7.51 7.52 31.6

DF1 of lineDF1 of lineDF1 of lineDF1 of line----

voltage [%]voltage [%]voltage [%]voltage [%] 0.4712 0.4847 10.210

Total power losses Total power losses Total power losses Total power losses [W][W][W][W]

3552 3893 4544

Inverter Efficiency Inverter Efficiency Inverter Efficiency Inverter Efficiency [%][%][%][%]

99.29 99.22 99.09

According to table 5.1 both hybrid asymmetric and cascaded symmetric inverters have the same THD for current and voltage, since they generate the same voltage levels. As compared with the other two topologies, the THD for the diode clamped inverter is about 3 times higher for the current and 3.8 times higher for the voltage. The THD of voltage is higher than current since the load is inductive. Similarly the DF1 for the diode clamped is larger than the DF1 for the hybrid asymmetric and cascaded symmetric inverters. It means that at a constant carrier frequency, the harmonics of the output voltage appear at higher frequencies. Moreover, power losses for hybrid asymmetric are lower, compared both with the cascaded symmetric and the diode clamped inverters. So, considering the power rating of inverters, hybrid asymmetric topology seems to show better performance in saving the energy than two other conventional topologies.


(a)

(b)

(c)

Fig. 5.7 Power losses distribution in constant frequency (600Hz) (a) Hybrid asymmetric 9-level inverter (b) Cascaded symmetric 9-level inverter (c) Diode clamped 3-level inverter

0

200

400

600

800

1000

1200

1400

1600

1800

2000

Cell 1 (IGBT Inverter) Cell 2 (IGCT Inverter)

Po

we

r L

os

se

s [

W]

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As it can be seen in Fig. 5.7.a, in hybrid asymmetric inverter, the IGBT cell has the largest portion of power losses, since this cell operates in the higher switching frequency than IGCT cell, and therefore the switching losses increase. In both of the cells the conduction power losses are the most significant losses of this inverter. It is due to the fact that the carrier frequency is low and all the switching devices commutate at a low switching frequency. Moreover, the RMS currents over the switches in the IGCT and IGBT inverters are 78 A and 72 A, respectively; so, the IGCT inverter has higher conduction losses than the other one. Fig. 5.7.b shows the power losses distribution in cascaded symmetric inverter. In this topology, all the cells operate with the same switching frequency and dc link voltages. Therefore, all cells present approximately the same semiconductor power losses. In the diode clamped inverter, Fig. 5.7.c, the power losses are concentrated in switch 1 and switch 4. This occurs because switch 2 in the positive and switch 3 in the negative half cycles do not commutate to generate the zero voltage level. So, the conduction losses are the major of power losses in these switches. In diodes, most of power losses are related to switching losses, since, as it was mentioned before, these diodes have the function of blocking the current in all the switches commutations.

5.2.2 Comparison at constant efficiency

To evaluate the three topologies for different applications with demanded efficiency, for the second comparison it is assumed that the inverter efficiencies for all of topologies are about ¸ º 99% at a constant inverter power of � + 500 ?�L. This efficiency is typical for state-of-the-art medium voltage applications [26]. Since the conduction losses of switches are dependent upon average values of voltage and current of switches, by controlling the carrier frequencies that affects the switching losses, the efficiency of 99% can be obtained. The performance indexes for this comparison are listed in Table 5.2 and the power losses distributions are shown in Fig. 5.7.

Comparing to the constant frequency state, with increase of the carrier frequencies, the THDs of current and voltage do not change significantly. This fact comes from that the topologies and the output voltage levels are not changed. Instead, since the frequency of the first harmonic band directly affects the DF1, the first distortion factor is decreased. This can be seen especially in hybrid asymmetric topology that by increase of the carrier frequency to 5400 Hz, DF1 is reduced by 93%. In cascaded symmetric with O� + 800 Hz and diode-clamped with O� + 1150 Hz the reductions of DF1 are approximately 79% and 48%. These values of DF1 reveal that the output filter of the diode-clamped and cascaded symmetric inverters will have greater volume, weight, and cost than the filter used in the hybrid asymmetric inverter to obtain the same line voltage distortion.


Table 5.2 Comparison results of multilevel inverters, η + 99%

ComparisonComparisonComparisonComparison Equal efficiency (99%)Equal efficiency (99%)Equal efficiency (99%)Equal efficiency (99%)

TopologiesTopologiesTopologiesTopologies Hybrid Asymmetric

9-Level

Cascaded Symmetric

9-Level

Diode-Clamped

3-Level

Total number of Total number of Total number of Total number of devices/phasedevices/phasedevices/phasedevices/phase

4 IGBT Modules +

4 IGCT/Diodes 16 LV-IGBT Modules

4 HV-IGBT

Modules +

2 Diodes

Number of phaseNumber of phaseNumber of phaseNumber of phase----voltage levelsvoltage levelsvoltage levelsvoltage levels

9 9 3

Number of lineNumber of lineNumber of lineNumber of line----voltage levelsvoltage levelsvoltage levelsvoltage levels

17 17 5

Carrier frequency Carrier frequency Carrier frequency Carrier frequency [Hz][Hz][Hz][Hz]

5400 860 1150

THD of phaseTHD of phaseTHD of phaseTHD of phase----current [%]current [%]current [%]current [%]

1.73 5.02 15.84

THD of lineTHD of lineTHD of lineTHD of line----voltage voltage voltage voltage [%][%][%][%]

6.6 6.78 32.3

DF1 of lineDF1 of lineDF1 of lineDF1 of line----

voltage [%]voltage [%]voltage [%]voltage [%] 0.037 0.102 5.338

Total power losses Total power losses Total power losses Total power losses [W][W][W][W]

4897 4999 4982

Inverter Efficiency Inverter Efficiency Inverter Efficiency Inverter Efficiency [%][%][%][%]

99.03 99.03 99.01

On the other hand, considering the power losses distribution in hybrid asymmetric topology, the switching losses are the major of power losses in the cell 1 (IGBT inverter). This increase of switching losses with respect to the previous comparison �f� + 600 Hz� proves that, in hybrid asymmetric topology the carrier frequency affects more the IGBT inverter switching losses than the IGCT inverter, since it works with higher switching frequency. In addition, in the state of operation in the same efficiency in three topologies, the frequency of carrier signals in hybrid asymmetric topology is about 6.2 times of cascaded symmetric and 4.7 times of diode-clamped. It shows the more relevance of this topology to the switching frequency that in practice limits the increase of carrier frequency up to 1000 Hz.


(a)

(b)

(c)

Fig. 5.8 Power losses distribution in equal efficiency (99%) (a) Hybrid asymmetric 9-level inverter (b) Cascaded symmetric 9-level inverter (c) Diode clamped 3-level inverter

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6 Conclusion and Future Work The hybrid asymmetric multilevel inverter, due to its benefits both in load

and line sides is presented as a new topology for industrial applications, especially in medium voltage drives. In recent years, asymmetric multilevel inverters have been considered widely because of the high number of output voltage levels and high reliability with a limited number of needed components.

6.1 Results

In Chapter 2, the conventional voltage source converter, both in 2-level and 3-level configurations were discussed. Then, different topologies of multilevel inverters, their advantages and disadvantages have been explained briefly. The three conventional multilevel inverter topologies are: cascaded symmetric multilevel inverter, diode-clamped multilevel inverter and flying-capacitor multilevel inverter. Afterward the discussion continued on hybrid multilevel inverters and inverter switching states, cells output voltages and switching frequencies. At the end, topology of hybrid asymmetric multilevel inverters has been derived, based on IGBT and IGCT switches.

In Chapter 3, different modulation techniques applied in multilevel inverters presented. The three main techniques are: selective harmonic elimination, carrier based and space vector based PWM. In this thesis, due to wide application of carrier based PWM, this modulation technique was used. Different techniques of PD-, POD-, APOD- and SFO-PWM which are used based on carrier based PWM method, were analyzed from switching frequency and harmonic spectrum points of view.

In Chapter 4, the drive model used in this work for the comparison of the different converter topologies has been described. Different performance indexes that are calculated in comparison of topologies were explained. It was explained that in this work THD, DF1, power losses and efficiencies of different topologies are compared.

In Chapter 5, the simulation environment of hybrid asymmetric and conventional multilevel inverters to drive a medium voltage high power induction motor were described and the comparison between these topologies were analyzed in two conditions; operating in constant frequency and constant efficiency. It was shown that hybrid asymmetric multilevel inverter shows better performance in both conditions than conventional multilevel inverters in all the performance indexes that leads to energy saving and improvement of power quality and reduce in size, weight and volume of its LC filter.

6.2 Future work

Considering that in this thesis the focus was on the carrier based PWM method and this method was applied on multilevel inverters, all the three modulation techniques can be applied in different topologies of multilevel


inverters and analyzed form harmonic spectrum, THDs, switching frequency, application in electric drives, etc. points of view.

In this thesis, the comparison is presented for a drive system of 4.16 kV. This comparison can be done for different voltage levels. Also if the comparison is done from an economical point of view, it gives a better picture in construction and application of hybrid asymmetric topology in industrial applications.

If all of topologies are implemented practically and compared and analyzed with simulation results in this thesis, the accuracy of simulation model can be verified. On the other hand, if a similar simulation conducted in another environment such as PSPICE or PSCAD/EMTDC, results of the two models can be compared and decision on the optimum results can be made.

Another interesting topic that can be studied in the following of this thesis is modeling and control of multilevel inverters in FACTS devices application, HVDC transmission lines and large wind turbine applications.


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