compare performance of 2d and 3d mesh architectures in network-on-chip

8/3/2019 Compare Performance of 2D and 3D Mesh Architectures in Network-On-Chip

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Compare Performance of 2D and 3D MeshArchitectures in Network-On-Chip

Reza Kourdy

Department of Computer EngineeringIslamic Azad University,

Khorramabad Branch, Iran

Mohammad Reza Nouri rad

Department of Computer EngineeringIslamic Azad University,

Khorramabad Branch, Iran

Abstract — The 3Dimentional Network on chip (NoCs) architectures is capable of achieving higher throughput, lower latency,

and lower energy dissipation at the cost of small silicon area overhead. In this paper, we survey the 2d-mesh and 3d-mesh of

NOCs to showing their intrinsic advantages related to each other. These topologies compared with average of propagation

delay, average of hop count and impact of fault in bandwidth utilization.

Index Terms — 3D-NoC (Three-dimensional Network on chip), 3D-IC (Three-dimensional integrated- circuit), MPSoC

(Multiprocessor Systems-on-Chip), IP (intellectual property).

1 INTRODUCTION

Moore's law predicts that by 2008, it will be possible tointegrate over a billion transistors on a single chip. Cur-rent core based on SOC methodologies will not respondto the needs of the billion transistor era. Network on Chip(NOC), a new chip design paradigm concurrently pro-posed by many research groups[1],[2],[3] is expected to bean important architectural choice for future SOCs. Theproposed NOC architectures offer a general but fixedcommunication platform which can be reused for a largenumber of SOC designs. A concept of computer networkin layers based on the classical OSI reference model isused by all of proposed NOC architectures. We predictthat NOC architecture would facilitate reuse at variouslevels of system design, thus reducing the time to designand test. However, NOC research is still in its infancy. Ahigher-level modelling will give us the insight of know-ing more about its architecture. We would use the tool,Network Simulator ns-2 [4],[5] which has been extensive-ly used in the research for design and evaluation of publicdomain computer network, to evaluate various designoptions for NOC architecture, including the design ofrouter, communication protocol, routing algorithms. Thispaper reports some experimental results based on thesimulation of NOC using ns-2. In the following, we give abrief overview of our NOC architecture and introduction

to ns-2. In section II, we describe how various aspects ofour NOC architecture was modelled using ns-2.

As semiconductor technology improves, the number ofprocessing cores integrated on a single chip has conti-nually increased. To connect many cores on a chip, Net-work-on-Chips (NoCs) [6, 7, 8] that introduce a packet-switched network structure have been widely employedinstead of traditional bus-based on-chip interconnects.

The performance bottleneck imposed by on-chip inter-connects in the deep submicron regime of process tech-nology has been widely documented [9], as have the ben-efits of standardization of on-chip communication [10].Implementing a standardized communication architec-

ture such as a packet-switched NoC for massively inte-grated multiprocessor systems provides an abstraction ofthe global interconnection link and can greatly reducedesign effort, potentially at the cost of some area and pos-sibly power and performance penalties. The suitability ofthe NoC as a communication architecture depends on theoverall system; i.e. the number of autonomous function-ing blocks, the degree of parallelism, and area and per-formance requirements dictate its usefulness [12].

2 BACKGROUND

On-chip interconnection is a widely studied research fieldand good overviews are presented [12],[13], which illu-strate the various interconnection schemes available forpresent ICs and emerging Multiprocessor Systems-on-Chip (MPSoC) architectures. A NoC-based interconnec-tion is able to provide an efficient and scalable infrastruc-ture, which is able to handle the increased communica-tion needs.

The network architecture, or topology, describes thephysical organization of the interconnections network. Anetwork topology can be classified as being either director indirect. A node in a network can be a terminal node,which acts as a source and sink for data, a switch that

routes data, or both. In a direct network, every node actsas a terminal node. In an indirect network, a node is ei-ther a terminal or a switch node. The networks shown inFigure 2.7 are direct networks.

A direct network can be redrawn as indirect by re-drawing each node as two nodes and showing the switchand terminal nodes separately. Designers of large-scaleSoCs must be aware of the advantages and disadvantagesof each architecture in order to select an appropriate can-didate for their implementations. The metrics that are ofinterest can be broadly categorized as [14]:

• performance (latency, throughput, cross-sectionbandwidth),

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• energy consumption,• reliability (error detection and/or correction),• scalability,• implementation cost (area).

2.1 Why 3D NoC?

Three-dimensional integrated circuits (3D-ICs) are ca-

pable of achieving better performance, functionality, andpackaging density compared to more traditional planarICs. On the other hand, networks-on-chip (NoCs) are anenabling solution for integrating large numbers of em-bedded cores in a single die. 3D NoC architectures com-bine the benefits of these two new domains to offer anunprecedented performance gain [15].

Technology scaling is causing the energy consumptionof the on-chip network to become an increasingly impor-tant design criteria. The goal of macronetworks is to max-imize performance without regard for energy consump-tion, especially for large scale parallel computers wherethroughput and latency are of primary importance. Ittherefore stands to reason that a straightforward adapta-tion of macronetwork implementations for network-on-chip is not appropriate. The problem faced by chip de-signers is that the design criteria run contrary to oneanother:

• Minimizing the energy consumption and maximiz-ing performance are usually conflicting goals.

• Increased reliability usually means higher complexi-ty, which results in larger area, degraded performance,and higher energy consumption.

Therefore, designing a NoC interconnect requiressearching through a vast multidimensional design space.There are many design parameters that can affect systemperformance and cost, but the design decision that has the

largest impact is the choice of topology. The remainder ofthis section will briefly discuss the basic network topolo-gies that other topologies are derived from.

2.2 Fault ModelThere exist several dimensions in classifying the possiblefault occurrences during the life cycle of an MPSoC. Welist the classification as follows:• Duration In terms of duration, the faults can be classi-fied into transient faults and permanent faults [16]. In thecase of the MPSoC, both types of fault can occur in thechip life cycle. Crash failures are permanent faults which

occur when a tile halts prematurely or a link disconnects,after having behaved correctly until the failure. Transientfaults can be either omission failures, when links losesome messages and tiles intermittently omit to send orreceive, or arbitrary failures (also called Byzantine or ma-licious), when links and tiles deviate arbitrarily from theirspecification, corrupting or even generating spuriousmessages. [17]• Location In general, MPSoC designs consist of two inte-grated parts, the Processing Elements (PEs) and Network-on-Chip (NoC). Faults can occur in both parts. In the casethat a fault occurs in the PEs, the computation results willbe erroneous. Dynamic fault detecting and masking ac-

tions are needed to make sure the erroneous results willnot contaminate the application environment. In the casethat a fault occurs in the communication path, such aslink failure and scrambled messages, a fault-tolerantcommunication protocol suite, including error-resilientcoding schemes, are needed to ensure the reliable deli-very of on-chip messages on top of an unreliable on-chipcommunication substrate.• Time to Failure Faults, can occur throughout the life-time of an IC. Using the point when the chip is packagedand tested as the watershed event, we distinguish be-tween before-shelf faults and after-shelf faults. Currently,chips with before shelf faults, i.e., defects which are dis-covered during testing, are invariably discarded. Onlydies with no discovered defects are shipped out as prod-ucts. With the shrinking feature size, it is becoming in-creasingly difficult to achieve decent yield with reasona-ble cost. The low yield problem will become more acutefor the 90nm technology and beyond.On the other hand, the potential yield of the manufactur-ing process can increase tremendously if some defects on

the die can be tolerated in the IC’s after-shelf life. Staticfault masking and isolation techniques, both hardwareand software based, can be used to use these previouslydeemed “Bad” chips in commercial products, such as PicoChip [18]. For after-shelf faults, dynamic fault detectionand recovery means are needed to ensure the correctfunction of the chip as long as possible. Furthermore,graceful degradation of system performance is necessaryfor some mission-critical Applications.

2.3 Related WorkUp to now NoC designs were limited to two dimen-

sions. But emerging 3D integration technology exhibitstwo major advantages, namely, higher performance andsmaller energy consumption [19]. A survey of the existing3D fabrication technologies is presented by Beyne [20].The survey shows the available 3D interconnection archi-tectures and illustrates the main research issues in currentand future 3D technologies. Through process/integrationtechnology advances, it is feasible to design and manufac-ture NoCs that will expand in the third dimension (3D-NoCs). Thus, it is expected that 3D integration will satisfythe demands of the emerging systems for scaling, per-formance, and functionality. A considerable reduction inthe number and length of global interconnect using 3Dintegration is expected [21].

3 NETWORK AND SYSTEM ARCHITECTURE

One of the widely used NoC topologies is the Mesh archi-tecture. We analyse the performance of a Mesh-basedNoC in presence of permanent faults With IP routingadopted.

3.1 Topology and Hardware ArchitecturesOur NOC is a scalable packet switched communication

platform for single chip design. The NOC architectureconsists of a mesh of switches with some resources. Re-






sources Are Heterogeneous or can be homogeneously. Aresource can be intellectual properties (IPs). Two differentnetwork topologies have simulated namely the 2D meshand 3D mesh. 2D topology is of size 8x8 while the 3DMesh topology built from 4x4x4 routers.

Fig . 1. Two-Dimensional mesh 8*8 Noc.

Fig . 2. . Three-Dimensional Mesh 4*4*4 Noc.

We use nostrum Mesh architecture of 2-dimension 8x8architecture [22], with equal link delay that implementedin real world that shown in Fig .1 and fig .2. The squarenodes stand for IPs and the circle nodes stand forswitches. This topology easily scaled to different sizes.The 3D router used here has a 7x7 crossbar switch,whereas the 2D router uses a 5x5 crossbar switch. Also,each router has a routing table And based on the sourceor destination address, the routing table decides whichlink the outgoing packet should use. The commoncharacteristic of NoC architectures is the constituent IP

cores communicate with each other through switches. Weassume the buffer size in each resource is infinite butfinite in switches. This implies the packet being droppedcannot happen in resources but only take place inswitches [23].

4 SIMULATION FRAMEWORK

The mesh-based 2D and 3D NoCs simulated by NS2 (anetwork simulator). We reduce all parameters as multiplyof 1000 to support the simulation time. To compare ofthese architectures in term of packet forwarding we con-sider the bandwidth between switches is one Mega-bit/Sec. The bandwidth between resources and switchesis ten times bigger than the bandwidth of switches toswitches. We consider the traffic source for each commu-nicated core was UDP, and the bandwidth of cores thatneeds was equal to one Megabit/Sec and the delay ofswitch-to-switch or resource to switch is equal to 10 milli-seconds.

5 EVALUATIONS AND SIMULATION RESULTS

Four parameters communication load, Fault-Tolerant,End-to-End Delay and Hop count consumption are de-fined for evaluation performance of our architectures.

5.1 Throughput and communication load

In this section, the proposed scheme evaluated through si-

mulations in terms of performance. We consider that two

resources 0 and 126 are communicating together that

have the maximum distance. A fault between switches

5 and 7 has occurred at time 1.2. This permanent fault

occurs in places that we have communication, as

shown in fig .3, the communication load has reduced.

Fig . 3. supported bandwidth in 2D and 3D NoC Mesh

5.2 Fault-Tolerant

The faults that occur in NoC have two types as be-

low:

• Permanent Faults.

• Transient Faults.






Depend of the nature of fault that was when and

where tacked place, we consider a permanent fault

that occurs in time 1.0, with three hops distance from

the source switch and transient fault was negligible.

Fig . 4. Lost packets in two architecture.

As shown in fig .4, when a permanent fault occurs incommunication path, the number of lost packets inmentioned architectures was equal to each other.

5.3 End to End Delay

End to end delay is another parameter that we considerfor evaluation performance of these architectures.

Fig . 5. Average end to end delay in two architecture.

As shown in fig .5, the average end to end delay betweenof mentioned cores in 3D-mesh is fewer than 2D-mesharchitecture. This means the transfer rate in 3D-mesh isfaster than 2D-mesh, with equal switches and resources.

5.4 Hop count

In the worst case, which the source and destination nodeshave the maximum distance, for transferring packets in2D topology 16 hops needed while in 3D topology pack-ets are transferring only by 11-hop count. The differenceof average hop count in both architectures has shown infig.6.

Fig . 6. Average hop count in two architecture.

As shown in fig.6, the 3D-mesh has fewer hop count

related 2D-mesh architecture. These hop count has noteffect on fault or bandwidth.

6 CONCLUSIONS AND FUTURE WORK

Through detailed simulation-based analysis of the relia-bility and network performance, we can demonstrate the3D-NoC proposed in this paper could empower highthroughput of data transmission with dramatic hop-Count reduction.

Table 1-Comparison 2D AND 3D NOC

ParameterNOC Improvement

per cent2d-mesh 3d-meshAvg propaga-

tion delay0/220 s 0/150s 31/81%

Avg hopcount

16.00 11.00 31/25%

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compare performance of 2d and 3d mesh architectures in network-on-chip

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