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Combinational Logic

EE 200

Digital Logic Circuit Design

Dr. Abdulaziz Tabbakh

College of Computer Sciences and Engineering

King Fahd University of Petroleum and Minerals

EE 200– Digital Logic Circuit Design – KFUPM slide 2

Outline

Introduction

Combinational Circuits

Analysis Procedure

Design Procedure

Binary Adder-Subtractor

Decimal Adder

Binary Multiplier

Magnitude Comparator

Decoders

Encoders

Multiplixers


Introduction

Logic Circuits

Combinational Sequential

A Combinational circuit consists of logic gates whose outputs

only depend on the current state/value of the inputs.

A sequential circuit employs storage elements along with logic

gates in addition to logic gates

Because the state of the storage elements is a function of

previous inputs, the output of sequential circuits depends on

current and previous input values.


Combinational Circuits

A combinational circuit is a block of logic gates having:

𝑛 inputs: 𝑥1, 𝑥2, … , 𝑥𝑛

𝑚 outputs: 𝑓1, 𝑓2, … , 𝑓𝑚

Logic Gates and wires

Each output is a function of the input variables

Each output is determined from present combination of

inputs

Combination circuit performs operation specified by logic

gates


Analysis Procedure

Starts with logic diagram and ends with a set of Boolean

functions, a truth table, or, an explanation of the circuit

operation.

If the logic diagram to be analyzed is accompanied by a

function name or an explanation of what it is assumed to

accomplish, then the analysis problem reduces to a

verification of the stated function


Analysis Procedure

A. Determine the function that the circuit implements:

1. Make sure that the given circuit is combinational

and not sequential. The diagram of a combinational circuit

has logic gates with no feedback paths or memory

elements .

2. Label all gate outputs that are a function of input variables.

Obtain Boolean function for each gate.

3. Label all gate outputs that are a function of input variables and

previously labeled gates. Obtain Boolean function for each of

these gates.

4. Repeat step (b) until the outputs of the circuit are obtained.

5. Substitute of previously defined variables to obtain the output

Boolean functions in terms of input variables


Example

Determine the simplified Boolean functions for the

outputs F1 and F2 as a function of the four inputs A, B,

and C.

𝐹2 = 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶𝑇1 = 𝐴 + 𝐵 + 𝐶𝑇2 = 𝐴𝐵𝐶𝑇3 = 𝐹2

′𝑇1𝐹1 = 𝑇3+ 𝑇2𝐹1 = 𝐹2

′𝑇1+ 𝐴𝐵𝐶= 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 ′ 𝐴 + 𝐵 + 𝐶 + 𝐴𝐵𝐶= 𝐴′ + 𝐵′ 𝐴′ + 𝐶′ 𝐵′ + 𝐶′ 𝐴 + 𝐵 + 𝐶 + 𝐴𝐵𝐶= 𝐴′ + 𝐵′𝐶′ 𝐴𝐵′ + 𝐴𝐶′ + 𝐵𝐶′ + 𝐵′𝐶 + 𝐴𝐵𝐶= 𝐴′𝐵𝐶′ + 𝐴′𝐵′𝐶 + 𝐴𝐵′𝐶′ + 𝐴𝐵𝐶


Analysis Procedure

To obtain the Truth Table from the Logic Diagram:

a) Prepare the truth table for n input variables and 2n input

combinations.

b) Label all gate outputs that are a function of input variables. Fill

in the truth table for these outputs.

c) Label all gate outputs that are functions of input variables and

previously labeled gates. Fill in the truth table columns for

these outputs.

d) Repeat step (c) until the columns for all the outputs are

obtained.


Example

Analyze the previous logic circuit by establishing the

truth table for F1 and F2.


Combinational Logic Design Procedure1. Specification

Specify the number of inputs and outputs and assign a symbol to each.

2. Formulation

Convert the specification into truth tables for outputs

3. Logic Minimization

Derive a Boolean function for each output as a function of inputs and

minimize these functions using K-map or Boolean algebra

4. Technology Mapping

Draw a logic diagram using ANDs, ORs, and inverters

Considerations: cost, delays, fan-in, fan-out

5. Verification

Verify the correctness of the design, either manually or using simulation


Example

Designing a BCD to Excess-3 Code Converter

1. Specification

1. Convert BCD code to Excess-3 code.

2. Input: 4-bit BCD code

3. Output: 4-bit Excess-3 code

2. Formulation

1. Done easily with a truth table

2. BCD input: 𝑎, 𝑏, 𝑐, 𝑑

3. Excess-3 output: 𝑤, 𝑥, 𝑦, 𝑧

4. Output is don't care for 1010 to 1111


Example

3. Logic Minimization using K-maps

cd

ab 00 01 11 10

00

01 1 1 1

11 x x x x

10 1 1 x x


Example


cd

ab 00 01 11 10

00 1 1 1

01 1

11 x x x x

10 1 x x


Example


cd

ab 00 01 11 10

00 1 1

01 1 1

11 x x x x

10 1 x x


Example3. Logic Minimization using K-maps

00 01 11 10

00

𝑎𝑏

𝑐𝑑K-map for 𝑤

01

11

10

K-map for 𝑥 K-map for 𝑦 K-map for 𝑧

00 01 11 10 00 01 11 10 00 01 11 10

1

11

11 1 1

XX XX

XX 1

1

1 1 1

XX XX

XX

1

1

XX XX

XX

1

1

XX XX

XX1

1

1

1

Minimal Sum-of-Product expressions:

𝑤 = 𝑎 + 𝑏𝑐 + 𝑏𝑑 , 𝑥 = 𝑏′𝑐 + 𝑏′𝑑 + 𝑏𝑐′𝑑′ , 𝑦 = 𝑐𝑑 + 𝑐′𝑑′ , 𝑧 = 𝑑′

Additional 3-Level Optimizations: extract common term (𝑐 + 𝑑)

𝑤 = 𝑎 + 𝑏(𝑐 + 𝑑) , 𝑥 = 𝑏′ 𝑐 + 𝑑 + 𝑏 𝑐 + 𝑑 ′ , 𝑦 = 𝑐𝑑 + (𝑐 + 𝑑)′


Example

4. Technology Mapping

Draw a logic diagram using ANDs, ORs, and inverters

𝑤 = 𝑎 + 𝑏(𝑐 + 𝑑) , 𝑥 = 𝑏′ 𝑐 + 𝑑 + 𝑏 𝑐 + 𝑑 ′ , 𝑦 = 𝑐𝑑 + (𝑐 + 𝑑)′, 𝑧 = 𝑑′


Example

5. Verification

Can be done manually

Extract output functions from circuit diagram

Find the truth table of the circuit diagram

Match it against the specification truth table

Verification process can be automated

Using a simulator for complex designs


Problem 4.5

Design a combinational circuit with three inputs, x, y, and

z, and three outputs, A, B, and C. When the binary input

is 0, 1, or 2, the binary output is two greater than the

input. When the binary input is 3, 4, 5, 6, or 7, the binary

output is one less than the input.

1. Specifications:

Inputs: 3-bits (x,y,z)

Output: 3-bits (A, B, C)

Input is (0, 1, or 2) the output is two greater than the input

Input is (3, 4, 5, 6, or 7) the output is one less than the input


Problem 4.5

Formulation & Logic Minimization:

X Y Z A B C

0 0 0 0 1 0

0 0 1 0 1 1

0 1 0 1 0 0

0 1 1 0 1 0

1 0 0 0 1 1

1 0 1 1 0 0

1 1 0 1 0 1

1 1 1 1 1 0


Problem 4.5

Circuit Diagram:

B

C


Standard Logic Circuits There are several combinational circuits that are employed extensively in the design

of digital systems.

These circuits are available in integrated circuits and are classified as standard

components. They perform specific digital functions commonly needed in the design

of digital systems.

In this chapter, we introduce the most important standard combinational circuits, such

as

Adders and Subtractors

Comparators

Decoders

Encoders

Multiplexers

These components are available in integrated circuits as medium-scale integration

(MSI) circuits. They are also used as standard cells in complex very largescale

integrated (VLSI) circuits such as application-specific integrated circuits (ASICs).

The standard cell functions are interconnected within the VLSI circuit in the same way

that they are used in multiple-IC MSI design.


Binary Adder-Subtractor

A binary adder–subtractor is a combinational circuit that

performs the arithmetic operations of addition and

subtraction with binary numbers.

A combinational circuit that performs the addition of two

bits is called a Half Adder.

The one that performs the addition of three bits (two

significant bits and a previous carry) is a Full Adder.


Half Adder (HA)

Recall that:

0+0 = 0 and carry of 0

0+1= 1 and carry of 0



Inputs: 2 bits (x, y)

Outputs: 2 bits (Sum, Carry)


Half Adder (HA)

This form is used to show

that two half adders can be

used to construct a full adder.


N-bit Addition

Addition of n-bit binary numbers requires the use of a full

adder

The process of addition proceeds on a bit-by-bit basis,

right to left, beginning with the least significant bit

Include the carry in the addition

0 0 0 1 1 1 0 1

0 0 1 1 0 1 1 0

+

(54)

(29)

(83)

1carry

01234bit position: 567

11 1

0 1 0 1 0 0 1 1


Full Adder (FA)

A full adder is a combinational

circuit that forms the arithmetic

sum of three bits

Specifications:

Inputs: 3 bits (Two of the input

represents the significant bits (x ,

y), and the third bit (z) represents

the carry from the previous stage)

Outputs: 2 bits (Sum (S) and

Carry (C))

Formulation:

Truth Table


Full Adder (FA)

Logic Minimization:


Full Adder (FA)

Circuit Implementation:


Full Adder (FA)

We still can play with the Boolean functions:


OR

Full Adder (FA)

HA HA

x

y

s0

c0

z

S

C


Binary Adder

A binary adder is a digital circuit that produces the arithmetic

sum of two binary numbers.

We can construct it by cascading FAs. We need n-FA for an

n-bit number.

Each FA adds 3 bits: ai, bi, ci, producing: Sum Si and Carry-

out Ci+1

Carry-out of cell i becomes carry-in to cell (i +1)


Example

0 1 0 0 1 1 1 1

0 1 1 0

0 1 1 1 0


Binary Adder

The four-bit adder is a typical example of a standard

component. It can be used in many applications

involving arithmetic operations

Observe that the design of this circuit by the classical

method would require a truth table with 29 = 512 entries

It is possible to obtain a simple and straightforward

implementation by using an iterative method of

cascading a standard function


Carry Propagation

Major drawback of ripple-carry adder is the carry propagation

The carries are connected in a chain through the full adders

This is why it is called a ripple-carry adder

The carry ripples (propagates) through all the full adders

a0

c0

s0

b0a1

s1

b1

c1

a2

s2

b2

c2

a3

s3

b3

c3

c4


Longest Delay Analysis

Suppose the XOR delay is 1 and AND-OR delay is 2

For an N-bit ripple-carry adder, if all inputs are present at once:

1. Most-significant sum-bit delay = 21 +(N – 1) 2

2. Final Carry-out delay = 1 + N 2

a0

c0

s0

b0a1

s1

b1

c1

a2

s2

b2

c2

a3

s3

b3

c3

c42222

1

1


Carry Propagation

How to reduce the Carry Propagation time delay?

An obvious solution for reducing the carry propagation

delay time is to employ faster gates with reduced

delays. However, physical circuits have a limit to their

capability.

Another solution is to increase the complexity of the

equipment in such a way that the carry delay time is

reduced.


Carry Propagation

The most widely used method to reducing the carry

propagation in a parallel binary adder is called the Carry

Lookahead Logic.

𝑃𝑖 = 𝐴𝑖⨁𝐵𝑖 Carry Propagate

𝐺𝑖 = 𝐴𝑖 . 𝐵𝑖 Carry Generate (Ci+1 =1 if Gi=1)

𝑆𝑖 = 𝑃𝑖⨁𝐶𝑖 Output Sum

𝐶𝑖+1 = 𝐺𝑖 + 𝑃𝑖𝐶𝑖 Output Carry


Carry Lookahead Logic Write the Boolean functions for the Carry outputs of each stage:

Note that P’s and G’s are functions of onlys A’s and B’s (inputs)

ALL carries are dependent on the inputs only (C3 does not have to

wait for C2 and C1 to become available; C3 is propagated at the

SAME TIME as C1 and C2).

This SPEED GAIN is traded off with increase in COMPLEXITY

(#gates)

00120121222223

001011000111112

0001

0

CPPPGPPGPGCPGC

CPPGPGCPGPGCPGC

CPGC

carryinputC


Carry Lookahead Logic


4-bit Carry Lookahead Adder

Each sum output

requires two XOR gates.

All output carries are

generated after exactly a

delay through two levels

of gates.

The delay of the carry

lookahead adder is

constant.


Binary Subtractor Subtraction of two n-digit unsigned numbers M-N in binary will

result in M+(2n -N), it is performed as:

M-N = M+(2n -N) = Add M to the 2’s complement of N

If M ≥ N, the sum will produce M-N+2n, 2n is the end carry and is

discarded.

If M < N, the result is 2n –(N-M) which is the 2’s complement of

(N-M). To obtain the answer in a familiar form, take the 2’s

complement of the sum and place a negative sign in front.

The 2’s complement can be obtained by taking the 1’s complement and adding 1 to the least significant pair of bits. The 1’s complement can be implemented with inverters, and a 1 can be added to the sum through the input carry.

Recall also that B 1 = B’ (B can be inverted if Xored with 1), B 0 = B


Binary Subtractor

When M=0 Addition (A+B)

When M=1 Subtraction (A+1’s Complement of B+1)

Can be used to add/subtract unsigned numbers and

signed 2’s complement numbers


Overflow

When two numbers with n digits each are

added/subtracted and the result is a number with n+1

digits, we say that an overflow occurred

Overflow is a problem in digital computers because the

number of bits that hold the number is finite and a result

that contains n+1 bits cannot be accommodated by an n-

bit space.

When two unsigned numbers are added, an overflow is

detected from the end carry out of the most significant

position.

in a 4-bit adder, A=1111, B=0001, A+B=1 0000

S = 0000 , C = 1 Overflow


Carry and Overflow

We can have carry without overflow and vice-versa

Four cases are possible (Examples on 8-bit numbers)

0 1 0 0 0 0 0 0

0 1 0 0 1 1 1 1+

1 0 0 0 1 1 1 1

79

64

143 (-113)

Carry = 0 Overflow = 1

1

1 0 0 1 1 1 0 1

1 1 0 1 1 0 1 0+

0 1 1 1 0 1 1 1

218 (-38)

157 (-99)

119


111

1 1 1 1 1 0 0 0

0 0 0 0 1 1 1 1+

0 0 0 0 0 1 1 1

15

248 (-8)

7


11111

0 0 0 0 1 0 0 0

0 0 0 0 1 1 1 1+

0 0 0 1 0 1 1 1

15

8

23


1


Overflow

In the case of signed numbers:

the leftmost bit always represents the sign

negative numbers are in 2’s-complement form

When two signed numbers are added, the sign bit is

treated as part of the number and the end carry does not

indicate an overflow.

An overflow may occur if the two numbers added are

both positive or both negative.


Overflow

Two signed binary numbers, +70 and +80, are stored in

two eight-bit registers. The range of numbers that each

register can accommodate is from binary +127 to binary

-128.

An overflow condition can be detected by observing the

carry into the sign bit position and the carry out of the

sign bit position.

If these two carries are not equal, an overflow has occurred.


Overflow

If the two binary numbers are considered to be unsigned,

then the C bit detects a carry after addition

If the numbers are considered to be signed, then the V

bit detects an overflow


Decimal Addition

Calculators that perform arithmetic operations directly in the

decimal number system represent decimal numbers in binary

coded form

In BCD adder. When adding two decimal digits with a possible

carry in of one, then the maximum sum is (9+9+1=19)

For binary addition, it is sufficient to consider a pair of

significant bits together with a previous carry.

A decimal adder requires a minimum of 9 inputs and 5

outputs, since four bits are required to code each decimal

digit and the circuit must have an input and output carry.

The following table shows the sum of two BCD codes when

performed in binary and compared to the sum when

performed in BCD. In both cases five outputs are needed.


Decimal Adder (BCD Adder)


Decimal (BCD) Adder

Inspecting the table reveals that a correction in the sum

is needed when the sum is greater than 9. The

correction is adding 6 to the sum.

The BCD adder will then consist of the 4-bit binary

adder. A second 4-bit binary adder is needed to add 6 to

the sum when it is greater than 9.

The required logic circuit needed to detect if correction is

needed can be obtained by inspecting the table. A

second method is to find a simplified expression for the

carry out C of the five variables K, Z8, Z4, Z2, and Z1.

Minterms m20 to m31 are considered don’t care

conditions.


Decimal Adder (BCD Adder)

When C = 1,

Add 0110 to

the binary

sum and

provide an

output carry

for the next

stage.

When C = 0,

Do Nothing!


Decimal (BCD) Adder

Output carry generated from the bottom

adder adder can be ignored, since it supplies

information already available at the output

carry terminal.

A decimal parallel adder that adds n decimal

digits needs n BCD adder stages.

The output carry from one stage must be

connected to the input carry of the next

higher order stage.


Binary Multiplier

When multiplying two binary numbers, A and B, the

multiplicand is multiplied by each bit of the multiplier

starting from the least significant bit.

Each such multiplication forms a partial product.

Successive partial products are shifted one position to

the left.

The final product is obtained from the sum of the partial

products.


Binary Multiplier

• The multiplication of two bits such as A0

and B0 produces a 1 if both bits are 1;

otherwise, it produces a 0.

• This is identical to an AND operation.


Binary Multiplier

For J multiplier bits and K multiplicand bits, we need

(J × K) AND gates

(J – 1) K-bit adders to produce a product of (J + K) bits

Let K=4 and J=3, then we need

12 AND gates

TWO 4-bit adders

we will get a product of 7-bits

B3 B2 B1 B0

A2 A1 A0

A0B3 A0B2 A0B1 A0B0

A1B3 A1B2 A1B1 A1B0

A2B3 A2B2 A2B1 A2B0

C6 C5 C4 C3 C2 C1 C0


Binary Multiplier

B3 B2 B1 B0

A2 A1 A0

A0B3 A0B2 A0B1 A0B0

A1B3 A1B2 A1B1 A1B0

A2B3 A2B2 A2B1 A2B0

C6 C5 C4 C3 C2 C1 C0



A magnitude comparator is a combinational circuit that

compares two unsigned numbers A and B and determines

their relative magnitudes.

Two Inputs:

Unsigned integer A (m-bit number)

Unsigned integer B (m-bit number)

Three outputs:

A > B (GT output)

A = B (EQ output)

A < B (LT output)

Exactly one of the three outputs must be equal to 1

While the remaining two outputs must be equal to 0

m-bit

Magnitude

Comparator

A[m–1:0]m

B[m–1:0]m

GT = A > B

EQ = A = B

LT = A < B



Circuit for comparing two n-bit numbers has 22n entries

in the truth table and becomes too cumbersome, even

with n = 3.

Digital functions that possess an inherent amount of

regularity can usually be designed by means of an

algorithm.


Example: 4-bit Magnitude Comparator

Inputs:

𝐴=𝐴3 𝐴2 𝐴1 𝐴0

𝐵=𝐵3 𝐵2 𝐵1 𝐵0

8 bits in total 256 possible combinations

Not simple to design using conventional K-map techniques

The magnitude comparator can be designed at a higher

level

Let us implement first the 𝐸𝑄 output (𝐴 is equal to 𝐵)

𝐸𝑄=1 ↔ 𝐴3=𝐵3 , 𝐴2=𝐵2 , 𝐴1=𝐵1 , and 𝐴0=𝐵0

Define: 𝐸𝑖=𝐴𝑖𝐵𝑖 + 𝐴𝑖′ 𝐵𝑖′

Therefore, 𝐸𝑄=𝐸3𝐸2𝐸1𝐸0


The Greater Than OutputGiven the 4-bit input numbers: 𝐴 and 𝐵

1. If 𝐴3 > 𝐵3 then 𝐺𝑇 = 1, irrespective of the lower bits of 𝐴 and 𝐵

Define: 𝐺3 = 𝐴3𝐵3′ (𝐴3 = 1 and 𝐵3 = 0)

2. If 𝐴3 = 𝐵3 (𝐸3 = 1), we compare 𝐴2 with 𝐵2

Define: 𝐺2 = 𝐴2𝐵2′ (𝐴2 = 1 and 𝐵2 = 0)

3. If 𝐴3 = 𝐵3 and 𝐴2 = 𝐵2, we compare 𝐴1 with 𝐵1

Define: 𝐺1 = 𝐴1𝐵1′ (𝐴1 = 1 and 𝐵1 = 0)

4. If 𝐴3 = 𝐵3 and 𝐴2 = 𝐵2 and 𝐴1 = 𝐵1, we compare 𝐴0 with 𝐵0

Define: 𝐺0 = 𝐴0𝐵0′ (𝐴0 = 1 and 𝐵0 = 0)

Therefore, 𝐺𝑇 = 𝐺3 + 𝐸3𝐺2 + 𝐸3𝐸2𝐺1 + 𝐸3𝐸2𝐸1𝐺0


The Less Than OutputWe can derive the expression for the 𝐿𝑇 output, similar to 𝐺𝑇

Given the 4-bit input numbers: 𝐴 and 𝐵

1. If 𝐴3 < 𝐵3 then 𝐿𝑇 = 1, irrespective of the lower bits of 𝐴 and 𝐵

Define: 𝐿3 = 𝐴3′ 𝐵3 (𝐴3 = 0 and 𝐵3 = 1)

2. If 𝐴3 = 𝐵3 (𝐸3 = 1), we compare 𝐴2 with 𝐵2

Define: 𝐿2 = 𝐴2′ 𝐵2 (𝐴2 = 0 and 𝐵2 = 1)

3. Define: 𝐿1 = 𝐴1′𝐵1 (𝐴1 = 0 and 𝐵1 = 1)

4. Define: 𝐿0 = 𝐴0′ 𝐵0 (𝐴0 = 0 and 𝐵0 = 1)

Therefore, 𝐿𝑇 = 𝐿3 + 𝐸3𝐿2 + 𝐸3𝐸2𝐿1 + 𝐸3𝐸2𝐸1𝐿0

Knowing 𝐺𝑇 and 𝐸𝑄, we can also derive 𝐿𝑇 = (𝐺𝑇 + 𝐸𝑄)′



XNOR

The unequal outputs can

use the same gates that

are needed to generate

the equal output.


Iterative Magnitude Comparator Design

The Magnitude comparator can also be designed iteratively

4-bit magnitude comparator is implemented using 4 identical

cells

Design can be extended to any number of cells

Comparison starts at least-significant bit

Final comparator output: 𝐺𝑇 = 𝐺𝑇4 , 𝐸𝑄 = 𝐸𝑄4 , 𝐿𝑇 = 𝐿𝑇4

𝐺𝑇3

𝐸𝑄3

𝐿𝑇3

Cell 3

𝐺𝑇4

𝐸𝑄4

𝐿𝑇4

𝐴3 𝐵3

𝐺𝑇2

𝐸𝑄2

𝐿𝑇2

Cell 2

𝐴2 𝐵2

𝐺𝑇1

𝐸𝑄1

𝐿𝑇1

Cell 1

𝐴1 𝐵1

0 = 𝐺𝑇0

1 = 𝐸𝑄0

0 = 𝐿𝑇0

Cell 0

𝐴0 𝐵0


Cell Implementation Each Cell 𝑖 receives as inputs:

Bit 𝑖 of inputs 𝐴 and 𝐵: 𝐴𝑖 and 𝐵𝑖

𝐺𝑇𝑖, 𝐸𝑄𝑖, and 𝐿𝑇𝑖 from cell (𝑖 − 1)

Each Cell 𝑖 produces three outputs:

𝐺𝑇𝑖+1, 𝐸𝑄𝑖+1, and 𝐿𝑇𝑖+1

Outputs of cell 𝑖 are inputs to cell (𝑖 + 1)

Output Expressions of Cell 𝑖

𝐸𝑄𝑖+1 = 𝐸𝑖 𝐸𝑄𝑖 𝐸𝑖 = 𝐴𝑖′𝐵𝑖

′ + 𝐴𝑖𝐵𝑖 (𝐴𝑖 equals 𝐵𝑖)

𝐺𝑇𝑖+1 = 𝐴𝑖 𝐵𝑖′ + 𝐸𝑖 𝐺𝑇𝑖 𝐴𝑖𝐵𝑖

′ (𝐴𝑖 > 𝐵𝑖)

𝐿𝑇𝑖+1 = 𝐴𝑖′𝐵𝑖 + 𝐸𝑖 𝐿𝑇𝑖 𝐴𝑖

′𝐵𝑖 (𝐴𝑖 < 𝐵𝑖)

Third output can be produced for first two: 𝐿𝑇 = (𝐸𝑄 + 𝐺𝑇)′

𝐺𝑇𝑖

𝐸𝑄𝑖

𝐿𝑇𝑖

Cell 𝑖

𝐺𝑇𝑖+1

𝐸𝑄𝑖+1

𝐿𝑇𝑖+1

𝐴𝑖 𝐵𝑖


Decoders

A binary code of n bits is capable of representing up to

2n distinct elements of coded information

A decoder is a combinational circuit that converts binary

information from n input lines to a maximum of 2n unique

output lines.

This is called an n-to-m line decoder. (m < or = 2n )

The output whose value is 1 represents the minterm

equivalent to the binary input.

Each combination of inputs will activate a unique output.

The name decoder is also used in conjunction with other

code converters, such as a BCD-to-seven-segment

decoder.


Example: 3x8 Decoder

The three inputs are decoded into eight outputs, each

representing one of the minterms of the three input variables

A particular application of this decoder is binary-to-octal

conversion. However, it can be used for decoding any three-

bit code to provide eight outputs


3-to-8 Decoder The output whose value is

equal to 1 represents the

minterm equivalent of the

binary number currently

available in the input lines.


Decoders

Some decoders are constructed with NAND gates.

Decoders include one or more enable inputs to control

the circuit operation.

The circuit operates with

complemented outputs and a

complement enable input

0


Decoders

A decoder may operate with complemented or

uncomplemented outputs.

The enable input may be activated with a 0 or with a 1

signal.

Some decoders have two or more enable inputs that must

satisfy a given logic condition in order to enable the circuit.

Decoders with enable inputs can be connected together to

form a larger decoder circuit

two 3-to-8-line decoders with enable inputs connected to form a

4-to-16-line decoder.

A Decoder with an enable input is also called a

Decoder-Demultiplexer.


4-to-16 Decoder

In general, enable inputs are a

convenient feature for

interconnecting two or more

standard components for the

purpose of combining them into a

similar function with more inputs

and outputs


Demultiplexer

Demultiplexer: It is a circuit that receives information

from a single line and directs it to one of 2n output lines.

The selection of a specific output is controlled by the bit

combination of n selection lines.

A demultiplexer (or demux) is a

device that takes a single input

line and routes it to one of

several digital output lines.

A demultiplexer of 2n outputs

has n select lines, which are

used to select which output line

to send the input. A

demultiplexer is also called a

data distributor.

0


Combinational Logic with Decoders

Any Boolean function can be expressed in sum-of-

minterms form

a decoder that generates the minterms of the function, together

with an external OR gate that forms their logical sum, provides a

hardware implementation of the function.

A combinational circuit with n inputs and m outputs can

be implemented with an n-to-2n decoder and m OR

gates.


Example

S(x,y,z) = Σ(1,2,4,7)

C(x,y,z) = Σ(3,5,6,7)


Combinational Logic using Decoders

A function with a long list of minterms requires an OR gate

with a large number of inputs.

A function having a list of k minterms can be expressed in its

complemented form F’ with 2n - k minterms.

If the number of minterms in the function is greater than 2n/2,

then F’ can be expressed with fewer minterms. In such a

case, it is advantageous to use a NOR gate to sum the

minterms of F’. The output of the NOR gate complements this

sum and generates the normal output F.

If NAND gates are used for the decoder, (active-low), then the

external gates must be NAND gates instead of OR gates. This

is because a two-level NAND gate circuit implements a sum-

of-minterms function and is equivalent to a two-level AND–OR

circuit.


Decoder

Construct a 5-to-32-line decoder with four 3-to-8-line

decoders with enable and a 2-to- 4-line decoder. Use

block diagrams for the components


Encoders

An Encoder is a digital circuit that performs the inverse

operation of a Decoder. It has 2n input lines and n output

lines.

It has maximum of 2n input lines and n output lines.

Output lines give the binary code of the input lines.

Only 1 input line should be active at a time.

2n-to-n

Encoder2n Inputs n Outputs


Example: 8-to-3 Encoder

Z = D1 + D3 + D5 + D7

Y = D2 + D3 + D6 + D7

X = D4 + D5 + D6 + D7


Encoder: Limitations

If two inputs are active simultaneously, say when D3 =

D6 = 1, then the output = 111 which doesn't represent

either binary 3 or binary 6

Encoder circuits must establish an input priority to ensure that

only one input is encoded

If ALL Input = 0s ⟹ ALL output = 0s which is the same

output when D0 = 1.

This discrepancy can be resolved by providing one more output

to indicate whether at least one input is equal to 1.


Encoder Application: Positional Encoder

Another common application of Encoder is magnetic positional control as

used on ships navigation or for robotic arm positioning … etc.

Here for example, the angular or rotary position of a compass is converted

into a digital code by a 74LS148 8-to-3 line priority encoder and input to the

systems computer to provide navigational data and an example of a simple

8 position to 3-bit output compass encoder is shown below.

More Info in link below

http://www.electronics-tutorials.ws/combination/comb_4.html

http://www.electronics-tutorials.ws/combination/comb_4.html


Priority Encoder

A priority encoder is an encoder circuit that includes the

priority function.

if two or more inputs are equal to 1 at the same time:

the input having the highest priority will take precedence

A valid bit (v) is introduced at output to indicate the

invalid all 0s input combination


Priority Encoder

1

The condition for output V is an OR

function of all the input variables

V = D0 + D1 + D2 + D3


Multiplexers

A multiplexer (MUX) is a combinational circuit that

selects binary information from one of many input lines

and directs it to a single output line

The selection is performed using selection control lines.

Normally, there are 2n input lines and n selection lines.

A MUX acts as an electronic switch that selects one of

several sources.

The multiplexer acts like an

electronic switch that selects

one of multiple sources


Application of MUX


Example: 2-to-1 MUX

=0

=1


Example: 4-to-1 MUX

I0

I1

I2

I3

Y

S1S0


Multiplexer

A multiplexer is also called a data selector, since it

selects one of many inputs and steers the binary

information to the output line

The AND gates and inverters in the multiplexer resemble

a decoder circuit, and they decode the selection input

lines.

In general, a 2n-to-1-line multiplexer is constructed from

an n-to-2n decoder by adding 2n input lines to it, one to

each AND gate. The outputs of the AND gates are

applied to a single OR gate.


Multi-bit MUX

quadruple 2-to-1-line

multiplexer

Equivalent to 4 parallel

mux’s share a common

selection line

It is viewed as a circuit

that selects one of two 4-

bit sets of data lines


Combinational Logic with MUX’s

RECALL: the AND and INV gates inside the mux

resemble a decoder with additional OR gate.

The minterms of a function are generated in a

multiplexer by the circuit associated with the selection

inputs

We can implement a Boolean function with n inputs with

(n-1)x1 MUX.

Connect the first (n-1) variables to the select lines

The remaining single variable of the function is used for the data

inputs (x, x’, 1, 0)


Example

Consider: F (x, y, z) = ∑(1, 2, 6, 7)


Example

Consider: F (A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)


Three-State Gates

Three-state gates can produce an output of (1, 0, and

high-impedance z)

In high-impedance state

the logic behaves like an open circuit, which means that the

output appears to be disconnected,

the circuit has no logic significance

the circuit connected to the output of the three-state

gate is not affected by the inputs to the gate.


MUX with Three-States Gates

combinational logic - kfupm...to obtain the truth table from the logic diagram: a) prepare the truth...

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