combinational logic circuits

KARMAVEER BHAURAO PATIL POLYTECHNIC,

SATARA

Rayat Shikshan Sanstha’s

Department Of Electronics And Telecommunication Engineering

Combinational Logic Circuits

05/02/2023 Amit Nevase 2

Principles of Digital Techniques

Amit NevaseLecturer,

Department of Electronics & Telecommunication Engineering, Karmaveer Bhaurao Patil Polytechnic, Satara

EJ3G Subject Code: 17320 Second Year Entc


Objectives

The student will be able to:

Understand basic digital circuits.

Understand conversion of number systems.

Implement combinational and sequential

circuits.

Understand logic families, data converters


Teaching & Examination Scheme

Two tests each of 25 marks to be conducted as per the schedule given by MSBTE.

Total of tests marks for all theory subjects are to be converted out of 50 and to be entered in mark sheet under the head Sessional Work (SW).

Teaching Scheme Examination Scheme

TH TU PR PAPERHRS TH PR OR TW TOTAL

03 -- 02 03 100 25# --- 25@ 150


Module I – Number System

Introduction to digital signal, Advantages of Digital System over analog systems (8 Marks)Number Systems: Different types of number systems( Binary,

Octal, Hexadecimal ), conversion of number systems,Binary arithmetic: Addition, Subtraction, Multiplication, Division.Subtraction using 1’s complement and 2’s complement

Codes (4 Marks) Codes -BCD, Gray Code, Excess-3, ASCII codeBCD addition, BCD subtraction using 9’s and 10’ complement

(Numericals based on above topic).


Module II – Logic Gates & Introduction to Logic Families

Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic

Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different

Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter


Module III – Combinational Logic Circuits

Introduction (8 Marks)Standard representation of canonical forms (SOP & POS),

Maxterm and Minterm , Conversion between SOP and POS formsK-map reduction techniques upto 4 variables (SOP & POS form),

Design of Half Adder, Full Adder, Half Subtractor & Full Subtractor using k-Map

Code Converter using K-map: Gray to Binary Binary to Gray Code Converter (upto 4 bit)

IC 7447 as BCD to 7- Segment decoder driver IC 7483 as Adder & Subtractor, 1 Digit BCD AdderBlock Schematic of ALU IC 74181 IC 74381



Necessity, Applications and Realization of following (8 Marks) Multiplexers (MUX): MUX TreeDemultiplexers (DEMUX): DEMUX Tree, DEMUX as DecoderStudy of IC 74151, IC 74155Priority Encoder 8:3, Decimal to BCD EncoderTristate Logic, Unidirectional & Bidirectional buffer ICs: IC 74244

and IC 74245


Module IV – Sequential Logic Circuit

Sequential Circuits (12 Marks)Comparison between Combinational & Sequential circuitsOne bit memory cell: RS Latch- using NAND & NOR Triggering Methods: Edge & Level TriggeringFlip Flops: SR Flip Flop, Clocked SR FF with preset & clear,

Drawbacks of SR FFClocked JK FF with preset & clear, Race around condition in JK FF,

Master Slave JK FFD and T Flip FlopsExcitation Tables of Flip FlopsBlock schematic and function table of IC 7474, IC 7475, IC 74373


Module IV – Sequential Logic Circuit Study of Counters (8 Marks)

Counter: Modulus of Counter, Types of Counters: Asynchronous & Synchronous Counters

Asynchronous Counter/Ripple Counter: 4 Bit Up/Down Counter Synchronous Counter: Excitation Tables of FFs, 3 Bit Synchronous

Counter, its truth table & waveformsBlock schematic and waveform of IC 7490 as MOD-N Counter

Shift Registers (4 Marks) Logic diagram, Truth Table and waveforms of 4 bit shift registers:

SISO, SIPO, PIPO, PISO 4 Bit Universial Shift RegistersApplications of Shift Registers (Logic Diagram & waveforms) of

Ring Counter and Twisted Ring Counter


Module V – Data Converters

Introduction and Necessity of Code Converters (8 Marks)DAC Types & Comparison of weighted resistor type (Mathematical

Derivation) and R-2R Ladder Type DAC (Mathematical Derivation upto 3 variable)

ADC Types & Their Comparison (8 Marks) Single Slope ADC. Dual Slope ADC, SAR ADC IC PCF 8591: 8 Bit ADC-DAC


Module VI – Memories

Principle of Operation & Classification of memory (10 Marks)Organization of memoriesRAM (Static & Dynamic), Volatile and Non-volatileROM (PROM, EPROM, EEPROM)Flash MemoryComparison between EEPROM & Flash

Study of Memory ICs Identification of IC number and their function of following ICs: IC

2716, IC 7481 and IC 6116


Module-IIICombinational Logic

Circuits


Specific Objectives

Realize various digital Circuits using K-map.

Realize various combinational logic circuits.

Use peripheral devices like buffer.



Introduction (8 Marks)Standard representation of canonical forms (SOP &

POS), Maxterm and Minterm , Conversion between SOP and POS forms

K-map reduction techniques upto 4 variables (SOP & POS form), Design of Half Adder, Full Adder, Half Subtractor & Full Subtractor using k-Map

Code Converter using K-map: Gray to Binary Binary to Gray Code Converter (upto 4 bit)



Standard Representation

Any logical expression can be expressed in the

following two forms:

Sum of Product (SOP) Form

Product of Sum (POS) Form


SOP Form

For Example, logical expression given is;

Sum

Product

. . .Y A B BC AC

05/02/2023 18

POS Form

For Example, logical expression given is;

Amit Nevase

( ).( ).( )Y A B B C A C

Sum

Product


Standard or Canonical SOP & POS Forms

We can say that a logic expression is said to be in the standard (or canonical) SOP or POS form if each product term (for SOP) and sum term (for POS) consists of all the literals in their complemented or uncomplemented form.


Standard SOP

Y ABC ABC ABC Each product term consists all the literals


Standard POS

( ).( ).( )Y A B C A B C A B C

Each sum term consists all the literals


Sr. No. Expression Type

1 Non Standard SOP

2 Standard SOP

3 Standard POS

4 Non Standard POS

Examples

Y AB ABC ABC

Y AB AB AB

( ).( ).( )Y A B A B A B

( ).( )Y A B A B C


Conversion of SOP form to Standard SOP

Procedure:1. Write down all the terms.2. If one or more variables are missing in any

product term, expand the term by multiplying it with the sum of each one of the missing variable and its complement .

3. Drop out the redundant terms


Example 1

Convert given expression into its standard SOP form Y AB AC BC

Y AB AC BC

Missing literal is A

Missing literal is B

Missing literal is C

.( ) .( ) .( )Y AB C C AC B B BC A A

Term formed by ORing of missing literal & its complement


Example 1 Continue….

.( ) .( ) .( )Y AB C C AC B B BC A A

Y ABC ABC ABC ABC ABC ABC

Y ABC ABC ABC ABC ABC ABC

Y ABC ABC ABC ABC

Standard SOP form Each product term consists all the literals


Conversion of POS form to Standard POS

Procedure:1. Write down all the terms.2. If one or more variables are missing in any

sum term, expand the term by adding the products of each one of the missing variable and its complement .

3. Drop out the redundant terms


Example 2

Convert given expression into its standard SOP form ( ).( ) ( )Y A B A C B C

Missing literal is A

Missing literal is B

Missing literal is C

( ).( ).( )Y A B CC A C BB B C AA

Term formed by ANDing of missing literal & its complement

( ).( ) ( )Y A B A C B C


Example 2 Continue….

Standard POS form Each sum term consists all the literals

( ).( ).( )Y A B CC A C BB B C AA

( )( ).( )( ).( )( )Y A B C A B C A B C A B C A B C A B C

( )( )( )( )Y A B C A B C A B C A B C

( )( )( )( )Y A B C A B C A B C A B C


Concept of Minterm and Maxterm

Minterm: Each individual term in the standard SOP form is called as “Minterm”.

Maxterm: Each individual term in the standard POS form is called as “Maxterm”.


The concept of minterm and max term allows us to introduce a very convenient shorthand notation to express logic functions


Minterms & Maxterms for 3 variable/literal logic function

Variables Minterms Maxterms

A B C mi Mi

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1ABC m

2ABC m

3ABC m

4ABC m

5ABC m

6ABC m

7ABC m

4A B C M

3A B C M

2A B C M

1A B C M

0A B C M 0ABC m

5A B C M

6A B C M

7A B C M


Minterms and maxterms

Each minterm is represented by mi where i=0,1,2,3,…….,2n-1

Each maxterm is represented by Mi where i=0,1,2,3,…….,2n-1

If ‘n’ number of variables forms the function, then number of minterms or maxterms will be 2n

• i.e. for 3 variables function f(A,B,C), the number of minterms or maxterms are 23=8


Minterms & Maxterms for 2 variable/literal logic function

Variables Minterms Maxterms

A B mi Mi

0 0

0 1

1 0

1 1

0AB m

1AB m

2AB m

3AB m 3A B M

2A B M

1A B M

0A B M


Representation of Logical expression using minterm

Y ABC ABC ABC ABC

m7 m3 m4 m5

7 3 4 5Y m m m m

(3, 4,5,7)Y m

( , , ) (3, 4,5,7)Y f A B C m

Logical Expression

Corresponding minterms

where denotes sum of products

OR


Representation of Logical expression using maxterm

( ).( ).( )Y A B C A B C A B C

M2 M0 M6

2 0 6. .Y M M M

(0,2,6)Y M

Logical Expression

Corresponding maxterms

where denotes product of sum

OR

( , , ) (0,2,6)Y f A B C M


Conversion from SOP to POS & Vice versa

The relationship between the expressions using minters and maxterms is complementary.

We can exploit this complementary relationship to write the expressions in terms of maxterms if the expression in terms of minterms is known and vice versa


Conversion from SOP to POS & Vice versa

For example, if a SOP expression for 4 variable is given by,

Then we can get the equivalent POS expression using the complementary relationship as follows,

(0,1,3,5,6,7,11,12,15)Y m

(2,4,8,9,10,13,14)Y M


Examples

1. Convert the given expression into standard form

Y A BC ABC

2. Convert the given expression into standard form

( ).( )Y A B A C




Maxterm and Minterm , Conversion between SOP and POS formsK-map reduction techniques upto 4 variables (SOP &

POS form), Design of Half Adder, Full Adder, Half Subtractor & Full Subtractor using k-Map

Code Converter using K-map: Gray to Binary, Binary to Gray Code Converter (upto 4 bit)



Karnaugh Map (K-map)

In the algebraic method of simplification, we need to write lengthy equations, find the common terms, manipulate the expressions etc., so it is time consuming work.

Thus “K-map” is another simplification technique to reduce the Boolean equation.


It overcomes all the disadvantages of algebraic simplification techniques.

The information contained in a truth table or available in the SOP or POS form is represented on K-map.



K-map Structure - 2 VariableA & B are variables or inputs0 & 1 are values of A & B2 variable k-map consists of 4 boxes i.e. 22=4


AB 0 1

0

1


K-map Structure - 2 VariableInside 4 boxes we have enter values of Y i.e.

output


AB 0 1

0

1

AB

AB

AB

AB

AB 0 1

0

1

0m 1m

3m2m

K-map & its associated minterms

BB

AA


Relationship between Truth Table & K-map


AB 0 1

0

1

BB

AA

A B Y

0 0 0

0 1 1

1 0 0

1 1 1

0 0

11

BA 0 1

0

1

B B

A

A 0 1

10


K-map Structure - 3 Variable A, B & C are variables or inputs 3 variable k-map consists of 8 boxes i.e. 23=8


ABC

0

1

BCA 00

0

1

01 11 10

ABC 0 1

00

01

11

10


3 Variable K-map & its associated product terms


ABC

0

1

BCA 00

0

1

01 11 10

ABC 0 1

00

01

11

10

00 01 11 10

ABC ABC ABC ABC

ABC ABC ABC ABC

ABC

ABC

ABC ABC ABC

ABC

ABC

ABC

ABC

ABC

ABC

ABC

ABC

ABC

ABC

ABC


3 Variable K-map & its associated mintermsKarnaugh Map (K-map)

ABC

0

1

BCA 00

0

1

01 11 10

ABC 0 1

00

01

11

10

00 01 11 10

0m4m 5m

1m6m2m3m

7m

5m4m6m

7m0m 2m1m 3m

0m 4m5m1m

6m2m3m 7m



ABCD

00

00

01

01 11 10

11

10

CDAB

00

00

01

01 11 10

11

10

K-map Structure - 4 VariableA, B, C & D are variables or inputs4 variable k-map consists of 16 boxes i.e. 24=16



ABCD

00

00

01

01 11 10

11

10

CDAB

00

00

01

01 11 10

11

10

ABCD ABCD ABCD ABCD ABCD

ABCD ABCD ABCD ABCD

ABCD ABCD ABCD ABCD

ABCD ABCD ABCD ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

4 Variable K-map and its associated product terms



m0 m4 m12 m8

m1 m5 m13 m9

m3 m7 m15 m11

m2 m6 m11 m10

ABCD

00

00

01

01 11 10

11

10

m0 m1 m3 m2

m4 m5 m7 m6

m12 m13 m15 m14

m8 m9 m11 m10

CDAB

00

00

01

01 11 10

11

10

4 Variable K-map and its associated minterms


Representation of Standard SOP form expression on K-mapFor example, SOP equation is given as

Y ABC ABC ABC ABC ABC

The given expression is in the standard SOP form. Each term represents a minterm. We have to enter ‘1’ in the boxes corresponding to each minterm as below

1 1 0 0

1 0 1 1

BCA 00

0

1

01 11 10

ABC ABC

ABC

ABC

ABC

BC BC BC BC

A

A


Simplification of K-map

Once we plot the logic function or truth table on K-map, we have to use the grouping technique for simplifying the logic function.

Grouping means the combining the terms in adjacent cells.

The grouping of either 1’s or 0’s results in the simplification of boolean expression.


If we group the adjacent 1’s then the result of simplification is SOP form

If we group the adjacent 0’s then the result of simplification is POS form

Simplification of K-map


Grouping

While grouping, we should group most number of 1’s.

The grouping follows the binary rule i.e we can group 1,2,4,8,16,32,…..…number of 1’s.

We cannot group 3,5,7,………number of 1’sPair: A group of two adjacent 1’s is called as PairQuad: A group of four adjacent 1’s is called as

QuadOctet: A group of eight adjacent 1’s is called as

Octet


Grouping of Two Adjacent 1’s : Pair

A pair eliminates 1 variable

0 0 1 1

0 0 0 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

ABCABC

Y ABC ABC

( )Y AB C C

( 1)Y AB C C


0 0 0 0

1 0 0 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A

0 1 0 0

0 1 0 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

1 1

1 0

BA 0

0

1

1B B

A

A

0 1 1 1

0 0 1 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A



0 1 0 0

0 0 0 0

0 0 0 0

0 1 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB



Possible Grouping of Four Adjacent 1’s : Quad

0 0 0 0

0 0 0 0

0 0 0 0

1 1 1 1

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 0 0

0 1 0 0

0 1 0 0

0 1 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

A Quad eliminates 2 variable



0 0 0 0

1 1 0 0

1 1 0 0

0 0 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 1 0

0 0 0 0

0 0 0 0

0 1 1 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB


05/02/2023 60Amit Nevase


1 0 0 1

0 0 0 0

0 0 0 0

1 0 0 1

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 0 0 0

1 0 0 1

1 0 0 1

0 0 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB




0 0 0 0

0 1 1 1

0 1 1 1

0 0 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 0 0 0

0 1 1 0

0 1 1 0

0 1 1 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB



Possible Grouping of Eight Adjacent 1’s : Octet

0 0 0 0

0 0 0 0

1 1 1 1

1 1 1 1

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 1 0

0 1 1 0

0 1 1 0

0 1 1 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

A Octet eliminates 3 variable


Possible Grouping of Eight Adjacent 1’s : Octet

1 1 1 1

0 0 0 0

0 0 0 0

1 1 1 1

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

1 0 0 1

1 0 0 1

1 0 0 1

1 0 0 1

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

A Octet eliminates 3 variable


Rules for K-map simplification

1. Groups may not include any cell containing a zero.

0

1

AB 0 1

0

1

B

B

AA

0

1 1

AB 0 1

0

1

B

B

AA

Not Accepted Accepted



2. Groups may be horizontal or vertical, but may not be diagonal

0 1

1 0

AB 0 1

0

1

B

B

AA

0 1

1 1

AB 0 1

0

1

B

B

AA




3. Groups must contain 1,2,4,8 or in general 2n cells

1 1

0 1

AB 0 1

0

1

B

B

AA

1 1

0 1

AB 0 1

0

1

B

B

AA


0 1 1 1

0 0 0 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

0 1 1 1

0 0 0 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A



4. Each group should be as large as possible


1 1 1 1

0 0 1 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A

1 1 1 1

0 0 1 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A



5. Each cell containing a one must be in at least one group

0 0 0 1

0 0 1 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A



6. Groups may be overlap

1 1 1 1

0 0 1 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A



7. Groups may wrap around the table. The leftmost cell in a row may be grouped with rightmost cell and the top cell in a column may be grouped with bottom cell

1 0 0 1

1 0 0 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A

1 1 1 1

0 0 0 0

0 0 0 0

1 1 1 1

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB



8. There should be as few groups as possible, as long as this does not contradict any of the previous rules.


1 1 1 1

0 0 1 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A

1 1 1 1

0 0 1 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A


9. A pair eliminates one variable.

10. A Quad eliminates two variables.

11. A octet eliminates three variables



Example 1

For the given K-map write simplified Boolean expression

0 1 1 1

0 0 1 0

ABC 00

0

1

01 11 10AB AB AB AB

C

C


Example 1 continue…..

0 1 1 1

0 0 1 0

ABC 00

0

1

01 11 10AB AB AB AB

C

C

AC

ABBC

Simplified Boolean expression

Y BC AB AC


Example 2

For the given K-map write simplified Boolean expression

1 1 0 1

1 0 0 1

ABC 00

0

1

01 11 10AB AB AB AB

C

C



1 1 0 1

1 0 0 1

ABC 00

0

1

01 11 10AB AB AB AB

C

C

AC B


Y B AC


Example 3

A logical expression in the standard SOP form is as follows;

Minimize it with using the K-map techniqueY ABC ABC ABC ABC


Example 3 continue……

Y ABC ABC ABC ABC

1 0 1 1

0 1 0 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

ABC

AB

AC

Y AC AB ABC



Example 4

A logical expression representing a logic circuit is;

Draw the K-map and find the minimized logical expression

(0,1,2,5,13,15)Y m



(0,1,2,5,13,15)Y m

1 1 0 1

0 1 0 0

0 1 1 0

0 0 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

ABD

ABDACD

Y ABD ACD ABD



Example 5

Minimize the following Boolean expression using K-map ;

( , , , ) (1,3,5,9,11,13)f A B C D m



0 1 1 0

0 1 0 0

0 1 0 0

0 1 1 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

CDBD

f BD CD


( , , , ) (1,3,5,9,11,13)f A B C D m

( )f D B C


Example 6


( , , , ) (4,5,8,9,11,12,13,15)f A B C D m



0 0 0 0

1 1 0 0

1 1 1 0

1 1 1 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

ADAC

f BC AC AD


( , , , ) (4,5,8,9,11,12,13,15)f A B C D m

BC


Example 7


2( , , , ) (0,1,2,3,11,12,14,15)f A B C D m



1 1 1 1

0 0 0 0

1 0 1 1

0 0 1 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

ACDABD

2f AB ABD ACD


AB

2( , , , ) (0,1,2,3,11,12,14,15)f A B C D m


Example 8

Solve the following expression with K-maps;

1. 2.

1( , , ) (0,1,3,4,5)f A B C m

2( , , ) (0,1,2,3,6,7)f A B C m



1( , , ) (0,1,3,4,5)f A B C m 2( , , ) (0,1,2,3,6,7)f A B C m

1 1 1 0

1 1 0 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

0 1 3 2

4 5 7 6

1 1 1 1

0 0 1 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A

0 1 3 2

4 5 7 6

AC

B BA

2f A B


1f AC B



Example 9

Simplify ;

( , , , ) (0,1,4,5,7,8,9,12,13,15)f A B C D m



1 1 0 0

1 1 1 0

1 1 1 0

1 1 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

BDC

f C BD


( , , , ) (0,1,4,5,7,8,9,12,13,15)f A B C D m


Example 10

Solve the following expression with K-maps;

1. 2.

1( , , , ) (0,1,3, 4,5,7)f A B C D m

2( , , ) (0,1,3,4,5,7)f A B C m



1 1 1 0

1 1 1 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

0 1 3 2

4 5 7 6

CB

2f B C


1f AC AD Simplified Boolean expression

1( , , , ) (0,1,3, 4,5,7)f A B C D m 2( , , ) (0,1,3,4,5,7)f A B C m

1 1 0 0

1 1 1 0

0 0 0 0

0 0 0 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

AD

AB

AB

AC


K-map and don’t care conditions

For SOP form we enter 1’s corresponding to the combinations of input variables which produce a high output and we enter 0’s in the remaining cells of the K-map.

For POS form we enter 0’s corresponding to the combinations of input variables which produce a high output and we enter 1’s in the remaining cells of the K-map.


But it is not always true that the cells not containing 1’s (in SOP) will contain 0’s, because some combinations of input variable do not occur.

Also for some functions the outputs corresponding to certain combinations of input variables do not matter.



In such situations we have a freedom to assume a 0 or 1 as output for each of these combinations.

These conditions are known as the “Don’t Care Conditions” and in the K-map it is represented as ‘X’, in the corresponding cell.

The don’t care conditions may be assumed to be 0 or 1 as per the need for simplification



K-map and don’t care conditions - Example

Simplify ;

( , , , ) (1,3,7,11,15) (0, 2,5)f A B C D m d


X 1 1 X

0 X 1 0

0 0 1 0

0 0 1 0

CDAB 00 01 11 10

CD CD CD CD

00AB

01

11

10

AB

AB

AB

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

CDAB

f CD AB AD


K-map and don’t care conditions - Example

( , , , ) (1,3,7,11,15) (0,2,5)f A B C D m d

AD


Half Adder

Half adder is a combinational logic circuit with two inputs and two outputs.

It is a basic building block for addition of two single bit numbers.

Half Adder

A

B

Sum

Carry

Inputs Outputs

05/02/2023 Amit Nevase 100

Half Adder

Input Output

A B Sum (S) Carry (C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Truth Table

05/02/2023 Amit Nevase 101

Half AdderK-map for Sum Output:

0 1

1 0

AB 0 1

0

1

B

B

AA

0 0

0 1

AB 0 1

0

1

B

B

AAK-map for Carry Output:

S AB AB

S A B

C AB

05/02/2023 Amit Nevase 102

Half Adder

Logic Diagram:

AB

S A B

C AB

05/02/2023 Amit Nevase 103

Half AdderLogic Diagram using Basic Gates:A B

S A B

C AB

05/02/2023 Amit Nevase 104

Full Adder

Full adder is a combinational logic circuit with three inputs and two outputs.

Full Adder

A

B

Sum

Carry

Inputs Outputs

Cin

05/02/2023 Amit Nevase 105

Full Adder

Truth TableInputs Outputs

A B Cin Sum (S) Carry (C)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

05/02/2023 Amit Nevase 106

Full Adder

K-map for Sum Output:

S ABC ABC ABC ABC 0 1 0 1

1 0 1 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

ABCABCABCABC

S ABC ABC ABC ABC

( ) ( )S C AB AB C AB AB

Let AB AB X

( ) ( )S C X C X

S C X

XLet A B S C A B

05/02/2023 Amit Nevase 107

Full Adder

K-map for Carry Output:

C AB BC AC 0 0 1 0

0 1 1 1

BCA 00

0

1

01 11 10BC BC BC BC

A

A

BCABAC

05/02/2023 Amit Nevase 108

Full AdderLogic Diagram:A B

S A B C

C AB BC AC

C

05/02/2023 Amit Nevase 109

Full Adder using Half Adders

A

B

C

HA1 HA2S0 S1

C0 C1

Carry

Sum

05/02/2023 Amit Nevase 110

Half Subtractor

Half subtractor is a combinational logic circuit with two inputs and two outputs.

It is a basic building block for subtraction of two single bit numbers.

Half Subtractor

A

B

Difference

Borrow

Inputs Outputs

05/02/2023 Amit Nevase 111

Input Output

A B Difference (D) Borrow (B)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Truth Table

Half Subtractor

05/02/2023 Amit Nevase 112

K-map for Difference Output:

0 1

1 0

AB 0 1

0

1

B

B

AA

0 1

0 0

AB 0 1

0

1

B

B

AAK-map for Borrow Output:

D AB AB

D A B

B AB

Half Subtractor

05/02/2023 Amit Nevase 113

Half Subtractor

Logic Diagram:

AB

D A B

B AB

05/02/2023 Amit Nevase 114

Half SubtractorLogic Diagram using Basic Gates:A B

D A B

B AB

05/02/2023 Amit Nevase 115

Full Subtractor

Full subtractor is a combinational logic circuit with three inputs and two outputs.

Full Subtractor

A

B

Difference

Borrow

Inputs Outputs

Bin

05/02/2023 Amit Nevase 116

Full Subtractor

Truth TableInputs Outputs

A B Bin (C) Difference (D) Borrow (B0)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

05/02/2023 Amit Nevase 117

Full Subtractor

K-map for Difference Output:

D ABC ABC ABC ABC 0 1 0 1

1 0 1 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

ABCABCABCABC

D ABC ABC ABC ABC

( ) ( )D C AB AB C AB AB

Let AB AB X

( ) ( )D C X C X

D C X

XLet A B D C A B

05/02/2023 Amit Nevase 118

Full Subtractor

K-map for Borrow Output:

0B AB BC AC 0 1 1 1

0 0 1 0

BCA 00

0

1

01 11 10BC BC BC BC

A

A

BCABAC

05/02/2023 Amit Nevase 119

Full SubtractorLogic Diagram:A B

D A B C

0B AB BC AC

C

05/02/2023 Amit Nevase 120

Full Subtractor using Half Subtractor

A

B

C

HS1 HS2D0 D1

B0 B1

Borrow

Difference

05/02/2023 Amit Nevase 121







05/02/2023 Amit Nevase 122

Design of Binary to Gray Code Converter

Block Diagram:

Binary to Gray Code

converter

B3

BinaryInputs

GrayOutputs

B2

B1

B0

G3

G2

G1

G0

05/02/2023 Amit Nevase 123


Binary Inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

Binary Inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

Truth Table :

05/02/2023 Amit Nevase 124


K-map for G0:

0 1 0 1

0 1 0 1

0 1 0 1

0 1 0 1

B3B2 00 01 11 10

003 2B B

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

B1B0

3 2B B

3 2B B

3 2B B

1 0B B 1 0B B 1 0B B 1 0B B

1 0B B 1 0B B

0 1 0 1 0G B B B B

0 0 1G B B

05/02/2023 Amit Nevase 125


K-map for G1:

0 0 1 1

1 1 0 0

1 1 0 0

0 0 1 1

B3B2 00 01 11 10

003 2B B

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

B1B0

3 2B B

3 2B B

3 2B B

1 0B B 1 0B B 1 0B B 1 0B B

2 1B B

1 2 1 2 1G B B B B

1 2 1G B B

2 1B B

05/02/2023 Amit Nevase 126


K-map for G2:

0 0 0 0

1 1 1 1

0 0 0 0

1 1 1 1

B3B2 00 01 11 10

003 2B B

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

B1B0

3 2B B

3 2B B

3 2B B

1 0B B 1 0B B 1 0B B 1 0B B

3 2B B

2 3 2 3 2G B B B B

2 3 2G B B

3 2B B

05/02/2023 Amit Nevase 127


K-map for G3:

0 0 0 0

0 0 0 0

1 1 1 1

1 1 1 1

B3B2 00 01 11 10

003 2B B

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

B1B0

3 2B B

3 2B B

3 2B B

1 0B B 1 0B B 1 0B B 1 0B B

3B

3 3G B

05/02/2023 Amit Nevase 128


Logic Diagram:

B3 B2 B1 B0

2 3 2G B B

1 2 1G B B

0 1 0G B B

3G

05/02/2023 Amit Nevase 129

Design of Gray to Binary Code Converter

Block Diagram:

Gray to Binary Code

converter

B3

BinaryOutputsGray

InputsB2

B1

B0

G3

G2

G1

G0

05/02/2023 Amit Nevase 130


Gray Inputs Binary Outputs

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

Gray Inputs Binary Outputs

G3 G2 G1 G0 B3 B2 B1 B0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

Truth Table :

05/02/2023 Amit Nevase 131

K-map for B0:

0 1 0 1

1 0 1 0

0 1 0 1

1 0 1 0

G3G2 00 01 11 10

003 2G G

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

G1G0

3 2G G

3 2G G

3 2G G

1 0G G 1 0GG 1 0G G 1 0G G

0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0B G G GG G G G G G G G G G G G G

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0G G GG G G G G G G GG G G G G

0 3 2 1 0B G G G G


05/02/2023 Amit Nevase 132

K-map for B1:

0 0 1 1

1 1 0 0

0 0 1 1

1 1 0 0

G3G2 00 01 11 10

003 2G G

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

G1G0

3 2G G

3 2G G

3 2G G

1 0G G 1 0GG 1 0G G 1 0G G

1 3 2 1 3 2 1 3 2 1 3 2 1B G G G G G G G G G G G G

1 3 2 1B G G G


05/02/2023 Amit Nevase 133

K-map for B2:

0 0 0 0

1 1 1 1

0 0 0 0

1 1 1 1

G3G2 00 01 11 10

003 2G G

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

G1G0

3 2G G

3 2G G

3 2G G

1 0G G 1 0GG 1 0G G 1 0G G

2 3 2 3 2B G G G G

1 3 2B G G


05/02/2023 Amit Nevase 134

K-map for B3:

0 0 0 0

0 0 0 0

1 1 1 1

1 1 1 1

G3G2 00 01 11 10

003 2G G

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

G1G0

3 2G G

3 2G G

3 2G G

1 0G G 1 0GG 1 0G G 1 0G G

3 3B G


05/02/2023 Amit Nevase 135

Logic Diagram:

G3 G2 G1 G0

2 3 2B G G

1 1 2 3B G G G

3B


0 0 1 2 3B G G G G

05/02/2023 Amit Nevase 136







05/02/2023 Amit Nevase 137

Seven Segment Display

a

b

c

d

e

fg

dp

05/02/2023 Amit Nevase 138

Seven Segment DisplaySegments

Display Number

Seven Segment Displaya b c d e f g

ON ON ON ON ON ON OFF 0

OFF ON ON OFF OFF OFF OFF 1

ON ON OFF ON ON OFF ON 2

ON ON ON ON OFF OFF ON 3

OFF ON ON OFF OFF ON ON 4

ON OFF ON ON OFF ON ON 5

ON OFF ON ON ON ON ON 6

ON ON ON OFF OFF OFF OFF 7

ON ON ON ON ON ON ON 8

ON ON ON ON OFF ON ON 9

05/02/2023 Amit Nevase 139

Types of Seven Segment Display

Common Cathode Display

Common Anode Display

05/02/2023 Amit Nevase 140


+Vcc

R R R R R R R R

a b c d e f g dp

05/02/2023 Amit Nevase 141


+Vcc

RR

RR

RR

RR

a

b

c

def

g

dp

BCD Input

BCD to 7 SegmentDecoder

05/02/2023 Amit Nevase 142


RR R R R R R R

a b c d e f g dp

05/02/2023 143


Amit Nevase

BCD Input

BCD to 7 SegmentDecoder

RR

RR

RR

RR

a

b

c

d

e

f

g

dp

05/02/2023 Amit Nevase 144

BCD to 7 Segment Decoder Driver ICs

Sr. No. IC Number Specifications

1 IC 7446,IC 74246

Active Low open collector outputs, maximum voltage 30 V, maximum current sinking capability 40mA

2IC 7447,IC 74247

Active Low open collector outputs, maximum voltage 15 V, maximum current sinking capability 40mA

3 IC 7448,IC 74248

Active High open collector outputs, Pull up resistor 2kohm, maximum voltage 5.5 V, maximum current sinking capability 6.4mA

05/02/2023 Amit Nevase 145

IC 7447

Pins Description

A,B,C,D BCD Inputs

Active Low Outputs

Lamp Test

Ripple Blanking Input

Blanking Input

Ripple Blanking output

to ga

LT

RBI

BI

RBO

05/02/2023 Amit Nevase 146

- Ripple Blanking Input

For the normal decoding operation, this input should be connected to logic 1.

If RBI is connected to ground, then it switches off the display when BCD inputs corresponding to 0.

For non-zero BCD inputs, the decoder output will be normal and the BCD number will be displayed.

RBI=0 is connected for blanking out the leading zeros in multidigit displays.

RBI

05/02/2023 Amit Nevase 147

– Blanking Input

If BI is connected to 0, then the display will be switched off irrespective of the BCD input.

This feature is used in the multiplexed display in order to save power.

In the non-multiplexed displays this input is permanently connected to Vcc

BI

05/02/2023 Amit Nevase 148

– Ripple Blanking Output

This output is normally at logic 1. But it goes to logic 0 during the zero blanking interval when RBI is forced to a low level.

RBO is used for cascading purpose and it is connected to RBI of the next stage.

RBO

05/02/2023 Amit Nevase 149

- Lamp Test

This pin can be used to check whether all the segments of the display are working properly or not.

If LT is forced low with RBO at logic 1 or open , then all the output terminals will be forced to their active state

LT

05/02/2023 Amit Nevase 150

Circuit Diagram

a

b

c

d

e

fg

dp

R

R

R

R

R

R

R

a

b

cde

f

g

dp

LT

RBI

/BI RBO

Vcc

Gnd

0A1A2A3A

5V

a

b

cde

f

g

Common

1

2

6

7

354

13

12

11

10

9

15

14

16

8

BCDInputs

LSB

MSB

IC 7447

05/02/2023 Amit Nevase 151

Display Configuration – LTS 542

a

b

c

d

e

fg

dp

a b

cde

fg

dp

Common

Common

05/02/2023 Amit Nevase 152

Display Configuration

05/02/2023 Amit Nevase 153






IC 7447 as BCD to 7- Segment decoder driverIC 7483 as Adder & Subtractor, 1 Digit BCD AdderBlock Schematic of ALU IC 74181 IC 74381

05/02/2023 Amit Nevase 154

N – Bit Parallel Adder

The full adder is capable of adding two single digit binary numbers along with a carry input.

But in practice we need to add binary numbers which are much longer than one bit.

To add two n-bit binary numbers we need to use the n-bit parallel adder.

It uses a number of full adders in cascade.The carry output of the previous full adder is

connected to the carry input of the next full adder..

05/02/2023 Amit Nevase 155

N – Bit Parallel Adder

0A1A2A1nA 0B1B2B1nB

0S1S2S1nS

0C inCFA-0FA-1FA-2FA-(n-1)

05/02/2023 Amit Nevase 156

4 – Bit Parallel Adder using full adder

0A1A2A3A 0B1B2B3B

0S1S2S3S

0C inCFA-0FA-1FA-2FA-3

05/02/2023 Amit Nevase 157

IC 7483 4 – Bit Binary Parallel Adder

0A1A2A3A 0B1B2B3B

0S1S2S3S

0C inCFA-0FA-1FA-2FA-3

05/02/2023 Amit Nevase 158

IC 7483 4 – Bit Binary Parallel Adder

Sum Output

IC 7483

0A1A2A3A 0B1B2B3B

0S1S2S3S

0C inC

Carry Output

Carry Input

A Binary number B Binary number

05/02/2023 Amit Nevase 159

Cascading of IC 7483

IC 7483-II

4A5A6A7A 4B5B6B7B

4S5S6S7S

0CinC

Carry Output

Higher nibble of A Binary number

Higher nibble of B Binary number

Sum Output

IC 7483-I

0A1A2A3A 0B1B2B3B

0S1S2S3S

0CinC

Carry Input

Lower nibble of A Binary number

Lower nibble of B Binary number

If we want to add two 8 bit binary numbers using 4 bit binary parallel adder IC 7483, then we have to cascade the two ICs in following way

05/02/2023 Amit Nevase 160

Design of 1 Digit BCD AdderBlock Diagram:

Logic Circuit

IC 7483-I

IC 7483-II

Add 0110 Command

inC0C

inC0C

A BCD no. B BCD no.

3S 2S 1S 0S

3S 2S 1S 0S

05/02/2023 Amit Nevase 161

Design of 1 Digit BCD Adder

As we know BCD addition rules, we understand that the 4 bit BCD adder should consists of following:A 4 bit binary adder to add the given two (4 bit

numbers).A combinational logic circuit to check if sum is

greater than 9 or carry 1.One more 4 bit binary adder to add 0110 to the

invalid BCD sum or if carry is 1

05/02/2023 Amit Nevase 162


Logic Table for design of Logic circuit:Inputs Y

S3 S2 S1 S0

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

Inputs Y

S3 S2 S1 S0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Sum is invalid BCD NumberY=1

05/02/2023 Amit Nevase 163


K-map for Logic circuit:

0 0 0 0

0 0 0 0

1 1 1 1

0 0 1 1

S3s2 00 01 11 10

003 2S S

01

11

10

0 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

S1S0

3 2S S

3 2S S

3 2S S

1 0S S 1 0S S 1 0S S 1 0S S

3 2S S

3 2 3 1Y S S S S

1 3S S

05/02/2023 Amit Nevase 164


IC 7483-I

IC 7483-II

inC0C

inC

0C

A BCD no. B BCD no.

3S 2S 1S 0S

3S 2S 1S 0S

BCD Output Sum

Not used

Carry output

'Y Y

CombinationalLogic Circuit

05/02/2023 Amit Nevase 165

4 Bit Binary Parallel Subtractor using IC 7483

Difference Output

IC 7483

0A1A2A3A 0B1B2B3B

0S1S2S3S

0C1inC Carry

OutputIt adds 1 to 1’s complement of B

A Binary number B Binary number

Vcc 5V

NOT gates for 1’s complement of B

05/02/2023 Amit Nevase 166

IC 7483 as Parallel Adder/Subtractor

Sum or Difference Output

IC 7483

0A1A2A3A

0B1B2B3B

0S1S2S3S

0C

inCCarry Output

Mode SelectM=0 AdditionM=1 Subtraction

A Binary number

B Binary number

M ModeSelect

05/02/2023 Amit Nevase 167






IC 7447 as BCD to 7- Segment decoder driver IC 7483 as Adder & Subtractor, 1 Digit BCD AdderBlock Schematic of ALU IC 74181, IC 74381

05/02/2023 Amit Nevase 168

IC 74181 – Arithmetic Logic Unit

A very popular & widely used combinational circuit is ALU which is capable of performing arithmetic as well as logical operation.

Arithmetic Operating Modes:AdditionSubtractionShift OperationMagnitude Comparison12 other arithmetic operations

05/02/2023 Amit Nevase 169

IC 74181

Logical Function Modes:Exclusive ORComparatorAND, NAND, OR, NOR10 other arithmetic operations

05/02/2023 Amit Nevase 170

IC 74181 – Pin Diagram

05/02/2023 Amit Nevase 171

IC 74181 – Function Table

05/02/2023 Amit Nevase 172

IC 74381 – 4 Bit Arithmetic Logic Unit

Features:Low input loading minimizes drive requirementsPerforms six arithmetic and logic functionsSelectable LOW (clear) and HIGH (preset)

functionsCarry generate and propagate outputs for use with

carry look ahead generator

05/02/2023 Amit Nevase 173

IC 74381 – Pin Configuration

05/02/2023 Amit Nevase 174

IC 74381 – Function Table

05/02/2023 Amit Nevase 175



and IC 74245

05/02/2023 Amit Nevase 176

Multiplexers

Multiplexer is a circuit which has a number of inputs but only one output.

Multiplexer is a circuit which transmits large number of information signals over a single line.

Multiplexer is also known as “Data Selector” or MUX.

05/02/2023 Amit Nevase 177

Necessity of Multiplexers

In most of the electronic systems, the digital data is available on more than one lines. It is necessary to route this data over a single line.

Under such circumstances we require a circuit which select one of the many inputs at a time.

This circuit is nothing but a multiplexer. Which has many inputs, one output and some select lines.

Multiplexer improves the reliability of the digital system because it reduces the number of external wired connections.

05/02/2023 Amit Nevase 178

Advantages of Multiplexers

It reduces the number of wires.So it reduces the circuit complexity and cost.We can implement many combinational

circuits using Mux.It simplifies the logic design.It does not need the k-map and simplification.

05/02/2023 Amit Nevase 179

Applications of Multiplexers

It is used as a data selector to select one out of many data inputs.

It is used for simplification of logic design.It is used in data acquisition system.In designing the combinational circuits.In D to A converters.To minimize the number of connections.

05/02/2023 Amit Nevase 180

Block Diagram of Multiplexer

DataInputs

Select Lines

Outputn:1

Mux

EEnable Input

Y

D0

D1

D2

D3

Dn-1

s0S1S2Sm-1

.

.

.

.

.

. . . .

Output

D0

D1

D2

D3

Dn-1

s0S1S2Sm-1

.

.

.

.

.

. . . .

Fig. General Block Diagram Fig. Equivalent Circuit

05/02/2023 Amit Nevase 181

Relation between Data Input Lines & Select Lines

In general multiplexer contains , n data lines, one output line and m select lines.

To select n inputs we need m select lines such that 2m=n.

05/02/2023 Amit Nevase 182

Types of Multiplexers

2:1 Multiplexer4:1 Multiplexer8:1 Multiplexer16:1 Multiplexer32:1 Multiplexer64:1 Multiplexer and so on…………

05/02/2023 Amit Nevase 183

2:1 Multiplexer

Select Lines

Output

2:1Mux

E

Enable Input

YD0

D1

s

DataInputs

Enable i/p (E)

Select i/p (S)

Output (Y)

0 X 0

1 0 D0

1 1 D1

Block Diagram

Truth Table

05/02/2023 Amit Nevase 184

Realization of 2:1 Mux using gates

S D1D0

Output

EEnable Input

Y

0SD

1SD

S

05/02/2023 Amit Nevase 185

4:1 Multiplexer

Select Lines

Output

4:1Mux

E

Enable Input

Y

D0

D1DataInputs

Enable i/p Select i/p Output

E S1 S0 Y

0 X X 0

1 0 0 D0

1 0 1 D1

1 1 0 D2

1 1 1 D3Block Diagram

Truth Table

D2

D3

S0S1

05/02/2023 Amit Nevase 186

Realization of 4:1 Mux using gates

Output

EEnable Input

Y

1 0 0S S D

S1 S0

1 0 1S S D

1 0 2S S D

1 0 3S S D

D0

D1

D2

D3

05/02/2023 Amit Nevase 187

8:1 Multiplexer

Select Lines

Output

8:1Mux

E

Enable Input

Y

D0

D1

DataInputs

Enable i/p Select i/p

Output

E S2 S1 S0 Y

0 X X X 0

1 0 0 0 D0

1 0 0 1 D1

1 0 1 0 D2

1 0 1 1 D3

1 1 0 0 D4

1 1 0 1 D5

1 1 1 0 D6

1 1 1 1 D7

Block Diagram

Truth Table

D2

D3

S0S2

D4

D5

D6

D7

S1

05/02/2023 Amit Nevase 188

16:1 Multiplexer

Select Lines

Output

16:1Mux

E

Enable Input

Y

D0D1

DataInputs

Block Diagram

D2D3

S0S2

D4D5D6D7

S1

D8D9D10

D11D12D13D14

D15

S3

05/02/2023 Amit Nevase 189

16:1 Multiplexer

Truth Table

Enable Select Lines OutputE S3 S2 S1 S0 Y

0 X X X X 0

1 0 0 0 0 D0

1 0 0 0 1 D1

1 0 0 1 0 D2

1 0 0 1 1 D3

1 0 1 0 0 D4

1 0 1 0 1 D5

1 0 1 1 0 D6

1 0 1 1 1 D7

1 1 0 0 0 D8

1 1 0 0 1 D9

1 1 0 1 0 D10

1 1 0 1 1 D11

1 1 1 0 0 D12

1 1 1 0 1 D13

1 1 1 1 0 D14

1 1 1 1 1 D15

05/02/2023 Amit Nevase 190

Mux Tree

The multiplexers having more number of inputs can be obtained by cascading two or more multiplexers with less number of inputs. This is called as Multiplexer Tree.

For example, 32:1 mux can be realized using two 16:1 mux and one 2:1 mux.

05/02/2023 191

8:1 Multiplexer using 4:1 Multiplexer

Amit Nevase

Select Lines

4:1Mux

E

Y1

D0

D1

D2

D3

S0

S1

Output

4:1Mux

E

D4

D5

D6

D7

S0

S1

S1

S0

S2

Y2

Y

05/02/2023 192

8:1 Multiplexer using 4:1 Multiplexer

Amit Nevase

4:1Mux

E

Y1

D0

D1

D2

D3

S0

S1

4:1Mux

E

D4

D5

D6

D7

S0

S1

S1

S0

S2

Y2

Output

2:1Mux

E

YD0

D1

05/02/2023 Amit Nevase 193

16:1 Mux using 4:1 Mux4:1Mux

D0

D1D2D3

S0S1

4:1Mux

D4

D5D6D7

4:1Mux

D8

D9D10D11

4:1Mux

D12

D13D14D15

S0S1

S0S1

S0S1

S1S0

4:1Mux

S0S1

S2S3

Output

Y

Y1

Y2

Y3

Y4

D0

D1D2D3

05/02/2023 Amit Nevase 194

Realization of Boolean expression using Mux

We can implement any Boolean expression using Multiplexers.

It reduces circuit complexity.It does not require any simplification

05/02/2023 Amit Nevase 195

Example 1

Implement following Boolean expression using multiplexer

( , , ) (0,3,5,6)f A B C m

Since there are three variables, therefore a multiplexer with three select input is required i.e. 8:1 multiplexer is required

The 8:1 multiplexer is configured as below to implement given Boolean expression

05/02/2023 196


Amit Nevase

( , , ) (0,3,5,6)f A B C m

Output

8:1Mux

E

Y

D0

D1

D2

D3

S0S2

D4

D5

D6

D7

S1

A B C

+Vcc

05/02/2023 Amit Nevase 197

Example 2

Implement following Boolean expression using multiplexer

( , , , ) (0, 2,3,6,8,9,12,14)f A B C D m

Since there are four variables, therefore a multiplexer with four select input is required i.e. 16:1 multiplexer is required

The 16:1 multiplexer is configured as below to implement given Boolean expression

05/02/2023 Amit Nevase 198


( , , , ) (0, 2,3,6,8,9,12,14)f A B C D m

Output

16:1Mux

E

Y

D0D1D2D3

S0S2

D4D5D6D7

S1

D8D9D10

D11D12D13D14

D15

S3

A B C

+Vcc

D

05/02/2023 Amit Nevase 199


Necessity, Applications and Realization of following (8 Marks) Multiplexers (MUX): MUX TreeDemultiplexers (DEMUX): DEMUX Tree, DEMUX as

DecoderStudy of IC 74151, IC 74155Priority Encoder 8:3, Decimal to BCD EncoderTristate Logic, Unidirectional & Bidirectional buffer ICs: IC 74244

and IC 74245

05/02/2023 Amit Nevase 200

De-multiplexer

A de-multiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs.

At a time only one output line is selected by the select lines and the input is transmitted to the selected output line.

It has only one input line, n number of output lines and m number of select lines.

05/02/2023 Amit Nevase 201

Block Diagram of De-multiplexer

DataInput

Select Lines

Outputs1:n

De-mux

E

Enable Input

Y0

Y1

Y2

Y3

Yn-1

s0S1S2Sm-1

.

.

.

.

.

. . . .

s0S1S2Sm-1

.

.

.

.

.

. . . .

Fig. General Block Diagram Fig. Equivalent Circuit

DataInput Outputs

Y0

Y1

Y2

Y3

Yn-1

05/02/2023 Amit Nevase 202

Relation between Data Output Lines & Select Lines

In general de-multiplexer contains , n output lines, one input line and m select lines.

To select n outputs we need m select lines such that n=2m.

05/02/2023 Amit Nevase 203

Types of De-multiplexers

1:2 De-multiplexer1:4 De-multiplexer 1:8 De-multiplexer1:16 De-multiplexer1:32 De-multiplexer1:64 De-multiplexer and so on…………

05/02/2023 Amit Nevase 204

1: 2 De-multiplexer

Select Lines

1:2De-mux

E

Enable Input

Y0

Y1

S

DataInput

Block DiagramDin

Enable i/p Select i/p Outputs

E S Y0 Y1

0 X 0 0

1 0 Din 0

1 1 0 Din

Truth Table

05/02/2023 Amit Nevase 205

1:2 De-mux using basic gates

E Din

SS

Y0

Y1

05/02/2023 Amit Nevase 206

1: 4 De-multiplexer

Select Lines

1:4De-mux

E

Enable Input

Y0

Y1DataInput

Block DiagramDin


E S1 S0 Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1 0 0Din 0 0 0

1 0 1 0 Din 0 0

1 1 0 0 0 Din 0

1 1 1 0 0 0 Din

Truth Table

S0S1

Y2Y3

05/02/2023 Amit Nevase 207

1:4 De-mux using basic gates

E Din

1S1S

Y0

Y1

0S0S

Y2

Y3

05/02/2023 Amit Nevase 208

1: 8 De-multiplexer

Select Lines

1:8De-mux

E

Enable Input

Y0

Y1

DataInput

Block Diagram

Din

S0S1

Y2Y3Y4

Y5

Y6Y7

S2

05/02/2023 Amit Nevase 209

1: 8 De-multiplexer


E S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 Din

1 0 0 1 0 0 0 0 0 0 Din 0

1 0 1 0 0 0 0 0 0 Din 0 0

1 0 1 1 0 0 0 0 Din 0 0 0

1 1 0 0 0 0 0 Din 0 0 0 0

1 1 0 1 0 0 Din 0 0 0 0 0

1 1 1 0 0 Din 0 0 0 0 0 0

1 1 1 1 Din 0 0 0 0 0 0

Truth Table

05/02/2023 210

1: 16 De-multiplexer

Amit Nevase

1:16De-mux

E

Enable Input

Y0

DataInput

Block Diagram

Din

S0S1S2

Y1

Y2

Y3

Y4

Y5Y6

Y7

Y8

Y9

Y10Y11

Y12

Y13

Y14

Y15

S3

05/02/2023 Amit Nevase 211

De-mux Tree

Similar to multiplexer we can construct the de-multiplexer with more number of lines using de-multiplexer having less number of lines. This is call as “De-mux Tree”.

05/02/2023 Amit Nevase 212

1:4 De-mux using 1:2 De-mux

Select Lines

1:2De-mux

E

Y0

Y1

S0

DataInput Din

1:2De-mux

E

Y2

Y3

Din

S1

S0

S0

Y0

Y1

Y0

Y1

05/02/2023 Amit Nevase 213

1:16 De-mux using 1:4 De-mux

Y0

Y1Y2Y3

S0S1

S0S1

S0S1

S0S1

1:4De-mux

S0S1

S2S3

Data Input

Y0

S1 S0

Y1Y2Y3

Din

Y4

Y5Y6Y7

Y8

Y9Y10Y11

Y12

Y13Y14Y15

Din

Din

Din

Din

1:4De-mux

1:4De-mux

1:4De-mux

1:4De-mux

05/02/2023 Amit Nevase 214

Decoder

Decoder is a combinational circuit.It converts n bit binary information at its input

into a maximum of 2n output lines.For example, if n=2 then we can design upto

2:4 decoder

05/02/2023 Amit Nevase 215

2:4 Decoder

2:4Decoder

E Enable Input

Y0

Y2

Inputs Block DiagramA

Truth Table

B

Y1

Y3

Enable i/p Data Inputs Outputs

E A B Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

05/02/2023 Amit Nevase 216

De-multiplexer as Decoder

It is possible to operate a de-multiplexer as a decoder.

Let us consider an example of 1:4 de-mux can be used as 2:4 decoder

05/02/2023 Amit Nevase 217

1:4 De-multiplexer as 2:4 Decoder

Select Lines

1:4De-mux

E

Enable Input

Y0

Y1DataInput

Din

S0S1

Y2Y3

1:4De-mux

E Enable Input

Y0

Y2

InputsA

B

Y1

Y3

S1

S0

Din

Vcc

1: 4 De-multiplexer 1: 4 De-multiplexer as 2:4 Decoder

05/02/2023 Amit Nevase 218

Realization of Boolean expression using De-mux

We can implement any Boolean expression using de-multiplexers.

It reduces circuit complexity.It does not require any simplification

05/02/2023 Amit Nevase 219

Example 1

Implement following Boolean expression using de-multiplexer

( , , ) (0,3,5,6)f A B C m

Since there are three variables, therefore a de-multiplexer with three select input is required i.e. 1:8 de-multiplexer is required

The 1:8 de-multiplexer is configured as below to implement given Boolean expression

05/02/2023 220


Amit Nevase

( , , ) (0,3,5,6)f A B C m

+Vcc

1:8De-mux

E

Enable Input

Y0

Y1

DataInput Din

S0S1

Y2Y3Y4

Y5

Y6Y7S2

A B C

Y

05/02/2023 Amit Nevase 221

Example 2

Implement following Boolean expression using de-multiplexer

( , , , ) (0, 2,3,6,8,9,12,14)f A B C D m

Since there are four variables, therefore a de-multiplexer with four select input is required i.e. 1:16 de-multiplexer is required

The 1:16 de-multiplexer is configured as below to implement given Boolean expression

05/02/2023 Amit Nevase 222


( , , , ) (0, 2,3,6,8,9,12,14)f A B C D mA B C

+Vcc

D

1:16De-mux

E

Enable Input

Y0

DataInput Din

S0S1S2

Y1

Y2

Y3

Y4

Y5Y6

Y7

Y8

Y9

Y10Y11

Y12

Y13

Y14

Y15S3

Y

05/02/2023 Amit Nevase 223



and IC 74245

05/02/2023 Amit Nevase 224

Multiplexer ICs

IC Number Description Output

IC 74157 Quad 2:1 Mux Same as input

IC 74158 Quad 2:1 Mux Inverted Output

IC 74153 Dual 4:1 Mux Same as input

IC 74352 Dual 4:1 Mux Inverted Output

IC 74151 8:1 Mux Inverted Output



05/02/2023 Amit Nevase 225

IC 74151 – General Description

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs.

Two complementary outputs provide both inverting and non-inverting buffer operation.

A Strobe input is provided which, when at the high level, disables all data inputs and forces the Y output to the low state and the output to the high state.

The Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients.

Y

05/02/2023 Amit Nevase 226

IC 74151 - Features

Advanced oxide-isolated, ion-implanted Schottky TTL process

Switching performance is guaranteed over full temperature and VCC supply range

Pin and functional compatible with LS family counterpart

Improved output transient handling capability

05/02/2023 Amit Nevase 227


Select Lines

8:1Mux

Enable Input

Y

D0

D1

DataInputs

Equivalent Diagram

D2

D3

S0S2

D4

D5

D6

D7

S1

VCC GND

Pin Diagram

E

Y

05/02/2023 Amit Nevase 228

De-multiplexer ICs

IC Number Description

IC 74138 1:8 De-multiplexer

IC 74139 Dual 1:4 De-multiplexer

IC 74154 1:16 De-multiplexer

IC 74155 Dual 1:4 De-multiplexer

05/02/2023 Amit Nevase 229

IC 74155 – General Description

These monolithic TTL circuits feature dual 1 line to 4 line de-multiplexers with individual strobes and common binary address inputs in a single 16 pin package.

The individual strobes permit activating or inhibiting each of the 4-bit sections as desired.

05/02/2023 Amit Nevase 230

IC 74155 - Features

Input clamping diodes simplify system design.Choice of outputs : Totem pole (‘LS155A) or

open collector (‘LS156).Individual strobes simplify cascading for

decoding or de-multiplexing larger words.Applications: • Dual 2 to 4 Line Decoder• Dual 1: 4 De-multiplexer• 3 to 8 line Decoder• 1 to 8 line de-multiplexer

05/02/2023 Amit Nevase 231


05/02/2023 Amit Nevase 232



and IC 74245

05/02/2023 Amit Nevase 233

Encoder

Encoder is a combinational circuit which is designed to perform the inverse operation of decoder.

An encoder has ‘n’ number of input lines and ‘m’ number of output lines.

An encoder produces an m bit binary code corresponding to the digital input number.

The encoder accepts an n input digital word and converts it into m bit another digital word

05/02/2023 Amit Nevase 234

Encoder

.

.

.

.

.

.

‘n’inputs

‘m’outputsEncoder

05/02/2023 Amit Nevase 235

Types of Encoders

Priority Encoder

Decimal to BCD Encoder

Octal to BCD Encoder

Hexadecimal to Binary Encoder

05/02/2023 Amit Nevase 236

Priority Encoder

This is a special type of encoder.

Priorities are given to the input lines.

If two or more input lines are “1” at the same

time, then the input line with highest priority

will be considered.

05/02/2023 Amit Nevase 237

Priority Encoder 8:3

‘8’inputs

‘3’outputs

PriorityEncoder

8:3

Y2

D0

D1

D2

D3

D4

D5

D6

D7

Y1

Y0

Highest Priority

Lowest Priority

05/02/2023 Amit Nevase 238

Priority Encoder 8:3

Inputs Outputs

D7 D6 D5 D4 D3 D2 D1 D0 Y2 Y1 Y0

0 0 0 0 0 0 0 0 X X X

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 1 X X X 0 1 1

0 0 0 1 X X X X 1 0 0

0 0 1 X X X X X 1 0 1

0 1 X X X X X X 1 1 0

1 X X X X X X X 1 1 1

Truth Table:

05/02/2023 Amit Nevase 239


‘9’inputs

‘BCD’outputs

Decimal toBCD

Encoder

A

D1

D2

D3

D4

D5

D6

D7

B

C

D8

D9

D

05/02/2023 Amit Nevase 240


Inputs Outputs

D9 D8 D7 D6 D5 D4 D3 D2 D1 D C B A

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 0 1 X 0 0 1 0

0 0 0 0 0 0 1 X X 0 0 1 1

0 0 0 0 0 1 X X X 0 1 0 0

0 0 0 0 1 X X X X 0 1 0 1

0 0 0 1 X X X X X 0 1 1 0

0 0 1 X X X X X X 0 1 1 1

0 1 X X X X X X X 1 0 0 0

1 X X X X X X X X 1 0 0 1

Truth Table:

05/02/2023 Amit Nevase 241


Necessity, Applications and Realization of following (8 Marks) Multiplexers (MUX): MUX TreeDemultiplexers (DEMUX): DEMUX Tree, DEMUX as DecoderStudy of IC 74151, IC 74155Priority Encoder 8:3, Decimal to BCD EncoderTristate Logic, Unidirectional & Bidirectional buffer ICs:

IC 74244 and IC 74245

05/02/2023 Amit Nevase 242

Tristate Logic

In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit.

05/02/2023 Amit Nevase 243

Digital Buffer

Sometimes in digital electronic circuits we need to isolate logic gates from each other or have them drive or switch higher than normal loads, such as relays, solenoids and lamps without the need for inversion.

One type of single input logic gate that allows us to do just that is called the Digital Buffer.

05/02/2023 Amit Nevase 244

Digital Buffer

Symbol Truth Table

The Digital Buffer

A Q

0 0

1 1

Boolean Expression Q = A Read as: A gives Q

05/02/2023 Amit Nevase 245

Digital Buffer Unlike the single input, single output inverter or NOT gate

such as the TTL 7404 which inverts or complements its input signal on the output, the “Buffer” performs no inversion or decision making capabilities (like logic gates with two or more inputs) but instead produces an output which exactly matches that of its input. In other words, a digital buffer does nothing as its output state equals its input state.

Then digital buffers can be regarded as Idempotent gates applying Boole’s Idempotent Law because when an input passes through this device its value is not changed. So the digital buffer is a “non-inverting” device and will therefore give us the Boolean expression of: Q = A.

05/02/2023 Amit Nevase 246

Tri-state Buffer

As well as the standard Digital Buffer seen above, there is another type of digital buffer circuit whose output can be “electronically” disconnected from its output circuitry when required. This type of Buffer is known as a 3-State Buffer or more commonly a Tri-state Buffer.

A Tri-state Buffer can be thought of as an input controlled switch with an output that can be electronically turned “ON” or “OFF” by means of an external “Control” or “Enable” ( EN ) signal input. This control signal can be either a logic “0” or a logic “1” type signal resulting in the Tri-state Buffer being in one state allowing its output to operate normally producing the required output or in another state were its output is blocked or disconnected.

05/02/2023 Amit Nevase 247

Tri-state Buffer - Equivalent

05/02/2023 Amit Nevase 248

Active High Tri-state Buffer

Symbol Truth Table

Tri-state Buffer

Enable IN OUT

0 0 Hi-Z

0 1 Hi-Z

1 0 0

1 1 1

Read as Output = Input if Enable is equal to “1”

05/02/2023 Amit Nevase 249

Active Low Tri-state Buffer

Symbol Truth Table

Tri-state Buffer

Enable IN OUT

0 0 0

0 1 1

1 0 Hi-Z

1 1 Hi-Z

Read as Output = Input if Enable is NOT equal to “1”

05/02/2023 Amit Nevase 250

Tri-state Buffer Control

05/02/2023 Amit Nevase 251

Buffer ICs

Sr. No. IC Number Description

1 IC 7407 TTL Hex non inverting Buffer

2 IC 7417 TTL Hex Buffer/Driver

3 IC 74244 TTL Octal Unidirectional Buffer

4 IC 74245 TTL Octal Bi-directional Buffer

5 IC 4050 CMOS Hex Non-inverting Buffer

6 IC 4503 CMOS Hex Tri-state Buffer

7 IC 40244 CMOS Octal Tri-state Buffer

05/02/2023 Amit Nevase 252

IC 74244 - Features

ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

Balanced propagation delaysAll inputs have a Schmitt-trigger action Inputs accepts voltages higher than VCCFor AHC only: operates with CMOS input levelsFor AHCT only: operates with TTL input levelsSpecified from − 40 to +85 and +125°C

05/02/2023 Amit Nevase 253

IC 74244 – Internal Diagram

05/02/2023 Amit Nevase 254

Bi-directional Buffer

It is also possible to connect Tri-state Buffers “back-to-back” to produce what is called a Bi-directional Buffer circuit with one “active-high buffer” connected in parallel but in reverse with one “active-low buffer”.

Here, the “enable” control input acts more like a directional control signal causing the data to be both read “from” and transmitted “to” the same data bus wire. In this type of application a tri-state buffer with bi-directional switching capability such as the TTL 74245 can be used.

05/02/2023 Amit Nevase 255

IC 74245 - Description

These octal bus transceivers are designed for asynchronous two-way communication between data buses.

The control function implementation minimizes external timing requirements.

The device allows data transmission from the A Bus to the B Bus or from the B Bus to the A Bus depending upon the logic level at the direction control (DIR) input.

The enable input (G) can be used to disable the device so that the buses are effectively isolated.

05/02/2023 Amit Nevase 256

IC 74245 - Features

Bi-Directional bus transceiver in a high-density 20-pin package

3-STATE outputs drive bus lines directlyPNP inputs reduce DC loading on bus linesHysteresis at bus inputs improve noise marginsTypical propagation delay times, port-to-port 8 nsTypical enable/disable times 17 ns IOL (sink current) - 24 mA IOH (source current) - -15 mA

05/02/2023 Amit Nevase 257

IC 74245 – Internal Diagram

05/02/2023 Amit Nevase 258

References

Digital Principles by Malvino Leach

Modern Digital Electronics by R.P. Jain

Digital Electronics, Principles and Integrated Circuits by Anil K. Maini

Digital Techniques by A. Anand Kumar

05/02/2023 Amit Nevase 259

Online Tutorials

http://nptel.ac.in/video.php?subjectId=117106086

http://www.electronics-tutorials.ws/combination/comb_1.html















05/02/2023 Amit Nevase 260

Thank You

Amit Nevase