co-design and co-verification using a synchronous … · co-verification using a synchronous...
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Co-Design and Co-Verification using a Synchronous Language
Satnam SinghXilinx Research Labs
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Virtex-II PRO
Device ArraySize
LogicGates
PPCs GBIOs BRAMs
2VP2 16 x 22 38K 0 4 12
2VP4 40 x 22 81K 1 4 28
2VP7 40 x 34 133K 1 8 44
2VP20 56 x 46 251K 2 8 88
2VP50 88 x 70 638K 4 16 216
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ZBT SSRAM SDRAM
ZBT SSRAMController
SDRAMController
405PPC
On-ChipPeripheral
ROM
High-SpeedPeripheral
On-ChipPeripheral
CoreConnect OPB(On-Chip Peripheral Bus)
OPB
DDRSDRAM
CoreConnect Processor Local Bus (PLB) Arbiter
DDR SDRAMController
External BusController OPB Bridge
OPB BridgeI-Cache PLB
D-Cache PLB
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Formal Techniques Project
• Domain specific languages for hardware design and verification (Lava) and cryptology (Cryptol).
• Formal methods for CAD (routing) and dynamic reconfiguration (reconfiguration controllers).
• Formal notations/representations for HW/SW co-design and verification (e.g. Esterel)
• Property checking (PSL/Sugar)• IP-reuse (more powerful type systems la de Alfaro
and Henzinger)
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Problems Challenges
• Customer requirements for migrating software into hardware (“salmon effect”):– determinism: multiple SW processes on RTOS vs. genuinely
concurrent HW– verification– isolation
• Customer requirements to trade-off HW/SW partitioning for products at different price points.
• Requirements for verification of SW+HW• Safe Dynamic Reconfiguration• Verification of control-based systems
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LocalLink (Point to Point)
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Aurora (Link Layer Protocol)
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TX of 10 Gigabit Ethernet MAC
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Verify RX Control Signals
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Safe Dynamic Reconfiguration
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JPEG2000 Platform
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Video Monitoring Application
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Bus Based Reconfiguration
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Bus Based Reconfiguration
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Bus Based Reconfiguration
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Single Specification for Hardware and Software
HW/SW agnostic specification void uart_device_driver (){.....} uart.c
VHDL, Verilog -> hardware implementation
C -> software implementation
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Embedded Developer Kit
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Configuration
0101110001110001110100111001100100111000111001010110001110001110
New .bit File0101110001110001110100111001100100111000111001010110001110001110
.mem File
DATA2BRAM
0101110001110001110100111001100100111000111001010110001110001110
ELF File
# CPU address space 0xFFFFE000 - 0xFFFFFFFF. ADDRESS_BLOCK dramctlrBUS_BLOCK [0xFFFFF000:0xFFFFFFFF] xrefdes/dramctlr/bram0 [7:0] LOC=RAMB16_X0Y0;xrefdes/dramctlr/bram1 [15:8] LOC=RAMB16_X1Y0;xrefdes/dramctlr/bram2 [23:16] LOC=RAMB16_X2Y0;. . .
END_BUS_BLOCK; END_ADDRESS_BLOCK;
BlockRam Memory Map (.bmm)
0101110001110001110100111001100100111000111001010110001110001110
.bit File
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FSM Specification
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Esterel Specification
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FIFO Extract
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Concurrent Loops
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Orthogonality
• Orthogonal language constructs for:– Sequencing– Concurrency– Waiting– Pre-emption
• Freely mixable at any level.• “Things are only written once.” Gérard Berry.
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Esterel Studio
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Creating design
Via Safe State Machines Via Esterel code
loop[ await A || await B ] ;emit O
each R
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Code generation
Esterel design void uart_device_driver (){.....} uart.c
VHDL, Verilog -> hardware implementation
C -> software implementation
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Hardware UART XC2V1000
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Direct use in SoC
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Soft UART MicroBlaze XC2V1000
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sender
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parallel to serial shift
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receive
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serial to parallel
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FIFO
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UART without bus interface
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OPB Protocol
M1_BE Byte enable
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UART with OPB Interface
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Generated circuit
Esterel UART Lite :912 LUTs385 flip flops
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Comparison with Original CoreGen IP
CoreGen UART Lite IP :100 LUTs51 flip flops9 times smaller !
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Verification by simulation
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Verification with Observers
Observed system
Systemmodel Observer
VerifierBUG is possibly
emittedBUG is always
emitted
BUG is never emitted
BUG
Inputs
Outputs
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Verification engines
• 2 proof engines available inside Esterel Studio
– Built-in verifier : TiGer• BDD technique
– Prover Plug-in• SAT technique
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Formal verification
Of the FIFO :
proving that only a read access can make it exit the “full” state
Proven in less than 2 seconds
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Specification of master behavior ...
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… slave
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and arbiter
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OPB Protocol violationse.g. Checking that RNW doesn’t change during a transaction :
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Formal verification
Of the OPB slave interface :
proving that it won’t cause bus timeouts
Proven in less than 2 seconds
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Formal verification
Using an internal observer to access internal signals
No constraint on input signals
Of the FIFO : proving that only initialized data is returned
Proven in 30 seconds
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Interactive Deadlock Demo
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Other examples (LocalLink, Aurora, ...)
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Positive Conclusions
• Control-based calculations can be implemented in hardware using a software style specification in Esterel (“computing without processors”).
• Synchronous observers provide an additional verification technique to simulation, assertion languages (Sugar/OpenVERA etc.) and permits co-verification.
• Co-synthesis allows HW/SW trade-offs to be explored.• VHDL/RTL provide poor interface between high systems
and back-end tools.
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Next Steps
• Currently working on:– Xilinx Link Layer protocol (LocalLink, Aurora).– TX portion of 10 gigabit ethernet MAC.
• Wire-speed high level processing of gigabit and 10-gigabit traffic.
• Language enhancements to better support HW design.
• Interface synthesis (a la CoWare)• Control for System Generator
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System Generator
HDL co-simulation
Hardware in the loopco-simulation
System Generator extends Simulink to support external simulation engines
•Hardware acceleration•Mixed-mode HDL/data flow