co by rakesh roshan

Computer OrganizationUNIT 1

Prepared ByProf. Rakesh Roshan

[email protected]

Prof. RAKESH ROSHAN 09971640291

REGISTER TRANSFER AND MICROOPERATIONS

• Register Transfer Language

• Register Transfer

• Bus and Memory Transfers

• Arithmetic Microoperations

• Logic Microoperations

• Shift Microoperations

• Arithmetic Logic Shift Unit


SIMPLE DIGITAL SYSTEMS

• Combinational and sequential circuits can be used to create simple digital systems.

• These are the low-level building blocks of a digital computer.

• Simple digital systems are frequently characterized in terms of– the registers they contain, and– the operations that they perform.

• Typically,– What operations are performed on the data in the registers– What information is passed between registers


MICROOPERATIONS (1)

• The operations on the data in registers are called microoperations.• The functions built into registers are examples of microoperations

– Shift– Load– Clear– Increment– …

Register Transfer Language


MICROOPERATION (2)

An elementary operation performed (during one clock pulse), on the information stored in one or more registers

R f(R, R)

f: shift, load, clear, increment, add, subtract, complement,and, or, xor, …

ALU(f)

Registers(R)

1 clock cycle



ORGANIZATION OF A DIGITAL SYSTEM

- Set of registers and their functions

- Microoperations set

Set of allowable microoperations provided by the organization of the computer

- Control signals that initiate the sequence of microoperations (to perform the functions)

• Definition of the (internal) organization of a computer



REGISTER TRANSFER LEVEL

• Viewing a computer, or any digital system, in this way is called the register transfer level

• This is because we’re focusing on– The system’s registers– The data transformations in them, and– The data transfers between them.



REGISTER TRANSFER LANGUAGE

• Rather than specifying a digital system in words, a specific notation is used, register transfer language

• For any function of the computer, the register transfer language can be used to describe the (sequence of) microoperations

• Register transfer language– A symbolic language– A convenient tool for describing the internal organization of digital computers– Can also be used to facilitate the design process of digital systems.



DESIGNATION OF REGISTERS

• Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13, IR)

• Often the names indicate function:– MAR - memory address register– PC - program counter– IR - instruction register

• Registers and their contents can be viewed and represented in various ways

– A register can be viewed as a single entity:

– Registers may also be represented showing the bits of data they contain


MAR


DESIGNATION OF REGISTERSRegister Transfer Language

R1 Register

Numbering of bits

Showing individual bits

Subfields

PC(H) PC(L)15 8 7 0

- a register - portion of a register - a bit of a register

• Common ways of drawing the block diagram of a register

7 6 5 4 3 2 1 0

R215 0

• Designation of a register


REGISTER TRANSFER

• Copying the contents of one register to another is a register transfer

• A register transfer is indicated as

R2 R1

– In this case the contents of register R2 are copied (loaded) into register R1– A simultaneous transfer of all bits from the source R1 to the

destination register R2, during one clock pulse– Note that this is a non-destructive; i.e. the contents of R1 are not altered by

copying (loading) them to R2

Register Transfer


REGISTER TRANSFER

• A register transfer such as

R3 R5

Implies that the digital system has

– the data lines from the source register (R5) to the destination register (R3)– Parallel load in the destination register (R3)– Control lines to perform the action

Register Transfer


CONTROL FUNCTIONS

• Often actions need to only occur if a certain condition is true• This is similar to an “if” statement in a programming language• In digital systems, this is often done via a control signal, called a control

function– If the signal is 1, the action takes place

• This is represented as:

P: R2 R1

Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P = 1) then (R2 R1)

Register Transfer


HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Implementation of controlled transfer

P: R2 R1

Block diagram

Timing diagram

Clock

Register Transfer

Transfer occurs here

R2

R1

Control Circuit

LoadP

n

Clock

Load

t t+1

The block diagram that depicts the transfer from R1 to R2. The n outputs of register R1 are connected to the n inputs of registerR2. The letter n will be used to indicate any number of bits for the register. It will be replaced by an actual number when the length Of the register is known. Register R2 has load input that is activated by the control variable P. In timing diagram, P is activated in the control section by the rising edge of a clock pulse at time t. The next positive transition of the clock at time t+1 finds the load active and the data inputs of R2 are then loaded into the register in parallel. P may go back to 0 at Time t+1; otherwise, the transfer will occur with every clock pulse transition while P remains active.


SIMULTANEOUS OPERATIONS

• If two or more operations are to occur simultaneously, they are separated with commas

P: R3 R5, MAR IR

• Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the contents of register IR into register MAR

Register Transfer


BASIC SYMBOLS FOR REGISTER TRANSFERS

Capital letters Denotes a register MAR, R2 & numerals Parentheses () Denotes a part of a register R2(0-7), R2(L)

Arrow Denotes transfer of information R2 R1

Colon : Denotes termination of control function P:Comma , Separates two micro-operations A B, B

A

Symbols Description Examples

Register Transfer


Bus and Memory Transfer

• Bus is a path(of a group of wires) over which information is transferred, from any of several sources to any of several destinations.

• A digital computer has many registers, and paths must be provided to transfer information from one register to another. The number of wires will be excessive if separate lines are used between each register and all other registers in the system. A more efficient scheme for transferring information between registers in a multiple-register configuration is a common bus system.

• A bus structure consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. Control signals determine which register is selected by the bus during each particular register transfer.

Register Transfer


Bus System for four registers

From a register to bus: BUS R

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4Register A Register B Register C Register D

B C D1 1 1

4 x1MUX

B C D2 2 2

4 x1MUX

B C D3 3 3

4 x1MUX

B C D4 4 4

4 x1MUX

4-line bus

x

yselect

0 0 0 0

Register A Register B Register C Register D

Bus lines

Bus and Memory Transfers

We can construct the common bus system is with multiplexers. The multiplexers select the sourceRegister whose binary information is then placed on the bus.

x y Register Selected

0 0 A

0 1 B

1 0 C

1 1 D


TRANSFER FROM BUS TO A DESTINATION REGISTER

Three-State Bus Buffers

Bus line with three-state buffers

Output Y=A if C=1High-impedence if C=0

Normal input A

Control input C

Select

Enable

0123

S0S1

A0B0C0D0

Bus line for bit 0


A bus system can be constructed with three-state gated instead of multiplexers. A three-state gate Is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. The third state is a high-impedance state. The high-impedance state Behaves like an open circuit, which means that the output is disconnected and does not haveA logic significance. Three-state gates may perform any conventional logic, such as AND and NAND.However, the one most commonly used in the design of a bus system is the buffer gate.

In the above diagram, The outputs of four buffers are connected together to form a single bus line . The control inputs to the buffers determine which of the four normal inputs will communicateWith the bus line. No more than one buffer may be in the active state at any given time. TheConnected buffers must be controlled so that only one three-state buffer has access to the busline while all other buffers are maintained in a high impedance state.Prof. RAKESH ROSHAN

09971640291

BUS TRANSFER IN RTL

• Depending on whether the bus is to be mentioned explicitly or not, register transfer can be indicated as either

or

• In the former case the bus is implicit, but in the latter, it is explicitly indicated


R2 R1

BUS R1, R2 BUS


MEMORY (RAM)

• Memory (RAM) can be thought as a sequential circuits containing some number of registers

• These registers hold the words of memory• Each of the r registers is indicated by an address• These addresses range from 0 to r-1• Each register (word) can hold n bits of data• Assume the RAM contains r = 2k words. It needs the following

– n data input lines– n data output lines– k address lines– A Read control line– A Write control line


data input lines

data output lines

n

n

k

address lines

Read

Write

RAMunit


MEMORY TRANSFER

• Collectively, the memory is viewed at the register level as a device, M.

• Since it contains multiple locations, we must specify which address in memory we will be using

• This is done by indexing memory references

• Memory is usually accessed in computer systems by putting the desired address in a special register, the Memory Address Register (MAR, or AR)

• When memory is accessed, the contents of the MAR get sent to the memory unit’s address lines


AR Memoryunit

Read

Write

Data inData out

M


MEMORY READ

• To read a value from a location in memory and load it into a register, the register transfer language notation looks like this:

• This causes the following to occur– The contents of the MAR get sent to the memory address lines– A Read (= 1) gets sent to the memory unit– The contents of the specified address are put on the memory’s output data lines– These get sent over the bus to be loaded into register R1


R1 M[MAR]


MEMORY WRITE

• To write a value from a register to a location in memory looks like this in register transfer language:

• This causes the following to occur– The contents of the MAR get sent to the memory address lines– A Write (= 1) gets sent to the memory unit– The values in register R1 get sent over the bus to the data input lines of the

memory– The values get loaded into the specified address in the memory


M[MAR] R1


SUMMARY OF R. TRANSFER MICROOPERATIONSBus and Memory Transfers

A B Transfer content of reg. B into reg. A

AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR

A constant Transfer a binary constant into reg. A

ABUS R1, Transfer content of R1 into bus A and, at the same time,

R2 ABUS transfer content of bus A into R2 AR Address registerDR Data registerM[R] Memory word specified by reg. RM Equivalent to M[AR]

DR M Memory read operation: transfers content of memory word specified by AR into DR

M DR Memory write operation: transfers content of DR into memory word specified by AR


MICROOPERATIONS

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations

- Logic microoperations

- Shift microoperations

Arithmetic Microoperations


ARITHMETIC MICROOPERATIONS

• The basic arithmetic microoperations are– Addition– Subtraction– Increment– Decrement

• The additional arithmetic microoperations are– Add with carry– Subtract with borrow– Transfer/Load– etc. …

Summary of Typical Arithmetic Micro-Operations


R3 R1 + R2 Contents of R1 plus R2 transferred to R3

R3 R1 - R2 Contents of R1 minus R2 transferred to R3

R2 R2’ Complement the contents of R2

R2 R2’+ 1 2's complement the contents of R2 (negate)

R3 R1 + R2’+ 1 subtraction

R1 R1 + 1 Increment

R1 R1 - 1 DecrementProf. RAKESH ROSHAN

09971640291

BINARY ADDER / SUBTRACTOR / INCREMENTER

FA

B0 A0

S0

C0FA

B1 A1

S1

C1FA

B2 A2

S2

C2FA

B3 A3

S3

C3

C4

Binary Adder-Subtractor

FA

B0 A0

S0

C0C1FA

B1 A1

S1

C2FA

B2 A2

S2

C3FA

B3 A3

S3C4

M

Binary Adder


The addition and subtraction operations can be combined into one common circuit by includingAn exclusive-OR gate with full adder. In 4-bit adder-subtractor circuit, the mode input M controlsThe operation. When M=0 the circuit is an adder and when M=1 the circuit becomes a subtractor.Each exclusive-OR gate receive input M and one of the inputs of B. When M=0, we have B 0=B.The full adders receives the value of B, input carry is 0, and the circuit performs A plus B. WhenM=1 we have B 1=B’ and C0 = 1. The B inputs are all complemented and a 1 is added through The input carry. The circuit performs the operation A plus the 2’s complement of B.


Binary Incrementer

The above diagram represents the 4-bit Binary incrementer using Half-Adder. One of the inputs to the least significant half-adder is connected to logic-1 and the other input is connected to the least significant bit of the number to be incremented. The output carry from one half-adder is connected to one of the inputs of the next-higher-order half-adder. The circuit receives the four bits from A0 through A3 , adds one to it and generates the incremented output in S0 through S3. The output carry C4 will be 1 only after incrementing binary 1111. This also causes outputs S0 through S3 to go to 0.

HAx y

C S

A0 1

S0

HAx y

C S

A1

S1

HAx y

C S

A2

S2

HAx y

C S

A3

S3C4


ARITHMETIC CIRCUIT

S1S00123

4x1MUX

X0

Y0

C0

C1

D0FA

S1S00123

4x1MUX

X1

Y1

C1

C2

D1FA

S1S00123

4x1MUX

X2

Y2

C2

C3

D2FA

S1S00123

4x1MUX

X3

Y3

C3

C4

D3FA

Cout

A0

B0

A1

B1

A2

B2

A3

B3

0 1

S0S1Cin

S1 S0 Cin Y Output Microoperation0 0 0 B D = A + B Add0 0 1 B D = A + B + 1 Add with carry0 1 0 B’ D = A + B’ Subtract with borrow0 1 1 B’ D = A + B’+ 1 Subtract1 0 0 0 D = A Transfer A 1 0 1 0 D = A + 1 Increment A1 1 0 1 D = A - 1 Decrement A1 1 1 1 D = A Transfer A



Arithmetic Circuit Contd…..• Addition: When S1S0=00, the value of B is applied to the Y inputs of the adder. If C in=0, the

output D=A+B. If Cin=1, output D=A+B+1. Both perform the add micro operation with or without adding the input carry.

• Subtraction: When S1S0=01, the complement of B is applied to the Y inputs of the adder. If Cin=1 , then D=A+B’+1. This produces A plus the 2’s complement of B , which is equivalent to a subtraction of A-B. When Cin=0 , then D=A+B’. This is equivalent to a subtract with borrow , that is , A-B-1.

• Increment: When S1S0=10, the inputs from B are neglected, and instead, all 0’s are inserted into the Y inputs. The output becomes D=A+0+Cin .This gives D=A when Cin=0 and D=A+1 when Cin=1. In the first case we have a direct transfer from input A to output D. In the second case, the value of A is incremented by 1.

• Decrement: When S1S0=11, all 1’s are inserted into the Y inputs of the adder to produce the decremented operation D=A-1 when Cin=0. This is because a number with all 1’s is equal to the 2’s complement of 1 ( the 2’s complement of binary 0001 is 1111). Adding a number A to the 2’s complement of 1 produces F=A+2’s complement of 1=A-1.When C in=1, then D=A-1+1=A, which causes a direct transfer from input A to output D.


LOGIC MICROOPERATIONS

• Specify binary operations on the strings of bits in registers– Logic micro operations are bit-wise operations, i.e., they work on the individual bits

of data– useful for bit manipulations on binary data – useful for making logical decisions based on the bit value

• There are, in principle, 16 different logic functions that can be defined over two binary input variables

• However, most systems only implement four of these– AND (), OR (), XOR (), Complement/NOT

• The others can be created from combination of these• Example: the exclusive-OR microoperation with the contents of two registers R1 and

R2 is symbolized by the statementP: R1R1 R2

It specifies that a logic microoperation to be executed on the individual bits of the registers provided that the control variable P=1.

Logic Microoperations


LIST OF LOGIC MICROOPERATIONS• List of Logic Microoperations - 16 different logic operations with 2 binary vars. - n binary vars → functions2 2 n

• Truth tables for 16 functions of 2 variables and the corresponding 16 logic micro-operations

BooleanFunction

Micro-Operations

Namex 0 0 1 1y 0 1 0 1


0 0 0 0 F0 = 0 F 0 Clear0 0 0 1 F1 = xy F A B AND0 0 1 0 F2 = xy' F A B’0 0 1 1 F3 = x F A Transfer A0 1 0 0 F4 = x'y F A’ B0 1 0 1 F5 = y F B Transfer B0 1 1 0 F6 = x y F A B Exclusive-OR0 1 1 1 F7 = x + y F A B OR1 0 0 0 F8 = (x + y)' F A B)’ NOR1 0 0 1 F9 = (x y)' F (A B)’ Exclusive-NOR1 0 1 0 F10 = y' F B’ Complement B1 0 1 1 F11 = x + y' F A B1 1 0 0 F12 = x' F A’ Complement A1 1 0 1 F13 = x' + y F A’ B1 1 1 0 F14 = (xy)' F (A B)’ NAND1 1 1 1 F15 = 1 F all 1's Set to all 1's


HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS

0 0 F = A B AND0 1 F = AB OR1 0 F = A B XOR1 1 F = A’ Complement

S1 S0 Output -operation

Function table


B

A

S

S

F

1

0

i

i

i0

1

2

3

4 X 1MUX

Select


APPLICATIONS OF LOGIC MICROOPERATIONS

• Logic microoperations can be used to manipulate individual bits or a portions of a word in a register

• Consider the data in a register A. In another register, B, is bit data that will be used to modify the contents of A

– Selective-set A A + B– Selective-complement A A B– Selective-clear A A • B’– Mask (Delete) A A • B– Clear A A B– Insert A (A • B) + C– Compare A A B



SELECTIVE SET

• In a selective set operation, the bit pattern in B is used to set certain bits in A

1 1 0 0 At

1 0 1 0 B1 1 1 0 At+1 (A A + B)

• If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps its previous value



SELECTIVE COMPLEMENT

• In a selective complement operation, the bit pattern in B is used to complement certain bits in A

1 1 0 0 At

1 0 1 0 B

0 1 1 0 At+1 (A A B)

• If a bit in B is set to 1, that same position in A gets complemented from its original value, otherwise it is unchanged



SELECTIVE CLEAR

• In a selective clear operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 At

1 0 1 0 B

0 1 0 0 At+1 (A A B’)

• If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged



MASK OPERATION

• In a mask operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 At

1 0 1 0 B

1 0 0 0 At+1 (A A B)

• If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged



CLEAR OPERATION

• In a clear operation, if the bits in the same position in A and B are the same, they are cleared in A, otherwise they are set in A

1 0 1 0 At

1 0 1 0 B

0 0 0 0 At+1 (A A B)



INSERT OPERATION• An insert operation is used to introduce a specific bit pattern into A

register, leaving the other bit positions unchanged• This is done as

– A mask operation to clear the desired bit positions, followed by– An OR operation to introduce the new bits into the desired positions– Example

• Suppose you wanted to introduce 1010 into the low order four bits of A: 1101 1000 1011 0001 A (Original)

1101 1000 1011 1010 A (Desired)

• 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask

1101 1000 1011 0000 A (Intermediate)

0000 0000 0000 1010 Added bits

1101 1000 1011 1010 A (Desired)



SHIFT MICROOPERATIONS

• There are three types of shifts– Logical shift– Circular shift– Arithmetic shift

Shift Microoperations

Serialinput

• A right shift operation

• A left shift operation Serialinput

Shift micro operations are used for serial transfer of data. They are also used in conjunction with arithmetic, Logic and other data-processing operations. The contents of a register can be shifted to the left or the right. At the same time that the bits are shifted , the first flip-flop receives its binary information from the serial Input. During a shift-left operation the serial input transfers a bit into the rightmost position . During a shift- Right operation the serial inputs transfers a bit into the leftmost position. The information transferred through the serial input determines the type of shift.


LOGICAL SHIFT

• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

• A left logical shift operation:

• In a Register Transfer Language, the following notation is used– shl for a logical shift left– shr for a logical shift right– Examples:

• R2 shr R2• R3 shl R3


0

0


CIRCULAR SHIFT• In a circular shift the serial input is the bit that is shifted out of the other

end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used– cil for a circular shift left– cir for a circular shift right– Examples:

• R2 cir R2• R3 cil R3



ARITHMETIC SHIFT

• An arithmetic shift is meant for signed binary numbers (integer)• An arithmetic left shift multiplies a signed number by two• An arithmetic right shift divides a signed number by two• The main distinction of an arithmetic shift is that it must keep the sign

of the number the same as it performs the multiplication or division

• A right arithmetic shift operation:

• A left arithmetic shift operation:


0

signbit

signbit


ARITHMETIC SHIFTShift Microoperations

• In a RTL, the following notation is used– ashl for an arithmetic shift left– ashr for an arithmetic shift right– Examples:

» R2 ashr R2» R3 ashl R3


HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS


S

01

H0MUX

S

01

H1MUX

S

01

H2MUX

S

01

H3MUX

Select 0 for shift right (down) 1 for shift left (up)Serial

input (IR)

A0

A1

A2

A3

Serialinput (IL)

Select Output

S H0 H1 H2 H3

0 IR A0 A1 A2

1 A1 A2 A3 IL

A combinational circuit shifter can be constructed with multiplexers. The 4-bit shifter has four Data inputs, A0 through A3 and four data outputs, H0 through H3. There are two serial inputs, oneFor shift left (IL) and the other for shift right (IR). When the selection input S=0 , the input data are Shifted right (down in the diagram). When S=1, the input data are shifted left(up in the diagram).The function table shows which input goes to each output after the shift. A shifter with n data and Outputs requires n multiplexers. The two serial inputs can be controlled another multiplexer to Provide the three possible types of shifts.


ARITHMETIC LOGIC SHIFT UNIT

S3 S2 S1 S0 Cin Operation Function0 0 0 0 0 F = A Transfer A0 0 0 0 1 F = A + 1 Increment A0 0 0 1 0 F = A + B Addition0 0 0 1 1 F = A + B + 1 Add with carry0 0 1 0 0 F = A + B’ Subtract with borrow0 0 1 0 1 F = A + B’+ 1 Subtraction0 0 1 1 0 F = A - 1 Decrement A0 0 1 1 1 F = A TransferA0 1 0 0 X F = A B AND0 1 0 1 X F = A B OR0 1 1 0 X F = A B XOR0 1 1 1 X F = A’ Complement A1 0 X X X F = shr A Shift right A into F1 1 X X X F = shl A Shift left A into F


ArithmeticCircuit

LogicCircuit

C

C 4 x 1MUX

Select

0123

F

S3S2S1S0

BA

i

A

D

A

E

shrshl

i+1 i

ii

i+1i-1

i

i

The arithmetic, logic and shift circuits can be combined intoOne ALU with common selection variables. The subscript i Designates a typical stage. Input Ai and Bi are applied to boththe arithmetic and logic units. A particular microoperation is selected with inputs S1 and S0. A 4*1 multiplexer at the output chooses between an arithmetic output in Ei and a logic output in Hi. The data in the multiplexer are selected with S3 and S2.The other two data inputs to the multiplexer receive inputs A i-1

for the shift-left operation. The output carry Ci+1 of a given arithmetic stage must be connected to the input carry C i of the next stage in sequence. The input carry to the first stage is the input carry Cin , which provides a selection variable forThe arithmetic operations.


Design of Fast adder (Carry- Lookahead Addition)

A fast adder circuit must speed up the generation of the carry signals. The logic expressions for s i(sum) and ci+1(carry out) of stage i are si=xi yi ziAnd ci+1=xiyi+xici+yiciFactoring the second equation into ci+1=xiyi+(xi+yi)ciWe can write ci+1=Gi and PiciWhere Gi=xiyi and Pi=xi+yiThe expression Gi and Pi are called the generate and propagate functions of stage i. If the generate function for stage I is equal to 1, then ci+1=1, independent of the input carry ci. This occurs when both xi and yi are 1. The propagate function means that an input carry will produce an output carry when either xi is 1 or yi is 1. All Gi and Pi functions can be formed independently and in parallel in one logic gate delay after the X and Y vectors are applied to the inputs of an n-bit adder.


Design of Fast adder (Carry- Lookahead Addition)

A fast adder circuit must speed up the generation of the carry signals. The logic expressions for si(sum) and ci+1(carry out) of stage i are si=xi yi ziAnd ci+1=xiyi+xici+yiciFactoring the second equation into ci+1=xiyi+(xi+yi)ciWe can write ci+1=Gi and PiciWhere Gi=xiyi and Pi=xi+yiExpanding ci in terms of i-1 subscripted variables and substituting into the ci+1Expression, we obtain ci+1=Gi+PiGi-1 + PiPi-1ci-1Continuing this type of expansion, the final expression for any carry variable is ci+1=Gi+PiGi-1 + PiPi-1Gi-2+……….+PiPi-1….P1G0+PiPi…….P0c0

Example:- c1=G0+Poc0 c2=G1+P1G0+P1P0c0 c3=G2+P2G1+P2P1G0+P2P1P0c0 c4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0c0The carries are implemented in the block labeled carry- lookahead logic. An adder implemented in this form is called a carry- lookahead adder.


4-bit Carry- lookahead adder

c0

s3

Carry- look ahead logic

B cell B cellB cellB cell

x3 y3 x2 y2 x1 y1 x0 y0

c3 c2 c1

s3 s2 s1 s0

c4

G3 G2 G1 G0P3 P2 P1 P0

G0I P0

I

Where P0I=P3P2P1P0

and G0I=G3+P3G2+P3P2P1G0


Addition and Subtraction Algorithm

Minuend in ASubtrahend in B

Augend in AAddend in B

As Bs As Bs

EA A+B’+1AVF 0

EA A+B

E

AVF E

AA A’

AA+1AsAs

As 0

END(result is in A and As)

Subtraction OperationAdd Operation

10 10

0 1

!=0 0

A<BA>=B

As=Bs As!=Bs

As!=BsAs=Bs


Booth Multiplication AlgorithmMultiply

Multiplicand in BRMultiplier in QR

AC 0Qn+1 o

SC n

QnQn+1

AC AC-BR ACAC+BR

Ashr(AC & QR)SC SC-1

SC

END

10 01

0011

!=0 0

Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement representation


Example of Multiplication with Booth algorithm

QnQn+1 BR=10111(BR)’+1=01001

AC QR Qn+1 SC

Initial 00000 10011 0 101

10 Subtract BR 01001

01001

Ashr 00100 11001 1 100

11 Ashr 00010 01100 1 011

01 Add BR 10111

11001

Ashr 11100 10110 0 010

00 Ashr 11110 01011 0 001

10 Subtract BR 01001

00111

Ashr 00011 10101 1 000

Let n=5 , multiply =(-9) * (-13)=+117


IEEE standard for floating numbersThis standard for representing floating-point numbers in 32 bits has been developed and specifies in detailBy the Institute of Electrical and Electronics Engineers(IEEE). The standard describes both the representation and the way in which the four basic arithmetic operations are to be performed. In 32-bit representation, the sign of the number is given in the first bit, followed by a representation for the exponent (to the base 2) of theScale factor. Instead of the signed exponent, E, the value actually stored in the exponent field is an unsignedInteger E’=E+127. This is called the excess-127 format. The last 23 bits represent the mantissa.

S E’ M

32 bits

Sign ofNumber:0 signifies +1 signifies -

8-bit signed Exponent inExcess-127representation

23-bitMantissa fraction

Value represented=±1.M × 2 E’-127

Example : Representation of 1.001010……….0 ×2 -87

0 00101011 . 001010………………………………………………………………0


co by rakesh roshan

Technology

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