CMPE 200Virtual memory1Q Answer:Given, size of virtual address is 48 bits.Size of physical memory is 4 GB.Word size is 64 bits and page size as 16 KB.

1. Given page table: 3-level page table, and V1: 10 bits, V2: 11 bits, V3: 13 bits.Size of an entry in tables: 32 bits.

a. From the given data, Bits of the virtual address that are used to index the first-level table are 38 – 47 bits.

b. Bits of the virtual address that are used to index the page tables at the bottom of the hierarchy aresecond-level: 27 – 37 bitsthird-level: 14 – 26 bits

c. Size of table at first-level: 210 x 22 = 212 = 4096 = 4 kBSize of table at second-level: 211 x 22 = 213 = 8192 = 8 kBSize of table at third-level: 213 x 22 = 215 = 32768 = 32 kB

d. Total amount of virtual memory covered by each entry of page table at each level,First-level: 238

Second-level: 227

Third-level: 214

2. Given, TLB size: 512 entries,TLB organization: 4-way set associative.Total number of sets: 512/4 = 128 = 27

Therefore, page offset will be from 0-13 bit

a. Bits of virtual address that are used to index the TLB are: 14 – 20

b. Bits of virtual address that are used as tags in the TLB are: 21 – 47

c. TLB tag size: 2Number of Tag bits = 227

3. Given, Cache size: 128 KBBlock size (line size): 64 KBSet size: 4 blocks per setVirtually indexed, physically tagged (VIPT)

Number of blocks = cache size / block size = 217 / 26 = 211 blocks.Number of sets = 211 / 4 = 29 setsTherefore, we know, index is 9 bits and word offset is 6 bits.Thus, block offset: 0 – 5 bitsIndex bits: 6 – 14 bitsTag bits: 15 – 31 bits.

a. Bits of virtual address that are used to index the tag RAM of the cache is 6 – 14 bits.

b. Bits of the virtual address that are used to find the target word within a cache block is: 3 – 5

c. Bits of the physical address that are matched against the tags in the tag RAMs are 15 – 31

2Q Answer:Given, Size of virtual address: 42 bits (from bit 0 to bit 41) Size of physical memory: 4 GB Word size: 64 bits (or 8 B) Page size: 16 KB Size of an entry in page tables: 32 bits (or 4 B)

1. Size of a single level page table is 228 x 4 = 230 = 1GB

2. We assume, 28 bit virtual page number is now split into two fields, we get the number of page tables in L1 and L2 as 1 & 2 respectively.Size of L1 page table: 214 x 4 = 216 bits.Similarly, Size of L2 page table: 214 x 4 x 2 = 217 bits.Therefore, total size of all page tables = 216 + 217 = 192 KB

3. Similarly for 3 level page table,Size of L1 page table: 28 x 4 = 210 bits = 1 KBSize of L2 page table: 22 x 210 x 2 = 213 bits = 8 KBSize of L3 page table: 22 x 210 x 2 = 213 bits = 8 KB

Summing up all, total size of all page tables = 17 KB

Multiprocessor3Q Answer:Given reference stream: r1 w1 r2 w2 r3 w3 r1 w1 r2 w2 r3 w3 r1 r2

Below table shows entries for MSI- invalidate coherence protocol

MSI Cycles Processor 1 State

Processor 2 State

Processor 3 State

r1 150 S I Iw1 10 M I Ir2 50 S S Iw2 10 I M Ir3 50 I S Sw3 10 I I Mr1 50 S I Sw1 10 M I Ir2 50 S S Iw2 10 I M I

r3 50 I S Sw3 10 I I Mr3 1 I I Mw3 1 I I Mr1 50 S I Sr2 150 S S S

Total cycles for

MSI-invalidat

e

662

Below table shows entries for MESI coherence protocol

MESI Cycles Processor 1 State

Processor 2 State

Processor 3 State

r1 150 E I Iw1 1 M I Ir2 50 S S Iw2 10 I M Ir3 50 I S Sw3 10 I I Mr1 50 S I Sw1 10 M I Ir2 50 S S Iw2 10 I M Ir3 50 I S Sw3 10 I I Mr3 1 I I Mw3 1 I I Mr1 50 S I Sr2 150 S S S

Total cycles for

MESI653

Below table shows entries for MOESI coherence protocol

MESI Cycles Processor 1 State

Processor 2 State

Processor 3 State

r1 150 E I Iw1 1 M I Ir2 50 O S Iw2 10 I M Ir3 50 I O S

w3 10 I I Mr1 50 S I Ow1 10 M I Ir2 50 O S Iw2 10 I M Ir3 50 I O Sw3 10 I I Mr3 1 I I Mw3 1 I I Mr1 50 S I Or2 50 S S O

Total cycles for MOESI

553

Comparison of MSI, MESI and MOESI coherence protocol

coherence protocol Total cycles

MSI-invalidate 662MESI 653

MOESI 553

From the above comparison we can say that MSI costs more than MESI and MOESI