cmos ttl fpga - ferdowsi university of mashhadprofsite.um.ac.ir/~shoraka/digitallogiclab.pdf ·...
TRANSCRIPT
7400
LED
NAND.
TTLCMOS
01
sinksource
datasheet
LED
bounce
bounce
debunce
debounceRS Latch
NCNO
NAND NOR
bounce
bounce
LED
LED
LED
LED
LED
10LED
LED
LED
LED
CMOS
01
01
TTL(standard)(source)
(sink)
7400
LEDVccLEDkΩ
Typical LED Characteristics
Semiconductor Wavelength Colour
VF @ 20mA
Material
GaAs 850-940nm Infra-Red
1.2v
GaAsP 630-660nm Red 1.8v
GaAsP 605-620nm Amber 2.0v
GaAsP:N 585-595nm Yellow 2.2v
AlGaP 550-570nm Green 3.5v
SiC 430-505nm Blue 3.6v
GaInN 450nm White 4.0v
Vcc
LED
LEDΩ
LED1LED
01LowHigh
LatchRS7400debounce
NAND
747474161
74161741607416274163
ANDORNOT
7474
74161
LoadResetcarry
clock
clock
clock
resetload
clockresetloadclock
resetload
clock
clock
look-ahead-carry
7474
74161
744774484511
ANDORNOT
74161
0059
0011
7seg1010
1011
seven segment7segment7seg
LED09
abcdefgLEDdp
7seg
(Common Cathode)(Common Anode)
7seg7seg
7seg
74477448
LEDkLED
74161
00590011
74283
reset74161
reset(load)clk
74161741637419074193
mskHz
(time-base)kHz
ab
akHz b
HzBCDb
breset
akHzb
ms
7seg
reset
HzHz
(time-base)
Hz
Hz
74283
7415374154
BCD
LED
BCD to 7segment
don’t care
ASMFSM
7415374154
BCD
741217412274123
A/D
1
D/ADAC
Latch
D/A
R/2R
Vod(R)
kΩ
kΩ
A/DADC
S&HA/D
A/D
(successive approximations)
A/DD/AR/2R
start conversion
D/A
start conversion
741217412274123
A/DD/A
405140524053
x
Vcc
active low
low
low
load enableactive low
(low)
low
resetreset
set
1 0 0 1 x 1 1 0 1 = 1 1 1 0 1 0 1
9 x 1 3 = 1 1 7
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 +
1 0 0 1 1 1 0 0 1
0 1 0 0 1 0 0 0
0 0 0 0 1 0 0 1 + 0 0 1 0 0 1 0 0 +
0 0 0 0 0 0 0 0 0
0 1 0 0 1 0 0
0 0 0 0 1 0 0 1 + 0 0 0 1 0 0 1 0 +
1 0 0 1 1 1 0 0 1
0 1 0 1 1 0 1 0
0 0 1 0 1 1 0 1 + 0 0 1 0 1 1 0 1 +
1 0 0 1 1 1 0 0 1
0 1 1 1 0 1 0 1
0 1 1 1 0 1 0 1
749574195
405140524053
FPGA
FPGA
FPGASpartan 3(3S400-PQ208)
LED
SDRAM
LED
Dip-Switch
MHz
(RS232)
USB
ADCDAC
JTAgFPGAROMROMFlash
LED
ISEXilinx
FPGA
clearFPGA
VHDL code for 7-segment drive library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity svnsegdrv is port ( din : in std_logic_vector (3 downto 0); segs : out std_logic_vector (7 downto 0));
end svnsegdrv; architecture behavioral of svnsegdrv is --file produced for nasre shargh fpga board --input : 4 bits are normally located : left msb, right lsb begin -- abcdefgdp common cathode -- with din select -- segs <= "11111100" when "0000", -- "01100000" when "0001", -- "11011010" when "0010", -- "11110010" when "0011", -- "01100110" when "0100", -- "10110110" when "0101", -- "10111110" when "0110", -- "11100000" when "0111", -- "11111110" when "1000", -- "11110110" when "1001", -- "11101110" when "1010", -- "00111110" when "1011", -- "10011100" when "1100", -- "01111010" when "1101", -- "10011110" when "1110", -- "10001110" when "1111", -- "11111111" when others; with din select -- abcdefgdp common anode segs <= "00000011" when "0000", "10011111" when "0001", "00100101" when "0010", "00001101" when "0011", "10011001" when "0100", "01001001" when "0101", "01000001" when "0110", "00011111" when "0111", "00000001" when "1000", "00001001" when "1001", "00010001" when "1010", "11000001" when "1011", "01100011" when "1100", "10000101" when "1101", "01100001" when "1110", "01110001" when "1111", "10101010" when others; end behavioral;
FPGA
FPGA
LEDFPGA
MHz
AM/PM
dip-switch
LED
kHzMHz
FPGA
FPGA
VHDL code for clock library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock2 is port ( clk : in std_logic; csel : in std_logic_vector (2 downto 0); yml : out std_logic_vector (7 downto 0); ymh : out std_logic_vector (7 downto 0); yhl : out std_logic_vector (7 downto 0); yhh : out std_logic_vector (7 downto 0); ampm : out std_logic);
end clock2; architecture behavioral of clock2 is component svnsegdrv port( din : in std_logic_vector(3 downto 0); segs : out std_logic_vector(7 downto 0) ); end component; signal d0 : std_logic_vector(3 downto 0) := (others => '0'); signal d1 : std_logic_vector(3 downto 0) := (others => '0'); signal d2 : std_logic_vector(3 downto 0) := (others => '0'); signal d3 : std_logic_vector(3 downto 0) := (others => '0'); signal c : std_logic_vector(27 downto 0) := (others => '0'); signal ck : std_logic; signal sampm : std_logic := '0'; begin process(clk, ck) begin if rising_edge(clk) then --ck'event and clk='1' then c<=c+1; end if; if rising_edge(ck) then if d0="1001" then d0 <= (others => '0'); if d1="0101" then d1 <= (others => '0'); if d2="1001" or (d2="0001" and d3="0001") then d2 <= (others => '0'); if d3="0001" then d3 <= (others => '0'); sampm <= not sampm; else d3<=d3+1; end if; else d2<=d2+1; end if; else d1<=d1+1; end if; else d0<=d0+1; end if; end if; end process; dd0: svnsegdrv port map(din => d0, segs => yml ); dd1: svnsegdrv port map(din => d1, segs => ymh ); dd2: svnsegdrv port map(din => d2, segs => yhl ); dd3: svnsegdrv port map(din => d3, segs => yhh ); ampm <= sampm; ck <= c(23) when (csel(0)='1') else c(20) when (csel(1)='1') else c(17) when (csel(2)='1') else c(14); end behavioral;
VHDL
VHDL
FPGA
hex
n-bit x n-bitn
FPGA.ucf
pull-upucf
FPGA
FPGA.ucfFPGA
VHDL code for keypad decoding library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock2 is
port ( clk : in std_logic; column : in std_logic_vector (3 downto 0); csel : in std_logic_vector (2 downto 0); row : out std_logic_vector (3 downto 0); y : out std_logic_vector (7 downto 0); cout : out std_logic_vector (7 downto 0); ampm : out std_logic); end clock2; architecture behavioral of clock2 is component svnsegdrv port( din : in std_logic_vector(3 downto 0); segs : out std_logic_vector(7 downto 0) ); end component; signal count : std_logic_vector(3 downto 0) := (others => '0'); signal reg : std_logic_vector(3 downto 0) := (others => '0'); signal decode : std_logic_vector(3 downto 0) := (others => '0'); signal c : std_logic_vector(27 downto 0) := (others => '0'); signal ck : std_logic; signal regclk : std_logic := '0'; begin process(clk) begin if rising_edge(clk) then --ck'event and clk='1' then c<=c+1; end if; end process; process(ck) begin if rising_edge(ck) then if count="1111" then count <= (others => '0'); else count<=count+1; end if; if regclk='1' then reg <= count; end if; end if; end process; process (count(1 downto 0),column(0),column(1),column(2),column(3)) begin case count(1 downto 0) is when "00" => regclk <= not column(0); when "01" => regclk <= not column(1); when "10" => regclk <= not column(2); when "11" => regclk <= not column(3); when others => regclk <= not column(0); end case; end process; dd0: svnsegdrv port map(din => count, segs => cout ); dd1: svnsegdrv port map(din => reg, segs => y ); ck <= c(23) when (csel(0)='1') else c(20) when (csel(1)='1') else c(17) when (csel(2)='1') else c(14); with count(3 downto 2) select row <= "0111" when "00", "1011" when "01", "1101" when "10", "1110" when others;
end behavioral;
FPGA
BCD
LED
truncationLED
start state 1 1 1 1 1 1 1 1
shift #1 1 1 1 1 1 1 1 1
shift #2 1 1 1 1 1 1 1 1
shift #3 , 7>4 1 1 1 1 1 1 1 1
add with 3 1 1 +
result 1 0 1 0 1 1 1 1 1
shift #4, 5>4 1 0 1 0 1 1 1 1 1
add with 3 1 1 +
result 1 1 0 0 0 1 1 1 1
shift #5 1 1 0 0 0 1 1 1 1
shift #6, 6>4 1 1 0 0 0 1 1 1 1
add with 3 1 1 +
result 1 0 0 1 0 0 1 1 1 1
shift #7, 7>4 1 0 0 1 0 0 1 1 1 1
add with 3 1 1 +
result 1 0 0 1 0 1 0 1 0 1
shift #8 1 0 0 1 0 1 0 1 0 1
Source (binary)Destination (BCD)
x1x10x100function
BCD
BCD
BCDBCD
BCD
BCDn
mn
m
m
n
BCD
BCD
BCD
BCDBCD
bps
dipswitchascii
bps
bps
RS232
“1”“0”
start bit
parity
“1”
stop bit
“1”idle
bps
RS232DD
“1”“0”
stopidlestart
“1”
“0”framing error
parity error
bpsdipswitch
ascii
bps
bps
o
o
o
(busy)
