cmos rf power amplifiers: nonlinear, linear, linearized

CMOS RF Power Amplifiers:Nonlinear, Linear, Linearized

David Su

Atheros Communications

Sunnyvale, California

2 of 41 IEEE Local Chapter Nov 2002

Outline

1.

• Introduction• Nonlinear Power Amplification• Linear Power Amplification• Linearization using Envelope

Elimination and Restoration• Conclusion


RF Power Amplification

• Purpose: Delivers “narrow-band” RF power to a

50-ohm antenna

• Performance:Output Power

Efficiency

Linearity

Antenna

Transmitter RF PA


Traditional PA Classification

Class Modes ConductionAngle

OutputPower

MaximumEfficiency Gain Linearity

ACurrentSource

100% moderate 50% Large Good

B 50% moderate 78.5% Moderate Moderate

C < 50% small 100% Small Poor

D

Switch

50% large 100% Small Poor

E 50% large 100% Small Poor

F 50% large 100% Small Poor


PA Classification & Input Drive

Vdd

0

2Vdd

0 100%

Class C Class Class ABB

ClassA

ClassD,E,F Switch

CurrentSource

Conduction Angle (VDC)

Inp

ut

Sig

nal

Ove

rdri

ve(V

in)


Power Amplifier Classification

Vdd

0

2Vdd

0 100%

Class C Class Class ABB

ClassA

ClassD,E,F

SaturatedClass A

Switch

CurrentSource

SaturatedClass C

Conduction Angle (VDC)

Inp

ut

Sig

nal

Ove

rdri

ve(V

in)


CMOS for RF Power Amplification

• Traditional RF PAs use GaAs / Bipolar.

• Advantages of CMOS:Low cost, high-yield, high-integration

Efficient switched-mode amplifier

• Disadvantages of CMOS:Low bandwidth

Low breakdown voltage


Simplified RF Output StageVDD

IDCL

VDD

VD

ID

Vin

+

–

IDC

CGS

CGD

RL

CC

gm VinIL

ID gmVin=

IL

VDDRL

-------------≤

VL

Vin ro

ID

VD

VDD

IDC


C

RL

RL

AC Equivalent Model

Class-A (Linear) Operation

Pout 12--- I

L2

RLVDD

2

2RL----------------≤=

For Pout = 1 W (Class A), RL = 4.5 Ω @ VDD = 3VRL = 3.1 Ω @ VDD = 2.5V

⇒Needs Impedance Transformation Network → 50 Ω antenna⇒Keep parasitic loss << RL of 3.1 Ω

L

VDD

IL

VDDRL

-------------≤

Vin


Efficiency of Class A operation

MatchingNetwork

PD

ID

L

VDD

VD

ID+

–

Pout VDD2

2RL----------------≤

Psupply IDCxVDDVDD

2

RL----------------= =

Efficiency PoutPsupply------------------------- 50%≤=

VD

Vin

VDD

IDC

IDCC

Vin

PD = ID x VD ↓ ⇒ Efficiency ↑

RL


Efficiency-Linearity Tradeoff

PD

ID

VD

Vin

MatchingNetwork

L

VDD

VD

ID+

–

• Large input signal

• Square wave output ID and VD

• Non-overlapping ID and VD1.

Pout VDD2

RL----------------=

IDC

C

Vin

PD = 0 ⇒ Efficiency =100%


Low-Voltage Operation

0 0.5 1.0 1.50

1

2

3

4

5

6

7

8

9

10

Ideal Output Power (W)

Eq

uiv

alen

tL

oad

Res

ista

nce

(Ω)

Class A,B

Class C

25%

Idc

VDD = 3V

RloadM1

10%5%

Pout VDD2

nRload----------------------≈

RloadVDD

2

nPout------------------≈

SwitchedMode

Class A,B: n = 2Class C: n > 2

Switched-Mode: n = 1


L

VDD

VD 50 ohm

+

–

IDC

Vin

Practical Power Amplifier DesignImpedance

Transformation

HarmonicTuning

VDC

InputDrive

3

2

1

LOAD PULL Optimization1. Impedance transformation: Output Power2. Harmonic Tuning: short @ 2fc & open@ 3fc for non-overlap ID & VD to

maximize efficiency3. Input drive: VDC -> Conduction Angle; Vin -> current source vs switch


Nonlinear Power Amplifier

• Hewlett Packard Labs(with W. McFarland)

• 800-MHz 32dBm AMPS PA with 42 %PAE in 0.8 µm CMOS


Choose n = 1.5 (assume 67% efficiency due to Ron > 0),VDD = 2.5V,For Pout = 1 W,

Rload = 4.2 Ω [Pout = VDD2/n Rload ]IDC = 0.49A [IL (peak) = IDC & Pout = 0.5 x IDC

2 x Rload]Ron = 1 Ω [Assume no overlap; PD = 0.5W = 0.5 x (2 IDC)2 x Ron]

⇒ Output transistor sizing: Ron < 1 Ω

Switched-Mode Design

MatchingNetwork

Antenna

L

VDD

Ron

Rload

RloadVDD

2

nPout------------------≈

IDC

Pout VDD2

nRload----------------------≈


Output Stage Design

IN A = 25dB5dBm

OUT

50Ω

VDD=2.5V

3.8nH 3.8pF

7.6pF2.5Vp

25pF

Zload

VD

ID

107 108 109 1010 10111

Frequency (Hz)

VD

ID +

–

Q~5101

|Zload|

102

103

104

Imp

edan

ce(o

hm

)

8400/1


Complete Amplifier

IN

OUTL1L2L3

M2

M150

Cp

VDD

M3

M4

M4c200

L4c

CMOS IC bond wiresL4

RF choke

Freq 824 – 849 MHz

VDD 2.5V

Pout 30 dBm


Die Photo 0.8µm CMOS

1.5 mm2


Power Supply Voltage (Volts)

Ou

tpu

tP

ow

er(d

Bm

)

Po

wer

Ad

ded

Eff

icie

ncy

(%)

1.0 1.5 2.0 2.5 3.010

15

20

25

30

35

40

45

50

10

15

20

25

30

35

40

45

50

Measured POUT and Efficiency

Efficiency

Power

Drain Efficiency ~ 68%


Linear Power Amplifier

• Atheros Communications(with D. Weber et al)

• 5-GHz 18dBm OFDM PA for IEEE802.11a in 0.25 µm CMOS


Spectral-Efficient Modulation

• 64-QAM (Quadrature Amplitude Modulation)— Large signal to noise ratio > 30dB

• OFDM (Orthogonal Frequency Division Mux)— Large peak to average power ratio of or

17dB52

Requires High Linearity in PA


Power Amplifier Design• Large peak to average ratio (PAR) of or 17dB

• Signal peaks are infrequent: 0.25dB SNRdegradation when PAR reduced to 6dB for16-QAM*.

• Implications:- Poor power efficiency- With 6dB PAR, to obtain 40mW (16dBm) requires

Psat of ~22dBm or 160mW- With 17dB PAR, to obtain 40mW (16dBm) requires

Psat of ~33dBm or 2W

*Van Nee & Prasad, OFDM for Wireless Multimedia Communications,Artech House, 2000

52


Linear PA makes efficient radios

• Frequency bandwidth is precious--> Maximize network capacity

• Energy/bit (battery life)More bits sent per second--> PA + the rest of the radio

are ON for shorter duration


Linear PA Design• Input load impedance

- signal dependency- cascode

• VGS overdrive- dc bias with capacitive level-shift

• Output load impedance- impedance matching network

• Stability- cascode


Power Amplifier Topology

Output

Bias

L3

Input

L2*

M2 M3

C2

L4*

Vpa = 3.3V • Class A operation

• Cascoded- 3.3V supply voltage- Stability

• Capacitive Level-shift- Metal-2,3,4,5 stacks

• Inductive loads

• Differential- Off-chip balun

* C.P. Yue and S.S. Wong, IEEE JSSC, May 1998


Power Amplifier Schematic

Vin+Vin-

Vpa=3.3V

L1p

C1pVout+

Bias

L3p

Bias

L2p

M2pM3p

C2p

L4p

L1n

C1nVout-

Bias

L3n

Bias

L2n

M2n M3n

C2n

L4n

PSAT = 22 dBm


Die Photograph

Tx

Rx

Synth

Bias

Log

ic


Measured BPSK OFDM Spectrum

16.25MHz

POFDM = 17.8 dBm


Measured Transmit Output Power

6 9 12 18 24 36 48 54

12

14

16

18O

FD

MO

utp

ut

Po

wer

(dB

m)

Data Rate (Mbps)

10


Linearized Power Amplification

• Hewlett Packard Labs(with W. McFarland)

• Linearization IC for NADC withefficiency improvement from 36% to49% using envelope elimination andrestoration


Applying Integration to RF PA

Transistors are cheap.• LARGE Output Power: Use switched-mode output stage• HIGH Efficiency: Use switched-mode output stage• GOOD Linearity: Use linearization circuits so that the output

stage does not need to be linear.

SOLUTION: Switched-mode output stage+ linearization.


Gate

VDD

Envelope Elimination and Restoration

Limiter

RF Input

RF Output

Phase

Amplifier

Ref: L. Kahn, Proc IRE, July 1952

Magnitude

EnvelopeDetector

Switched-Mode PA

Amplifier

Combiner


Closed-Loop EER Implementation

Limiter

RF Input RF OutputMagnitude

PhaseRF PowerAmplifier

Atten.

+

_

SwitchingPower Supply

∆-Mod Class-D

Σ

Buffer

EnvelopeDetector

EnvelopeDetector


∆-Modulated Switching Power Supply

• Closed-loop system• Modulation to generate a two-level output

⇒ Pulse width modulation vs. Delta modulation

• Efficient Class-D driver

+_

Load

Σ

LowpassFilter

Modulation

Ref Out

Class-DDriver


Switched-cap Circuit for ∆ Modulation

Subtraction &Compensation

OutputBuffer

Comparator LowpassFilter

Off-Chip

φ1

φ1

φ2

φ1

φ1

φ2

φ2

φ1

φ1

φ2

φ2

φ1

φ2

φ2

φ1

φ1

φ2

φ2


Die Photograph

Buffer∆-Mod SwitchingPower Supply

EnvelopeDetector

(2 mm2)(1.9 mm2)

(0.03 mm2)

(0.34 mm2)Limiter


Supply Voltage 3.0V

Output Voltage 0.1 to 2.65V

Output Current 0.75 A

Bandwidth 100 kHz

Harmonic Distortion –55 dBc

Efficiency 80%

Die Area 3.9 sq mm

Switching Power Supply

Frequency (in kHz)

Ou

tpu

tS

pec

tru

m(i

nd

B)

0 20 40 60 80 100–80

–70

–60

–50

–40

–30

–20

–10

0


Spectral Mask of CMOS PA

836.5M

–60

–40

–20

0

Am

plit

ud

e(1

0d

B/d

iv)

Frequency (15kHz/div)

Saturated Output

Linearized Output

RBW: 300 HzVBW: 100 Hz

836.395M 836.605M

ACP1 –30dBc

ACP2 –48dBc


π/4 QPSK Constellation of CMOS PA

With LinearizationWithout Linearization

Mag Err = 2.2%rms

Phase Err = 1.5orms


Output Power (dBm)

linearized

original

10 15 20 25 300

10

20

30

40

50

60

Po

wer

-ad

ded

Eff

icie

ncy

(%)

nonlinear

Peak Linear Power: 26.5dBm → 29.5dBm

Peak Linear PAE: 36% → 49%

Efficiency of 4.8-V GaAs PA


Conclusion

• Nonlinear (switched-mode) PA provides(+) large output power and high efficiency(–) poor linearity

• Linear PA provides(+) linearity, spectral efficiency(-) poor efficiency

• Linearization using envelope elimination andrestoration(+) linear RF output + high efficiency(-) implementation complexity

cmos rf power amplifiers: nonlinear, linear, linearized

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