cmos latches and flip-flops · sequential digital circuits à two main data storage mechanisms: i...
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CMOS Latches and Flip-Flops
João Canas Ferreira
University of PortoFaculty of Engineering
2016-05-04
Topics
1 General Aspects
2 Circuits based on positive feedback
3 Circuits based on charge storage
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 2 / 30
Sequential digital circuits
à Two main data storage mechanisms:
I positive feedbackI electric charge storage
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 3 / 30
Latch vs. register (flip-flop)
D
Clk
Q D
Clk
Q
Clk Clk
D D
Q Q
Latch stores data while clock is low(level-sensitive circuit)
Register stores date on rising clockedge (edge-triggered)
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 4 / 30
Latches
Source: [Rabaey03]
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 5 / 30
Circuits with latches
Latch N is transparent for φ = 0 Latch P is transparent for φ = 1
NLatch
Logic
Logic
PLatch
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 6 / 30
Timing parameters
t
CLK
t
D
tc-q
tholdtsu
t
Q stabledata
stabledata
Register
CLK
D Q
tsu how long the input data must be stable before the active clock edge
thold how long the input should remain stable after the active clock edge
tc-q output propagation delay referred to the clock edge
tplogic worst propagation delay through combinational logic
tcd smallest propagation delay through combinational logic (contamination delay)
à Conditions for correct operation: T ≥ tc−q + tplogic + tsutcdreg + tcdlogic ≥ thold
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Timining characterization
D Q
clk
D Q
clk
tc-q tc-q
td-q
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 8 / 30
Positive feedback implies bistability
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 9 / 30
Topics
1 General Aspects
2 Circuits based on positive feedback
3 Circuits based on charge storage
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 10 / 30
Latches based on multiplexers
CLK
1
0D
Q 0
CLK
1D
Q
Q=Clk⋅QClk⋅InQ=Clk⋅QClk⋅In
negative latch positive latch
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 11 / 30
CMOS latch
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 12 / 30
Latch: alternative implementation
à Only uses NMOS pass transistors Important: There should be no over-lap of the clock signals
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 13 / 30
Master-slave register
Source: [Rabaey03]
à Two latches of opposite polarity (master: negative, slave: positive)à The register is positive edge-triggered (active edge is the rising edge)
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Master-slave register: implementation
Source: [Rabaey03]
tsu = 3 × tpd_inv + ttp_dx
tc−q = tpd_inv + ttp_dx
thold = 0
à Main issue: relatively large chargeon the clock signal
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Propagation delay
tc−q(lh) = 23 ps FreePDK45 technology tc−q(hl) = 26 psJoão Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 16 / 30
Setup time simulation
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 17 / 30
Setup time violation (simulation)
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Clock load reduction
Source: [Rabaey03]
à I2 and I4 should be weak inverters (ratioed circuit)à Reverse current is, typically, not a problem.
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 19 / 30
Issue: clock signal overlap
Source: [Rabaey03]
à There is a direct path between D and Q (overlap on the rising edge)à Contention on node Aà Main solution: avoid overlapping clock signals or use pseudo-static register.
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 20 / 30
Forcing the feedback loop
Source: [Rabaey03]
I set/reset latch based on NOR gatesI fully asynchronous (is not a good match to the synchronous design style)
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 21 / 30
SR latch with clock signal
Source: [Rabaey03]
à Better for use in synchronous circuitsà Sizing problem: how should transistors M5-M6 and M7-M8 be sized?
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 22 / 30
Dimensioning exampleM5 n1 s 0 0 NMOS+ L=50n W=’factor*90n’M6 qbar clk n1 0 NMOS+ L=50n W=’factor*90n’* FreePDK45 technology
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Topics
1 General Aspects
2 Circuits based on positive feedback
3 Circuits based on charge storage
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 24 / 30
Static vs. dynamic latch
Static Dynamic
Source: [Rabaey03]
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Dynamic registerPositive edge-triggeredtsetup < tx_gate
thold = 0tc−q < 2× tpinv + tx_gate
Source: [Rabaey03]
à Clock overlap is a significant issue
t0−0 < tT1 + tI1 + tT2t1−1 < tholdSource: [Rabaey03]
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Pseudo-static latch
Source: [Rabaey03]
I Much better noise immunityI The feedback inverter must be “weak”.
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 27 / 30
C2MOS latches and registersà C2MOS: Clocked CMOS
Source: [Rabaey03]
à Immune to clock overlap if the rise/fall times are sufficiently small.
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 28 / 30
Behavior for overlapping clock signals
At X: possible transition 0→1 At X: possible transition 1→0 (def. hold time)
à During the overlap only one of the pull-up or pull-down networks is active.
João Canas Ferreira (FEUP) CMOS Latches and Flip-Flops 2016-05-04 29 / 30
References
à Some of the figures come from the book:
Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2nd
edition,Prentice Hall, 2003.http://bwrc.eecs.berkeley.edu/icbook/
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