Lecture 1

1

1

The Future of CMOSThe Future of CMOS

David Pulfrey

2

CHRONOLOGY ofCHRONOLOGY ofthe FETthe FET

• 1965 Commercialization (Fairchild)

• 1991 “The most abundant object

made by mankind’’ (C.T. Sah)

• 2003 The 10 nm FET (Intel)

• 1933 Lilienfeld’s patent (BG FET)

Lecture 1

2

3

SCALING: WHY DO IT?SCALING: WHY DO IT?

• Increase speed

• Increase density

• Reduce cost (?)

4

SCALING: SPEEDSCALING: SPEED

VDD=0.75V0.85V

Published data

Intel data

NMOS

1.45 THz2.63 THz

VDD=0.8V

Gate Length (nm)

Gat

e D

e lay

(ps)

10 100 1000

101

102

100

10-1

Morkoc04

CV/I

Lecture 1

3

5

SCALING: DENSITYSCALING: DENSITY

Perlmutter04, Raghavan00

P4 (130): 55M in 146 mm2

P4- Prescott (90): 125M in 112 mm2

P4- Dothan (90): 140M in 87 mm2

6

SCALING: COSTSCALING: COST

Lecture 1

4

7

SCALING: FACTORY COSTSCALING: FACTORY COST

Moore’s Law for Fabs!

MIT02

Intel 300mm

8

THE SHRINKING FETTHE SHRINKING FET

Leff reduced 30XBut devices are still “well tempered”

So urce

NCHW B

n+poly

NSUB

Dr ai n

oxide

Ln+ n+

ga te

xj

VDD

Lint

y

xCMOS 3 CMOS P18 CMOS P13 90NM

1987 2001 2002 2003

L nm 3000 180 130 100LINT nm 700 10 0 2.5XJ nm 1000 160 190 150TOX nm 85 4.1 2.8 2.3NCH cm-3 1.00E+16 3.90E+17 6.15E+17 8.37E+17VDD V 5.0 1.8 1.2 1.0VTHO V 0.95 0.47 0.35 0.24

Tox

Lecture 1

5

9

THE SIGNIFICANCE OF ETHE SIGNIFICANCE OF EXX AND EAND EYY

Ex < Ey = diode

Ex > Ey = transistor

• keeping Ex> Ey

• and avoiding the short- channel effect

NSUBx

VDD

TOX

XJLD

L

y

Well tempered means:

10 Pulfrey89

SHORTSHORT--CHANNEL EFFECT: CHANNEL EFFECT: VVTT depends on Ldepends on L

Charge under gate due to E from G, S and D

L′

L

ox

BT C

QV ∆=∆

• Geometrical constructionto estimate VT drop due to E encroachment

• Reduce junction depth

Lecture 1

6

11

Raised S and DRaised S and D

xj

Gargini02a

• Improves ION by 20- 30%

12

Current and Current and EEyy

1985 2003 200?

VDD,V 5 1 0.8

L, nm 3000 100 15

"Ey",mV/nm

1.6 10 53

factorbody 2

)( 2

=

−=

mmVV

CLZI TGS

oxDsat µ

1)(andLoftindependeni.e.

)(

TGS

TGSsatoxDsat

VVf

VVZCI

−

−= υ

Lecture 1

7

13

MOBILITYMOBILITY

• FETs don’t operate at high Ey all the time,

or over all of the channel.

• High mobility still very desirable to increase drive current

• Get high µ from strained-silicon channel

14

SiSi on on SiGeSiGe: Tensile strain: Tensile strain

IBM04

Lecture 1

8

15

Strained Strained SiSi: breaking the symmetry: breaking the symmetry

• 6 equivalent directions

• Intervalley scattering

• 2 sub- bands lowered in energy• Reduced intervalley scattering• Decreased effective mass (horizontal)

16

Strained Strained SiSi: Relaxed sub: Relaxed sub--layerslayers

IBM04

Lecture 1

9

17

18

Current and VCurrent and VTT

Decreasing (VDD - VT ) means a loss of gate overdrive

Morkoc04

• Ultimate VT ≈ 0.2 V

• Determined by ID,subt

10-2

10-1

100

101

101 102 103

VDD

VT

Channel length (nm)

Pow

er s

uppl

y (V

),Th

r esh

old

Volta

ge (V

)

ECE1

E0

Quantization important

Lecture 1

10

19

S

B

G

CB

ICOX

:

1

factorbodythem

mV

CC

VV GS

ox

B

GSSIB =

+=≡ψ

It’s done by capacitive control of the source- channel barrier height

Control of Control of IID,subtD,subt

Ec

⎟⎠⎞

⎜⎝⎛

mqVT

OFF

THRESHOLD

SOURCE DEPLETION

⎥⎦

⎤⎢⎣

⎡−==

t

TthreshDGSsubtD mV

VIVI exp)0( ,,

This sets lower limit to VT, e.g., 0.2Vi.e., ION/IOFF ≈104

20

KVmVmdV

IdS

t

GS

D

300at 060.0303.2

log1

10

==

⎟⎟⎠

⎞⎜⎜⎝

⎛=

−

Aox

B

ox

ox

s

ox

B

NsmallandtsmallNeed

Wt

CC

mcall

:

11:Re ⋅+=+=εε

It’s the VGS needed to reduce ID by 10X

SubSub--Threshold SlopeThreshold Slope

T reduce ∴=q

kTVt

VT compromiseGate leakage

Lecture 1

11

21

(b) FN tunneling(c) direct tunneling

de Broglie wavelength:KEm

hmvh

.2==λ

For an electron in Si at KE=φox/2 : λ = 6.1 nm

Electron could be either side of the barrier!

2.3nm

Taur98

ColdCold--Electron TunnelingElectron Tunneling

22

λπa

AA

Tinc

trans 4expy probabilit Tunneling 2

2 −≈=

= 0.0002 for 180nm= 0.0031 for 130nm= 0.0088 for 90nm

What is a tolerable gate current?

Taur98

Tunneling FactsTunneling Facts

Lecture 1

12

23

Ultimate SubUltimate Sub--Threshold CurrentThreshold Current

• S → D tunneling

<V t

Gate controlledbarrier

Source

Drain

Short channel,

moderate drain bias

direct

Short channel,larger drain bias

Gate controlledbarrier ?

Source

Drain

<Vt

Zener

• Expected to occur at L ≈ 10 nmMorkoc04

24 Chau03

Lecture 1

13

25 Chau03

26 Frank02

Power constrained scaling limitsPower constrained scaling limits

It is power dissipation, rather than scaling, that will be the limiting factor

e.g., can scale big servers more aggressively than portables and SRAMs

Lecture 1

14

27

HighHigh--k dielectricsk dielectrics

ox

oxox T

Cε

=• High TOX needed to reduce gate leakage• High COX needed for ID and S• Resolve conflict by increasing ε

Wong02

28

HighHigh--k dielectrics: tunnelingk dielectrics: tunneling

λπa

AA

Tinc

trans 4exp yprobabilit Tunneling 2

2 −≈=

∫ −−

=a

dxExVmh

T0

])([24expy probabilit Tunneling π

oxhigh a Need φ∴

Lecture 1

15

29

HighHigh--k dielectrics: contendersk dielectrics: contenders

Wong02

• must withstand

poly activation (950C)

• or use metal gate

Also:

30

Metal gate: selfMetal gate: self--alignmentalignment

Poly gates made self- alignment possible

• Perhaps use sacrificial poly gate,

• then deposit metal.

• Co- evaporation of metals (Ti and Ni)

to obtain different work functions,

• i.e., different VT’s for NMOS and PMOS

or for different blocks on same wafer.

Possibilities:

Lecture 1

16

31

Metal gate and NMetal gate and NSUBSUB

• If VT controlled by metal, perhaps can use undoped Si substrate.

• This would remove the problem of dopant fluctuations.

Gargini02

32

Beyond Planar CMOSBeyond Planar CMOS

Planar CMOS:Planar CMOS:• 10 nm prototypes demonstrated• raised source and drain• strained Si• high- k dielectric• metal gate• limitation is power dissipation

• Double gate CMOS• SOI CMOS

Further improvements:Further improvements:

Lecture 1

17

33

DoubleDouble--Gate CMOSGate CMOS

• SCE controlled by device geometry, not doping

• Can use undoped channel - reduces statistical fluctuations and Zener BD

• Increased Cox improves ION and SWong02

• Design flexibility - different VG’s and Tox’s

34

SCE: VSCE: VTT RollRoll--offoff

Philips04, MIT02

Note: benefit of

shrinking dSi

DIBL

Lecture 1

18

35

ox

B

CC

mq

kTmScall +== 1303.2:Re

DG: Improved ON/OFF ratioDG: Improved ON/OFF ratio

DG doubles without reducing Tox

Tends to zero (small dSi and inversion from top and bottom)

• For same IOFF, set VT 60mV lower, get more ION

36

DG example: FINFETDG example: FINFET

• DG is a deeply scalable FET, but fabrication is difficultWong02

Lecture 1

19

37

• More easily fabricated• Ultra thin body• No leakage through substrate• Very low Cj

• Good device isolation for RF• Technology of choice for SOC • Not as deeply scalable as DG

SOI CMOSSOI CMOS

Gargini02a

SIMOX

38

SOI: stateSOI: state--ofof--thethe--artart

• Small L, xj, dSi

Chau03

• Fully depleted• Raised S and D

Lecture 1

20

39

ConclusionConclusion

• Planar CMOS: 10nm - THz operation - millions of transistors

• DG CMOS: reduced SCE - best sub- threshold slope

- high performance digital

• SOI CMOS: reduced leakage and parasitic C - RF capable

• Do we, or our children, need anything more?

CMOS

40

ReferencesReferences

Chau03 - ftp://download.intel.com/research/silicon/Chau%20DRC%20062303%20foils.pdfDavid04 - ftp://download.intel.com/research/silicon/Ken_David_GSF_030604.pdfFrank02 - Frank D.J, IBM J. R&D, v46, 235, 2002Gargini02 - ftp://download.intel.com/research/silicon/PaoloISSUS0102.pdfGargini02a - ftp://download.intel.com/research/silicon/Paolo%20M2S2%200902.pdfIBM03 - http://www- 3.ibm.com/chips/services/foundry/offerings/sige/5hp/IBM04 http://www.research.ibm.com/resources/press/strainedsilicon/MIT02 http://ocw.mit.edu/NR/rdonlyres/Electrical-Engineering-and-Computer-Science/6-720JIntegrated-Microelectronic-DevicesFall2002/4E1C74EA-38FB-41CF-B654-3C5AD913B2E9/0/lecture33.pdMorkoc04 - Morkoc H., WOCSDICE, Slovakia, 2004Perlmutter04 - ftp://download.intel.com/research/silicon/Perlmutter053104.pdfPulfrey89 - Pulfrey D.L., N.G.Tarr, “Introduction to Microelectronic Devices”, Prentice-Hall, 1989Raghavan00 - Raghavan G. et al., IEEE Spectrum, v37(10), 47, 2000Rucker03 - Rucker R. et al., IEDM, paper 5.3, 2003Taur98 - Taur Y., T.H.Ning, “Fundamentals of Modern VLSI Devices”,Cambridge University Press, 1998Taur99 - Taur Y., IEEE Spectrum, 25, July 1999Wong02 - Wong H-S.P., IBM J. R&D, v46, 133, 2002Yeo02 - Yeo K-S. et al., “CMOS/BiCMOS VLSI”, Prentice-Hall, 2002