cmos funda full course

CADENCE CONFIDENTIAL1 CADENCE DESIGN SYSTEMS, INC.

SESSION 1: MOS THEORY

•Review of PN Junction•MOS Structure•Accumulation, cutoff, Inversion•MOS transistor•Threshold Voltage

2 CADENCE CONFIDENTIAL

Review of PN Junction

• Drift current: electrons and holes move in an electric field

(+)

holes

E field

electrons

• Diffusion current: electrons and holes move from high concentration to low concentration

Si Si Si Si

e-conc.

(-)


Review (cont)

• PN junction built-in potential

EC

EFnEFp

EV

qV0

• Fermi levels line up• Electrons traveling from right to left have to cross potential barrier of qV0

E field

NP- V0 +

2ln

i

DA

n

NN

q

kT

q

EEV inip

0


• When biased, electric field in depletion region changes

– Forward bias: reduces electric field

– Reverse bias: increases electric field

• Electric field is a result of uncovered charges. Therefore depletion width must change

– Forward bias: less charges needed. Depletion width reduces

– Reverse bias: more charges needed. Depletion region increases.

Bias Effect on Depletion Width


0

)(2V

NN

NN

qW

da

dad

Width of depletion region:

VVNN

NN

qW

da

dad

0

)(2

Width of depletion region with bias V:

Bias Effect on Depletion Width


• Forward bias: barrier lowered, diffusion current dominates

• Reverse bias: barrier raised, only current is small drift current of minority carriers

• Diode only lets current flow in one direction

• Diode equation:

)1( /0 kTqVeII

I0 = generation current

Diode Equation


• Separated charges result in depletion region capacitance

• Similar to parallel-plate capacitor

E field

NP

ad

adj NN

NN

VV

qAC

0

2

2

)(2 0 VV

NN

NNqAQ

ad

adj

Charge in depletion region: Capacitance:

Capacitance of P/N Junction


MOS structure

• MOS: Metal-oxide-semiconductor

– Gate: metal (or polysilicon)

– Oxide: silicon dioxide, grown on substrate

• MOS capacitor: two-terminal MOS structure

Si substrate

Oxide (SiO2)

Metal gate (Al)

Body or substrate terminal

Gate terminal


MOS Energy Band Diagram

• Work function (qM, qS): energy required to take electron from Fermi level to free space

• Work function difference between Al and Si

• At equilibrium, Fermi levels must line up

qM

EC

Ei

EFp

EV

qS

E0

EFm

oxidebandgap8ev

OxideMetal p-type Si

qoxide qS


MOS Energy Band Diagram

EFp

EV

EC

M O S (p-type)

• Bands must bend for Fermi levels to line up

• Part of voltage drop occurs across oxide, rest occurs next to O-S interface

• Amount of bending is equal to work function difference: qM - qS

Ei

EFm

qFqS

F = Fermi potential (difference between EF and Ei in bulk)

S = surface potential


Flat-Band Voltage

• Flat-band voltage

– Built-in potential of MOS system

– Work function difference: VFB = m - S

– Apply this voltage to “flatten” energy bands


MOS capacitor operation

• Assume p-type substrate

• Three regions of operation

– Accumulation (VG < 0)

– Depletion (VG > 0 but small)

– Inversion (VG >> 0)

P-type Si substrate

VB = 0

VG


Accumulation

• Negative voltage on gate: attracts holes in substrate towards oxide

• Holes “accumulate” on Si surface (surface is more strongly p-type)

• Electrons pushed deeper into substrate

P-type Si substrate

VG < 0

VB = 0

EFpEV

EC

Ei

EFm

qVG


Depletion

• Positive voltage on gate: repels holes in substrate

– Holes leave negatively charged acceptor ions

• Depletion region forms: devoid of carriers

– Electric field directed from gate to substrate

• Bands bend downwards near surface

– Surface becomes less strongly p-type (EF close to Ei)

P-type Si substrate

VG > 0

VB = 0

Depletion regionEox

EFp

EV

EC

EiEFm

qVG


Depletion region depth

• Calculate thickness xd of depletion region

– Find charge dQ in small slice of depletion area

– Find change in surface potential to displace dQ by distance xd (Poisson equation):

xd

dx

dQdxqNdQ A

SiA

Si

dxxqNd

dQxd


Depletion region depth (cont.)

– Integrate perpendicular to surface

– Result:

Si

dAFS

x

Si

AS

xqN

dxxqN

ddS

F

2

2

2

0

A

FSSid qN

x

2


Depletion region charge

• Depletion region charge density

– Due only to fixed acceptor ions

– Charge per unit area

FSSiA

dA

qNQ

xqNQ

2


Inversion

• Increase voltage on gate, bands bend more

• Additional minority carriers (electrons) attracted from substrate to surface

– Forms “inversion layer” of electrons

• Surface becomes n-type

P-type Si substrate

VG >> 0

VB = 0

EFpEV

EC

Ei

EFm

qVG

electrons

Eox


• Definition of inversion

– Point at which density of electrons on surface equals density of holes in bulk

– Surface potential is same as F, but different sign

EV

EFp

Ei

EC

qF

qS = -qF

Remember:

qF = EF - Ei

Inversion


MOS transistor

• Add “source” and “drain” terminals to MOS capacitor

• Transistor types

– NMOS: p-type substrate, n+ source/drain

– PMOS: n-type substrate, p+ source/drain

source drain

P-substrate

N+ N+

NMOS

source drain

N-substrate

P+ P+

PMOS


MOS Transistor

• Important transistor physical characteristics

– Channel length L

– Channel width W

– Thickness of oxide tox

L

Wtox


MOS transistor operation

• Simple case: VD = VS = VB = 0

– Operates as MOS capacitor

• When VGS<VT0, depletion region forms

– No carriers in channel to connect S and D

source drain

P-substrate

VB = 0

Vg < VT0

Vd=0Vs=0

depletionregion


MOS transistor operation

• When VGS > VT0, inversion layer forms

• Source and drain connected by conducting n-type layer (for NMOS)

source drain

P-substrate

VB = 0

Vg > VT0

Vd=0Vs=0

depletionregion

inversionlayer


MOS transistors Types and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact


Threshold voltage

• Threshold voltage (VT0): voltage between gate and source required for inversion

– Transistor is “off” when VGS < VT0

• Components:

– Work function difference between gate and channel (Flat-band voltage)

– Gate voltage to change surface potential

– Gate voltage to offset depletion charge

– Gate voltage to offset fixed charges in gate oxide and silicon-dioxide interface


Threshold voltage (1)

• Work function difference GC between gate and channel

– Represents built-in potential of MOS system

– For metal gate: GC = F(substrate) - M(gate)

– For poly gate: GC = F(substrate) - F(gate)

GCTV 0



• First component accounts for built-in voltage drop

• Now apply additional gate voltage to achieve inversion: change surface potential by -2F

FGCTV 20



• Offset depletion region charge, due to fixed acceptor ions

• Calculate charge at inversion (S =-F)

– From before:

– So:

– For non-zero substrate bias (VSB 0):

Due to larger depletion region

FSSiAqNQ 2

FSiAB qNQ 220

SBFSiAB VqNQ 22


Threshold voltage (3, cont.)

• To offset this charge, need voltage -QB/Cox

• Cox = gate capacitance per unit area

– Cox=ox/tox

– tox = thickness of gate oxide

ox

BFGCT C

QV 20



• Correct for non-ideal fixed charges

– Fixed positive charge density Qox at boundary between gate oxide and substrate

– Due to impurities, lattice imperfections at interface

– Correct with gate voltage = -Qox/Cox

• Final threshold voltage formula (for NMOS):

ox

ox

ox

BFGCT C

Q

C

QV 0

0 2


Threshold voltage

• General form (non-zero substrate bias):

• Can also write as:

• Replacing second term:

ox

ox

ox

BFGCT C

Q

C

QV 2

ox

BBTT C

QQVV 0

0

ox

SiA

FSBFTT

C

qN

VVV

2

220

Substrate-biascoefficient


Threshold voltage, summary

• If VSB = 0 (no substrate bias):

• If VSB 0 (non-zero substrate bias)

• Body effect (substrate-bias) coefficient:

• Threshold voltage increases as VSB increases!

ox

ox

ox

BFGCT C

Q

C

QV 0

0 2

FSBFTT VVV 220

ox

SiA

C

qN

2


NMOS PMOS

Substrate Fermi potential F < 0 F > 0

Depletion charge density QB < 0 QB > 0

Substrate bias coefficient > 0 < 0

Substrate bias voltage VSB > 0 VSB < 0

Threshold Voltage (NMOS vs. PMOS)


Body effect

• Body effect: Voltage VSB affects threshold voltage of transistor

– Body normally connected to ground for NMOS, VDD for PMOS

– Raising source voltage increases VT of transistor

– Implications on circuit design

VT0

A

B

Vx

If Vx > 0, VSB (A) > 0,VT(A) > VTO


Threshold voltage adjustment

• Threshold voltage can be changed by doping the channel region with donor or acceptor ions

• For NMOS:

– VT increased by adding acceptor ions (p-type)

– VT decreased by adding donor ions (n-type)

– Opposite for PMOS

• Approximate change in VT0:

– Density of implanted ions = NI [cm-2]

– Assume all implanted impurities are ionized

ox

IT C

qNV 0


• 5 Minutes Break


MOS EQUATIONS – Lecture 1

•Cut-off, Linear, Saturation •Drain Current equations•MOS Characteristics•Oxide capacitance•Junction Capacitance


MOS transistor characteristics

• Three regions of operation: overview

– Cutoff: VGS < VT

No inversion layer formed, drain and source are isolated by depleted channel. IDS 0

– Linear: VGS > VT, VDS < VGS-VT

Inversion layer connects drain and source.Current is almost linear with VDS (like a resistor)

– Saturation: VGS>VT, VDSVGS-VT

Channel is “pinched-off”. Current saturates.


Cutoff Region

• VGS < VTN

• VGS > VTP

• Depletion region – no inversion

• Current between drain and source is 0

– Actually there is leakage current

source drain

substrate

VB

VG VDVS

depletionregion


Linear mode

• When VGS>VT, an inversion layer forms between drain and source

• Current IDS flows from drain to source (electrons travel from source to drain)

• Depth of channel depends on V between gate and channel

– Drain end narrower due to larger drain voltage

– Drain end depth reduces as VDS is increased

VB = 0

Vg > VT0Vd < VGS-VT0

depletionregion (larger at

drain end)Channel

(inversion layer)

source drain

P-substrate

VB = 0

Vg > VT0Vd < VGS-VT0Vs=0


Linear I/V Equation

• Gradual Channel Approximation:

– Assume dominant electric field in y-direction

– Current is constant along channel


Linear I/V Equation

• Assume that VGS > VT, then the charge induced per unit area in channel

)()( yVVVCyQ TGSoxI • The resistance dR of length dy of channel

)(yQW

dydR

In

• Where W is width of channel and μn mobility of electron.


Linear I/V Equation

• For current ID, drop across this resistance will be

• For total length L on integration we have

dVVVVCWdyI TGSox

V

n

L

D

DS

)(00

dyyQW

IdRIdV

In

DD )(


Linear I/V Equation

• Final equation for ID

221

DSDSTGSoxnD VVVVL

WCI

L

WCk oxnnn Device transconductance:

oxnn Ck 'Process transconductance:

221'

DSDSTGSnD VVVVL

WkI


Saturation mode• When VDS = VGS - VT:

– No longer voltage drop of VT from gate to substrate at drain

– Channel is “pinched off”

• If VDS is further increased, no increase in current IDS

– As VDS increased, pinch-off point moves closer to source

– High electric field in depleted region accelerates electrons towards drain

source drain

VB = 0

Vg > VT0Vd > VGS-VT0Vs=0

depletionregion

pinch-off point


Saturation I/V Equation

• As drain voltage increases, channel remains pinched off

– Channel voltage remains constant

– Current saturates

• To get saturation current, use linear equation with VDS = VGS - VT

2

21

TNGSoxnD VVL

WCI


MOS I/V Characteristics

• I/V curve for ideal MOS device

• VGS3> VGS2 >VGS1

Drain voltage VDS

Dra

in c

urre

nt I

DS

VGS1

VGS2

VGS3

Linear

Saturation


MOS I/V Characteristics

0.0 1.0 2.0 3.0 4.0 5.0

VDS (V)

1

2

I D (

mA

)

0.0 1.0 2.0 3.0VGS (V)

0.010

0.020

÷ I

D

VT

SubthresholdCurrent

Triode Saturation

VGS = 5V

VGS = 3V

VGS = 4V

VGS = 2V

VGS = 1V

(a) ID as a function of VDS (b) ID as a function of VGS

(for VDS = 5V).

Sq

ua

re D

ep

end

en

ce

VDS = VGS-VT

NMOS Enhancement Transistor: W = 100 m, L = 20 m


MOSFET Capacitances

• Oxide Capacitance

– Gate to Source overlap

– Gate to Drain overlap

– Gate to Channel

• Junction Capacitance

– Source to Bulk junction

– Drain to Bulk junction


• Overlap capacitances

– gate electrode overlaps source and drain regions

– LD is overlap length on each side of channel

– Leff = Ldrawn – 2LD

– Total overlap capacitance:

source drain

LD

Ldrawn

DoxGDOGSOO WLCCCC 2

Oxide capacitances


• Channel capacitances

– Gate-to-source: Cgs

– Gate-to-drain: Cgd

– Gate-to-bulk: Cgb

• Cutoff:

– No channel connecting source and drain

– Cgs = Cgd = 0

– Cgb = CoxWLeff

– Total channel capacitance CC = CoxWLeff

source drainCgb

CgdCgs

Oxide capacitances


• Linear mode

– Channel spans from source to drain

– Capacitance split equally between S and D

effoxGS WLCC2

1 effoxGD WLCC2

1

– Total channel capacitance CC = CoxWLeff

• Saturation mode– Channel is pinched off:

effoxGS WLCC3

20GDC

– Total channel capacitance CC = 2/3 CoxWLeff

0GBC

0GBC

Oxide capacitances


Cg,total

(no overlap)

Oxide capacitances


Junction Capacitance

Reverse-biased P-N junctions!Capacitance depends on reverse-bias voltage.



ad

adj NN

NN

VV

qAC

0

2

2

For a P-N junction:

ad

adSij NN

NN

V

qC

00 2

If V=0, Cap/area =

m

jj

VV

ACC

0

0

1

General form:

m = grading coefficient (0.5 for abrupt junctions)(0.3 for graded junctions)



• Junction with substrate

– Bottom area = W * LS (length of drain/source)

– Sidewall facing channel: area = W * Xj

– Total cap = Cj

• Junction with sidewalls

– “Channel-stop implant”

– Perimeter = 2LS + W

– Area = P * Xj

– Total cap = Cjsw

• Total junction cap C = Cj + Cjsw


SESSION 2: STATIC INVERTERS – Lecture 1

•Characteristics of Inverters•Resistive Load Inverters•VTC, Delay, Power Dissipation•Pseudo-NMOS Inverters•Depletion Load Inverters


MOS voltage levels

Case 1: NMOS discharges capacitor

• Initially: Vout = VDD (capacitor fully charged)

• VGS of NMOS = VDD

• What is final Vout?

VDDG D

SCload

Vout

time

Vout

VDD

• NMOS remains on since VGS > VT

• Final output voltage Vout = 0V


Case 2: NMOS charges capacitor

• Initially: Vout = 0

• Initial VGS of NMOS = VDD

• What is final Vout?

VDDG D

S

Cload

Vout

time

Vout

VDD

• NMOS remains on until VGS = VT

• Final output voltage Vout = VDD - VT

VDD

VDD-VT

MOS voltage levels


MOS voltage levels

Repeat for PMOS:

• Case 1: PMOS discharging capacitor

GndG S

DCload

Vout

• PMOS on until VGS = VT

• Vout = |VT|

• Case 2: PMOS charging capacitor

GndG S

D

Cload

Vout

• PMOS always on (VGS = -VDD)• Vout = VDD

VDD


MOS voltage levels

• NMOS summary

– Transfers logic ‘0’ completely (good for discharging a node)

– Does not transfer logic ‘1’ completely (bad for charging a node)

• PMOS summary

– Transfers logic ‘1’ completely

– Does not transfer logic ‘0’ completely

• Result:

– NMOS used for pulldown, PMOS for pullup


• Inverter is simplest digital logic gate

• Many different circuit styles possible

– Resistive-load

– Pseudo-NMOS

– CMOS

• Important characteristics

– Speed (delay through the gate)

– Power consumption

– Robustness (tolerance to noise)

– Area and process cost

Inverter Operation

‘0’ ‘1’‘1’ ‘0’

In Out0 11 0


InverterVin Vout

VDD

VDDVin

Vout

ideal

actual

Inverter model: VTC

Ideal digital inverter:

– When Vin=0, Vout=VDD

– When Vin=VDD, Vout=0

– Sharp transition region

Voltage transfer curve (VTC): plot of output voltage Vout vs. input voltage Vin


Actual inverter: VOH and VOL

• VOH and VOL represent the “high” and “low” output voltages of the inverter

• VOH = output voltage when Vin = ‘0’

• VOL = output voltage when Vin = ‘1’

• Ideally,VOH = VDD,VOL = 0

• Difference (VOH-VOL) is the voltage swing of the gate

– Full-swing logic swings from ground to VDDVDD

Vin

Vout

VOH

VOL

VDD


Inverter switching threshold:

– Point where voltage transfer curve intersects line Vout=Vin

– Represents the point at which the inverter switches state

– Normally, VTH VDD/2

VDD

Vin

Vout

VOH

VOL

Vout=Vin

VTH

Inverter threshold


Noise Margins

• VIL and VIH measure effect of input voltage on inverter output

• VIL = largest input voltage recognized as logic ‘0’

• VIH = smallest input voltage recognized as logic ‘1’

• Defined as point on VTC where slope = -1

VDD

Vin

Vout

VOH

VOL

VIL VIH

Slope = -1


Noise margin (cont)

VOH

VOL

VIH

VIL

“1”

“0”

NMH

NML

• Noise margin is a measure of the robustness of an inverter

– NML = VIL - VOL

– NMH = VOH - VIH

• Models a chain of inverters. Example:

– First inverter output is VOH

– Second inverter recognizes input > VIH as logic ‘1’

– Difference VOH-VIH is “safety zone” for noise

Ideally, noise margin should be as large as possible

interconnect


Noise margin (cont)

• Why are VIL, VIH defined as unity-gain point on VTC?

– Assume there is noise on input voltage Vin

noiseinout VVfV

noisein

outinout V

dV

dVVfV

– First-order approximation:

– If gain (dVout/dVin) > 1, noise will be amplified.

– If gain < 1, noise is filtered. Therefore VIL, VIH ensure that gain < 1


Inverter time response

• Propagation delay measured from 50% point of Vin to 50% point of Vout

• tphl = t1 - t0, tplh = t3 - t2, tp = ½(tphl+tplh)

VDD

Vss

VDD/2

VDD

Vss

VDD/2

Vin

Vout

t0 t1 t2 t3


Rise and fall time

• Fall time: measured from 90% point to 10% pointtF = t1 - t0

• Rise time: measured from 10% point to 90% point tR = t3 - t2

• Alternately, can define 20%-80% rise/fall time

V90%

V10%

t0 t1t2 t3

tF tR


Ring oscillator

• Ring oscillator circuit: standard method of comparing delay from one process to another

• Odd-number n of inverters connected in chain: oscillates with period T (usually n >> 5)

V1 V3 V2VOH

T

V50%

tPHL2 tPLH3 tPHL1 tPLH2 tPHL3 tPLH1

Cload Cload

V1 V2V3

nft

ntTfntT

ttttttT

pp

p

phlplhphlplhphlplh

2

1 ,

2

11 ,2

332211


Resistive-load inverter

• Requires only NMOS transistor and resistor

• When Vin = 0:

– NMOS is OFF (VGS = 0)

– No current through NMOS or resistor

– Vout VDD

• When Vin = VDD:

– NMOS is ON (VGS = VDD)

– NMOS on resistance << R

– Vout 0

VinVout

VDD

Gnd

R

G D

S

Remember: if body terminal not shown, it is connected to

gnd for NMOS, VDD for PMOS


Resistive-load inverter: VOH

• Vin = 0: NMOS transistor off, no current flows in circuit

• No voltage drop across R

• VOH = VDD

Vin=0

Vout

VDD

Gnd

R


• Vin = VDD: NMOS transistor on (linear mode)

Vin=VDDVout

VDD

Gnd

R Iload

ID

OLL

W

OLOLTDDLWOLDD

OLDDD

OLDS

DDINGS

DSDSTGSLW

D

VRk

VVVVkR

VVR

VVI

VV

VVV

VVVVkI

'

2

21'

2

21'

1

])[()(

)(

)(

• Solve quadratic equation for VOL, Approx value is

(because ID = Iload)

Resistive-load inverter: VOL


• Note that the value of VOL depends on the size of the NMOS device and on R

– Increase W to reduce VOL

– Increase R to reduce VOL

• Logic with this property is called “ratioed logic”

– Requires careful sizing for correct logic levels

• Ratioless logic: output levels do not depend on transistor sizes

Resistive-load inverter: VOL cont


Resistive-load inverter: VIL

• VIL = low unity gain point of VTC

– When Vin = VIL, NMOS in saturation:

2

21

2

21

TinnDDout

TinnoutDD

VVRkVV

VVkR

VV

– Take derivative of Vout with respect to Vin, set to -1

Tn

ILin

Tinnin

out

VRk

VV

VVRkdV

dV

1

1

increase VIL (and NML) by reducing kn


• VIH = high unity gain point of VTC

– When Vin = VIH, NMOS in linear region:

2

21

221

outnoutTinnoutDD

outoutTinnoutDD

RVkVVVRkVV

VVVVkR

VV

– Take derivative of Vout with respect to Vin, set to -1

outnoutnTinn

in

outoutnoutn

in

outTinn

in

out

RVkRVkVVRk

dV

dVRVkRVk

dV

dVVVRk

dV

dV

1

– Solve this equation simultaneously with (1) to get:

RkRk

VVV

nn

DDTIH

1

3

8

(1)

Resistive-load inverter: VIH


Resistive-load inverter: VTH

• Threshold of resistive-load inverter: VTH:

– Point on VTC where Vin = Vout:

– NMOS in saturation (ignoring l):

2'21

2'21

)(TTHL

WTHDD

THoutin

TinLW

D

VVkR

VV

VVV

VVkI

– Solve this quadratic for VTH


Resistive-load inverter: VTC

• Plot IDS of transistor and Iload of resistor vs. Vout

• Since currents must be equal, intersection points define VTC

Dra

in c

urre

nt I

DS

Vout = VDS

Vin=2V

VDD

Vin=1V

Vin=3V

Vin=4V

Vou

tVin1 2 3 40

VDD

Resistor load line (slope = 1/R)R

VDD

VOL


Resistive-load inverter: VTC

• Changing value of R affects VTC curve

• larger R → reduces VOL and improves NML but degrades NMH

Dra

in c

urre

nt I

DS

Vout = VDS

Vin=2V

VDD

Vin=1V

Vin=3V

Vin=4V

Vou

t

Vin1 2 3 40

VDD

R

VDD

R

largeR

small R

R

small R

largeR


Resistive-load inverter: power

• Static power consumption: depends on input voltage V in

– P0 = power when Vin = ‘0’

– P1 = power when Vin = ‘1’

• Average power depends on input probability

– a = probability that Vin = ‘1’

– (1-a) = probability that Vin = ‘0’

– Pavg = aP1 + (1-a)P0


Resistive-load inverter: power

• Find P0 and P1:

– Vin = 0: NMOS transistor off. No current flows from VDD to Gnd (except leakage). P0 = 0

– Vin = VDD: NMOS transistor on. Output voltage Vout = VOL.

R

VVVP

R

VVVP

IVPR

VVI

DDOLDDavg

DDOLDD

OLDDload

1

,Static power consumed

when Vin = VDD


Resistive-load inverter: delay

Output falling (Vin = 1):

• Discharge Cload through NMOS

• Need large ID, small IR

R IR

ID‘1’Cload

R IR

‘0’Cload

Output rising (Vin = 0):

• Charge Cload through resistor

• Need large IR


Resistive-load inverter: delay• Delay calculation: approximate method

– Use an average value of capacitor current IC

– Find current at start of transition, and current at end of transition, and use the average

01

0

1

0

,

VVI

Ct

dVI

Cdt

dVI

Cdt

dt

dVCI

avgd

V

V avg

t

avgavg

d

For rise delay: V0 = 0, V1 = VDD/2For fall delay: V0 = VDD, V1 = VDD/2


Resistive-load inverter: delay• Inverter rise delay tplh:

– Beginning of transition:

R

VVIVV OLDD

COLout

,

– End of transition:

R

VIVV DD

CDDout 2 ,2

1 – Average current:

R

VVI OLDD

avg 4

23

– Delay:

OLDDOLDD

loadplh

avg

loadd VV

VV

RCtVV

I

Ct

2

101 23

4,

Vin Vout


Resistive-load inverter: delay

• Inverter fall delay tphl:

– Beginning of transition: Vout=VDD (NMOS in saturation)

2

21

0 TDDnC VVkI – End of transition: Vout=½VCC (NMOS in linear)

– Average current:

1021

CCavg III

– Delay:

DDavg

loadphl

avg

loadd V

I

CtVV

I

Ct 2

101 ,

DDTDDnDDDDTDDnC VVVkVVVVkI 212

412

41

21

1


Resistive-load inverter: problems

• Static power consumption

• Tradeoff between delay and power:

– For fast operation, need small resistor

– For low power, need large resistor

• VOL is larger than 0V

– Reduced noise margin

• Large area

– Hard to make large resistance values on chip


Pseudo-NMOS inverter

• Replace resistor with “always-on” PMOS transistor

• Easier to implement in standard process than large resistance value

• PMOS load transistor:

– On when VGS < VT → VGS = -VDD: transistor always on

– Linear when VDS > VGS-VT → Vout-VDD > -VDD-VT → Vout > -VT

– Saturated when VDS < VGS-VT → Vout-VDD < -VDD-VT → Vout < -VT

Vin

VDD

Gnd

GS

D

VGS,P = -VDD

Remember: VT(PMOS) < 0

Vout


Pseudo-NMOS inverter: VOH

• VOH for pseudo-NMOS inverter:

– Vin = 0

– NMOS in cutoff: no drain current

• Result: VOH is VDD (as in resistive-load inverter case)

VDD

Gnd

Vout


Pseudo-NMOS inverter: VOL

• Find VOL of pseudo-NMOS inverter:

– Vin = VDD: NMOS on in linear mode

221

OLOLTnDDnDn VVVVkI

– PMOS on in saturation mode (assume)

2

21

TpDDpDp VVkI (neglecting )

– Setting Idn = Idp:

02

212

21 TpDDpOLTnDDnOLn VVkVVVkVk

• Key point: VOL is not zero

– Depends on thresholds, sizes of N and P transistors


Pseudo NMOS inverter: VTC

VDS = Vout

Dra

in c

urre

nt I

DS

Vin=2V

VDD

Vin=1V

Vin=3V

Vin=4V

-VDS = -(Vout - VDD)-D

rain

cur

rent

-I D

S

I/V curve for NMOS: I/V curve for PMOS:

VGS=-VDD

• Plot of -IDS vs -VDS since current is from source to drain• Only one curve since VGS fixed


Vout = VDS

Dra

in c

urr

ent

I DS

Vin=2V

VDD

Vin=1V

Vin=3V

Vin=4V

Vou

t

Vin1 2 3 40

VDD

• Similar VTC to resistive-load inverter

• Sharper transition region, smaller area

Pseudo NMOS inverter: VTC


Depletion-load inverter

• Depletion-load inverter: uses depletion NMOS transistor as load

– Depletion transistor has VT < 0

• Load is always on:

– VGS = 0 > VT

• Body effect of depletion transistor is significant (when Vout = VOH)

Vin

VDD

Gnd

GD

S

VGS = 0

Vout


Depletion-load inverter

• Static characteristics: VOH and VOL

– VOH: NMOS driver is off. As long as body effect does not cause VT(load) > 0, VOH = VDD

– VOL: driver in linear mode, depletion load in saturation

2212

21

OLOLTdDDndTlnl VVVVkVk

(solve for VOL) → VOL is non-zero

Need to calculate using body-effect coefficient


CMOS INVERTER – Lecture 1

•Regions of Operation•Noise margin•Inverter capacitances•Delay, Rise and Fall time


CMOS Inverter

• Complementary NMOS and PMOS devices

• In steady-state, only one device is on (no static power consumption)

• Vin=1: NMOS on, PMOS off

– Vout = VOL = 0

• Vin=0: PMOS on, NMOS off

– Vout = VOH = VDD

• Ideal VOL and VOH!

• Ratioless logic

Vin Vout

VDD

Gnd


CMOS Inverter: VTC

Vout = VDS

Dra

in c

urre

nt I

DS

Vin=2V

VDD

Vin=1V

Vin=3V

Vin=4V

Vou

t

Vin1 2 3 40

VDD

PMOS NMOS

• Output goes completely to VDD and Gnd• Sharp transition region


CMOS inverter operation

• NMOS transistor:

– Cutoff if Vin < VTN

– Linear if Vout < Vin – VTN

– Saturated if Vout > Vin – VTN

• PMOS transistor

– Cutoff if (Vin-VDD) < VTP → Vin < VDD+VTP

– Linear if (Vout-VDD)>Vin-VDD-VTP → Vout>Vin - VTP

– Sat. if (Vout-VDD)<Vin-VDD-VTP → Vout < Vin-VTP

Vin Vout

VDD


CMOS inverter VTC

P linearN cutoff

P linearN sat P sat

N sat

P satN linear

P cutoffN linear


CMOS inverter VTC

VDD

VDD

Vin

Vout

kp=kn

kp=5kn

kp=0.2kn

• Increase W of PMOS kp increases VTC moves to right

• Increase W of NMOS kn increases VTC moves to left

• For VTH = VDD/2 kn = kp

Wn 2Wp


Effects of VTH adjustment

• Result from changing kn/kp ratio:

– Inverter threshold VTH VDD/2

– Rise and fall delays unequal

– Noise margins not equal

• Reasons for changing inverter threshold

– Want a faster delay for one type of transition (rise/fall)

– Remove noise from input signal: increase one noise margin at expense of the other


CMOS inverter: VIL

• KCL:

• Differentiate and set dVout/dVin to –1

• Solve simultaneously with KCL to find VIL

2,,,0,

2,0, 2

22 pDSpDSpTpGSp

nTnGSn VVVV

kVV

k

2,0

2,0 2

22 DDoutDDoutpTDDinp

nTinn VVVVVVV

kVV

k

in

outDDoutDDout

in

outpTDDinpnTinn dV

dVVVVV

dV

dVVVVkVVk ,0,0

DDpTILoutpnTILn VVVVkVVk ,0,0 2

R

nTRDDpToutIL k

VkVVVV

1

2 ,0,0

p

nR k

kk


CMOS inverter: VIH

• KCL:

• Differentiate and set dVout/dVin to –1

• Solve simultaneously with KCL to find VIH

2,0,

2,,,0, 2

22 pTpGS

pnDSnDSnTnGS

n VVk

VVVVk

2,0

2,0 2

22 pTDDin

poutoutnTin

n VVVk

VVVVk

pTDDinpin

outoutout

in

outnTinn VVVk

dV

dVVV

dV

dVVVk ,0,0

pTDDIHppTIHoutn VVVkVVVk ,0,02

R

nToutRpTDDIH k

VVkVVV

1

2 ,0,0p

nR k

kk


CMOS inverter: VTH

• KCL:

• Solve for VTH = Vin = Vout

2,0,

2,0, 22 pTpGS

pnTnGS

n VVk

VVk

2,0

2,0 22 pTDDin

pnTin

n VVVk

VVk

R

pTDDR

nT

TH

k

VVk

V

V1

1

1,0,0

p

nR k

kk


CMOS inverter: Ideal VTH

• Ideally, VTH = VDD/2

• Assuming VT0,n = VT0,p,

R

pTDDR

nT

TH

k

VVk

V

V1

1

1,0,0

p

nR k

kk

2

,0

,0, 2

2

nTDD

pTDDidealR VV

VVk

1, idealRk

5.2

p

n

n

p

LW

LW


• Assuming VT0,n= -VT0,p, and kR = 1,

0238

1TDDIL VVV

0258

1TDDIH VVV

DDIHIL VVV

ILOLILL VVVNM

ILIHDDIHOHH VVVVVNM

CMOS inverter: VIL and VIH for Ideal VTH


Vin

VDD

Gnd

Cgd,p

Cgs,p

Cdb,p

Csb,p

Cgd,n

Cgs,n Csb,n

Cdb,n Cint Cg

f

Cap on node f:

• Junction cap Cdb,p and Cdb,n• Gate capacitance Cgd,p and Cgd,n• Interconnect cap• Receiver gate cap

CMOS inverter: capacitances


• Junction capacitances Cdb,p and Cdb,n:

– Equation for junction cap

– Non-linear, depends on voltage across junction

– Use Keq factor to get equivalent capacitance for a voltage transition

m

da

dajm

jj NN

NNqC

V

ACVC

0

0

0

0 1

2,

1

jsweqswjeqdb CPKCAKC



• Gate capacitances CGD,p and CGD,n:

– In steady state, what regions are transistors in?

– One is in cutoff: CGD = CGS = 0

– One is in saturation: CGD = 0

– Therefore, gate-to-drain capacitance is only due to overlap capacitance:

Doxngdpgd WLCCC ,,

However, also need to consider Miller effect ...



• When input rises by V, output falls by V

– Effective voltage change across Cgd1 is 2V

– Effective capacitance to ground is twice Cgd1

• Including Miller effect:

Vin

Vout

Cgd1

Vin

Vout

2Cgd1

Doxngdpgd WLCCC 2,,



• Interconnect capacitance

– Due to capacitance of metal and poly lines used to connect transistors

– Complex; includes parallel-plate and fringing-field components

– For wide wires:

WLt

Cox

oxint tox = thickness of field oxide

Sample capacitances for 1m process:poly: 0.058 fF/m2 M1: 0.031 fF/m2

M2: 0.015 fF/m2 M3: 0.010 fF/m2



• Receiver gate capacitance

– Includes all capacitances of gate(s) connected to output node

– Unknown region of operation for receiver transistor: total gate cap varies from (2/3)WLCox to WLCox

– Ignore Miller effect since operation unknown

– Assume worst-case value, include overlap

oxDoxeffg CWLCWLC 2

Review: CMOS inverter capacitances


First-order inverter delay

• Assume: Current charging or discharging capacitance Cload is nearly constant Iavg

Vin VoutCload

SSDDavg

loadPLH

DDDDavg

loadPHL

VVI

Ct

VVI

Ct

21

21


Inverter delay, falling

• Assume PMOS fully off (ID,p = 0)

CloadVinID.n

dt

dVCI

dt

dVCI

outloadnD

,Need to determine ID,n



• From t0 to t1: NMOS in saturation

• From t1 to t2: NMOS in linear region

• Find ID in each region

VDD

VDD - Vtn

VDD/2

t0 t1 t2

NMOS in saturation

NMOS in linear region


CMOS inverter delay

• Another approximate method:

– Again assume constant Iavg

– Iavg = current I1 at start of transition

– good approximation esp. for deep submicron

2

2

TPDDp

DDloadPLH

TnDDn

DDloadPHL

VVk

VCt

VVk

VCt

V1=VDD

V2=½VDD

t1 t2

I1

Iavg = I1


Inverter delay, falling t1-t0

• Assumption: Input fast enough to go through transition before output voltage changes

• Vout drops from VDD to VDD-VTN (NMOS saturated)

2,0

,001

2,0

2,0

2,0

)(

2

)(

2

2/)(2/)(

,01

0

nTOHn

nTL

VV

V

outnTOHn

L

t

t

nTOHnnTinnDS

VVk

VCtt

dVVVk

Cdt

VVkVVkI

nTOH

OH


Inverter delay, falling t2-t1• Vout drops from (VOH-VT0,n) to VDD/2

• NMOS in linear region

2/)(

2/)()(2ln

)(

)(

)(

,0

,012

2/)(

221

,012

221

,0

,0

OLOH

OLOHnTOH

nTOHn

L

VV

VV outoutnTOHn

outL

outoutnTOHnDS

VV

VVVV

VVk

Ctt

VVVVk

dVCtt

VVVVkI

OLOH

nTOH



• Total fall delay = (t1-t0) + (t2-t1)

1)(4

ln2

)(,0

,0

,0

,0 OLOH

nTOH

nTOH

nT

nTOHn

LPHL VV

VV

VV

V

VVk

Ct


Inverter delay, rising

• Similar calculation as for falling delay

• Separate into regions where PMOS is in linear, saturation

1

)(4ln

2

)(,0

,0

,0

,0 OLOH

pTOLOH

pTOLOH

pT

pTOLOHp

LPLH VV

VVV

VVV

V

VVVk

Ct


Inverter rise, fall time

• Exact method: separate into regions

– t1

– Vout drops from 0.9VDD to VDD-VT (NMOS in saturation)

– Vout rises from 0.1VDD to VT (PMOS in saturation)

– t2

– Vout drops from VDD-VT to 0.1VDD (NMOS in linear region)

– Vout rises from VT to 0.9 VDD (PMOS in linear region)

– tf,r = t1 + t2


Inverter rise, fall time

• Average current method:

– Find current at start and end of transition

– Find average and use

avgrisefall I

VC,


How to improve delay?

• Minimize load capacitances

– Small interconnect capacitance

– Small Cg of next stage

• Raise supply voltage

• Increase transistor gain factor

– increase transistor drive current for charging/discharging output capacitance


CMOS inverter delay

• Review of exact method

– Break transition into regions of operation

– Example: tphl (output falling):

VDDVDD - Vtn

VDD/2

t0 t1 t2

NMOS in saturation

NMOS in linear region


CMOS inverter delay

• What if input has finite rise/fall time?

– Both transistors are ON for some amount of time

– Capacitor charge/discharge current is reduced

22

2)()(

r

phlphl

tsteptactualt

2

2

2)()(

f

plhplh

tsteptactualt

Empirical equations:

trise(ns)

t pHL(n

s)

CADENCE CONFIDENTIAL127CADENCE DESIGN SYSTEMS, INC.

SESSION 3: CMOS LOGIC STRUCTURES Lecture 1

•MOS a Switch•Static CMOS•NAND,NOR•Transistor sizing•Complex Gate•Design techniques


Switch-level model

• Model transistors as switches and resistances

• Resistance Ron = average resistance for a transition

• For NMOS tphl:

Rn

RP

A

A

DDoutDDout VVD

DS

VVD

DSon

DDoutNMOSDDoutNMOSon

I

V

I

VR

VVRVVRR

21

21

21

21 )()( CL


Switch-level model

Delay estimation using switch-level model (for general RC circuit):

Rn CL

0

101

01

ln)ln()ln(

1

0

V

VRCVVRCt

dVV

RCttt

dVV

RCdt

R

VI

dVI

Cdt

dt

dVCI

p

V

V

p


Switch-level model

• For fall delay tphl, V0=VDD, V1=VDD/2

Lpplh

Lnphl

p

DD

DDp

CRt

CRt

RCt

V

VRC

V

VRCt

69.0

69.0

)5.0ln(

lnln 21

0

1

Standard RC-delay equations


Static CMOS

• Complementary pullup network (PUN) and pulldown network (PDN)

• Only one network is on at a time

• PUN: PMOS devices

– Why?

• PDN: NMOS devices

– Why?

• PUN and PDN are dual networks

• Output is always connected to VDD or Gnd

VDD

VSS

PUN

PDN

In1

In2

In3

F = G

In1

In2

In3

PUN and PDN are Dual Networks

PMOS Only

NMOS Only


Dual Networks

B

A F

• Dual networks:

• parallel connection in PDN = series connection in PUN, vice-versa

• If CMOS gate implements logic function F:

– PUN implements function F

– PDN implements function G = F’

Example: NAND gate

parallel

series


NAND gate

• NAND function: F = A•B

• PUN function: F = A • B = A + B

– “Or” function (+) → parallel connection

– Inverted inputs A, B → PMOS transistors

• PDN function: G = F = A • B

– “And” function (•) → series connection

– Non-inverted inputs → NMOS transistors


NOR gate

• NOR gate operation: F = A+B

• PDN: G = F = A+B

• PUN: F = A+B = A•BA

B

A B


CMOS gate design

• Designing a CMOS gate:

– Find pulldown NMOS network from logic function or by inspection

– Find pullup PMOS network

– By inspection

– Using logic function

– Using dual network approach

– Size transistors using equivalent inverter

– Find worst-case pullup and pulldown paths

– Size to meet rise/fall or threshold requirements


Graph-based dual network

• Draw network for PUN or PDN

– Circuit nodes are vertexes

– Transistors are edges

A B

F

gnd

A B

F


• To derive dual network:

– Create new node in each enclosed region of graph

– Draw new edge intersecting each original edge

– Edge is controlled by inverted input

A B

A B A

BF

Graph-based dual network


Analysis of CMOS gates

• Represent “on” transistors as resistors

1 1

1RW

W

W

R

R

• Transistors in series → resistances in series• Effective resistance = 2R• Effective width = ½ W


• Represent “on” transistors as resistors

• Transistors in parallel → resistances in parallel• Effective resistance = ½ R• Effective width = 2W

0 0

0

RWW W R R

Analysis of CMOS gates


Equivalent Inverter

• CMOS gates: many paths to VDD and Gnd

– Multiple values for VTH, VIL, VOL, etc

– Different delays for each input combination

• Equivalent inverter

– Represent each gate as an inverter with appropriate device width

– Include only transistors which are on or switching

– Calculate VTH, delays, etc using inverter equations


• VTH of the equivalent inverter is used (assumes all inputs are tied together)

– For specific input patterns, VTH will be different

• For VIL and VIH, only the worst case is interesting since circuits must be designed for worst-case noise margin

• For delays, both the maximum and minimum must be accounted for in race analysis

Static CMOS Logic Characteristics


Equivalent Inverter: VTH

• Example: NAND gate threshold VTH

Three possibilities:

– A & B switch together

– A switches alone

– B switches alone

• What is equivalent inverter for each case?


Equivalent inverter: delay

• Represent complex gate as inverter for delay estimation

• Use worse-case delays

• Example: NAND gate

– Worse-case (slowest) pull-up: only 1 PMOS “on”

– Pull-down: both NMOS “on”

WN

WN

WP WP WP

½ WN


Example: NOR gate

• Find threshold voltage VTH when both inputs switch simultaneously

• Two methods:

– Transistor equations

– Equivalent inverter

A

B

A B

F

WN

WP

WP

WN


Example: complex gateDesign CMOS gate for this truth table:

A B C F

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0

F = A•(B+C)


Example: complex gate

Completed gate:

CB

A

C

B

A

F

WP

WP

WP

WN

WN WN

• What is worse-case pull up delay?

• What is worse-case pull down delay?

• Effective inverter for delay calculation:

½ WP

½ WN


Transistor Sizing

• Sizing for switching threshold

– All inputs switch together

• Sizing for delay

– Find worst-case input combination

• Find equivalent inverter, use inverter analysis to set device sizes


VDD

A B

A

B

C

D

C D

tp a1FI a2FI2 a3FO+ +=

Fan-Out: Number of Gates Connected2 Gate Capacitances per Fan-Out

FanIn: Quadratic Term due to:

1. Resistance Increasing2. Capacitance Increasing(tpHL)

Influence of Fan-In and Fan-Out


1 3 5 7 9fan-in

0.0

1.0

2.0

3.0

4.0t p

(ns

ec)

tpHL

tp

tpLHlinear

quadratic

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

tp as a function of Fan-In


• Transistor Sizing: As long as Fan-out Capacitance dominates

• Progressive Sizing:

CL

In1

InN

In3

In2

Out

C1

C2

C3

M1 > M2 > M3 > MN

M1

M2

M3

MN

Distributed RC-line

Can Reduce Delay with more than 30%!

Complex Gate - Design Techniques


In1

In3

In2

C1

C2

CL

M1

M2

M3

In3

In1

In2

C3

C2

CL

M3

M2

M1

(a) (b)

• Transistor Ordering

critical pathcritical path

Complex Gate - Design Techniques(2)


• Improved Logic Design



• Buffering: Isolate Fan-in from Fan-out

CLCL



CMOS design guidelines

• Transistor sizing

– Size for worst-case delay, threshold, etc

– Tapering: transistors near power supply are larger than transistors near output

• Transistor ordering

– Critical signal is latest-arriving signal to gate

– Put critical signals closest to output

– Stack nodes are discharged by early signals

– Reduced body effect on top transistor


CMOS design guidelines

• Limit fan-in of gate

– Fan-in: number of gate inputs

– Affects size of transistor stacks

– Normally fan-in limit is 3-4

• Convert large multi-input gates into smaller chain of gates

• Limit fanout of gate

– fanout: number of gates connected to output

– Capacitive load: affects gate delay

• NANDs are better than NORs


• 5 minute break


PASS LOGIC and D Latch – Lecture 1

Transmission gate

MUX

Tristate Inverter

D Latch, MS register


CMOS disadvantages

• For N-input CMOS gate, 2N transistors required

– Each input connects to an NMOS and PMOS transistor

– Large input capacitance: limits fanout

• Large fan-in gates: always have long transistor stack in PUN or PDN

– Limits pullup or pulldown delay

– Requires very large transistors

• Single-stage gates are inverting


Pseudo-NMOS logic

• Pseudo-NMOS: replace PMOS PUN with single “always-on” PMOS device

• Same problems as pseudo-NMOS inverter:

– VOL larger than 0

– static power when PDN is on

• Advantages

– Replace large PMOS stacks with single device

– Reduces overall gate size, input capacitance

– Especially useful for wide-NOR structures


Transmission Gate Logic

• NMOS and PMOS connected in parallel

• Allows full rail transition – ratioless logic

• Equivalent resistance relatively constant during transition

• Complementary signals required for gates

• Some gates can be efficiently implemented using transmission gate logic

= =


Equivalent Resistance

• For a rising transition at the output (step input)

– NMOS sat, PMOS sat until output reaches |VTP|

– NMOS sat, PMOS lin until output reaches VDD-VTN

– NMOS off, PMOS lin for the final VDD – VTN to VDD voltage swing

Vin Vout

VDD

0V


• NMOS sat:

• PMOS sat:

2

21,

tnoutDDn

outDDneq

VVVk

VVR

2

21,

tpDDp

outDDpeq

VVk

VVR

Equivalent Resistance – Region 1


• NMOS sat:

• PMOS lin:

outDDTPDDp

outDDoutDDTPDDp

outDDpeq

VVVVk

VVVVVVk

VVR

2

2

2

22,

2

21,

tnoutDDn

outDDneq

VVVk

VVR



• NMOS off:

• PMOS lin:

neqR ,

outDDTPDDppeq VVVVk

R

2

2,



Equivalent resistance

• Equivalent resistance Req is parallel combinaton of Req,n and Req,p

• Req is relatively constant

VDDVTp Vcc-VTn

Req,p

Req,n

Req

R

Vout


Resistance Approximations

• To estimate equivalent resistance:

– Assume both transistors in linear region

– Ignore body effect

– Assume voltage difference is small

tnDDnneq VVk

R

1

, tpDDp

peqVVk

R

1

,

tpDDptnDDn

eqVVkVVk

R

1


Transmission Gate Logic

• Useful for multiplexers (select between multiple inputs) and XORs

• Transmission gate implements logic function F = A if S

– If S is 0, output is floating, which should be avoided

– Always make sure one path is conducting from input to output

• Two transmission gates can implement

AS + BS’

– TGate 1: A if S

– TGate 2: B if S’


AM2

M1

B

S

S

S F

VDD

GND

VDD

In1

In2

S S

S S

Pass-Transistor Based Multiplexer


A

B

F

B

A

B

B

M1

M2

M3/M4

Transmission Gate XOR


• Can implement Boolean formulas as networks of switches.

• Can build switches from MOS transistors—transmission gates.

• Transmission gates do not amplify but have smaller layouts.

Switch logic


complementary

n-type

Types of switches


n-type switch has source-drain voltage drop when conducting:

– conducts logic 0 perfectly;

– introduces threshold drop into logic 1.

VDD

VDD

VDD - Vt

Behavior of n-type switch


n-type switch driving static logic

Switch under-drives static gate, but gate restores logic levels.

VDD

VDD

VDD - Vt


n-type switch driving switch logic

Voltage drop causes next stage to be turned on weakly.

VDD VDD - Vt

VDD

VDD -2 Vt


Behavior of complementary switch

• Complementary switch products full-supply voltages for both logic 0 and logic 1:

– n-type transistor conducts logic 0;

– p-type transistor conducts logic 1.


NMOS in SERIES PARALLEL

• Switch controlled by the gate input

• NMOS switch closes when the gate input is High

• Remember - NMOS transistors pass a strong 0 but a weak 1


PMOS in SERIES PARALLEL

• Switch controlled by the gate input

• PMOS switch closes when the gate input is low

• Remember - PMOS transistors pass a strong 1 but a weak 0


Pass Transistor Logic

• Primary inputs drive source/drain terminals as well as gate terminals

• N transistors instead of 2N

• No static power consumption

• Ratioless

• Bidirectional (versus undirectional)


NMOS Only Switch

• VC does not pull up to VDD, but VDD – VTn

• Threshold voltage drop causes static power consumption (M2 may be weakly conducting forming a path from VDD to GND)


NMOS Only Switch

• VC does not pull up to VDD, but VDD – VTn

• Threshold voltage drop causes static power consumption (M2 may be weakly conducting forming a path from VDD to GND)

• Body effect - VSB at x - when pulling high (B is tied to GND and S charged up close to VDD). So the voltage drop is even worse


Cascaded Pass Transistors

• Pass transistor gates should not be cascaded as on the left


Tristate Inverter

– Tri-state inverters : 0 1 Z

A F

en

en

tri-state inverter

When en=0, F is “floating”


Memory elements

• Stores a value as controlled by clock.

• May have load signal, etc.

• In CMOS, memory is created by:

– capacitance (dynamic);

– feedback (static).


Variations in memory elements

• Form of required clock signal.

• How behavior of data input around clock affects the stored value.

• When the stored value is presented to the output.

• Whether there is ever a combinational path from input to output.


Memory element terminology

• Latch: transparent when internal memory is being set from input.

• Flip-flop: not transparent—reading input and changing output are separate events.


Clock terminology

• Clock edge: rising or falling transition.

• Duty cycle: fraction of clock period for which clock is active (e.g., for active-low clock, fraction of time clock is 0).


Memory element parameters

• Setup time: time before clock during which data input must be stable.

• Hold time: time after clock event for which data input must remain stable.

clock

data


Dynamic latch

Stores charge on inverter gate capacitance:


Latch characteristics

• Uses complementary transmission gate to ensure that storage node is always strongly driven.

• Latch is transparent when transmission gate is closed.

• Storage capacitance comes primarily from inverter gate capacitance.


Latch operation

• = 0: transmission gate is off, inverter output is determined by storage node.

• = 1: transmission gate is on, inverter output follows D input.

• Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid.


Stored charge leakage

• Stored charge leaks away due to reverse-bias leakage current.

• Stored value is good for about 1 ms.

• Value must be rewritten to be valid.

• If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid.


Non-dynamic latches

• Must use feedback to restore value.

• Some latches are static on one phase (pseudo-static)—load on one phase, activate feedback on other phase.


Re-circulating latch

Static on one phase:

LD’

LD

2’

2


Clocked inverter

symbol

circuit’


Clocked inverter operation

= 0: both clocked transistors are off, output is floating.

= 1: both clocked inverters are on, acts as an inverter to drive output.


Clocked inverter latch


Clocked inverter latch operation

• Not transparent—use multiple storage elements to isolate output from input.

• Major varieties:

• master-slave;

• edge-triggered.

= 0: i1 is off, i2-i3 form feedback circuit.

= 1: i2 is off, breaking feedback; i1 is on, driving i3 and output.

• Latch is transparent when = 1.


Flip-flops

• Not transparent—use multiple storage elements to isolate output from input.

• Major varieties:

– master-slave;

– edge-triggered.


Master-slave flip-flop

D Q

master slave


Master-slave operation

• ø = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change.

• ø = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value.


Signal skew

• Machine data signals must obey setup and hold times—avoid signal skew.

• If delays along different paths vary significantly, outputs may not be valid even though inputs are.


Signal skew example

• Invalid latch input: signals are not aligned:

D Qa

b

x

time

a

b

x

stable

5 10

stable

stable

circuit

timing diagram


Clock skew

Clock must arrive at all memory elements in time to load data.


SESSION 4: POWER DISSIPATION– Lecture

•Static and Dynamic Power Dissipation •Short Circuit Dissipation•Impact of Rise/Fall Times on Short-Circuit Currents. • Buffer Design Issues


CMOS inverter power

• Power has three components

– Static power: when input isn’t switching

– Dynamic capacitive power: due to charging and discharging of load capacitance

– Dynamic short-circuit power: direct current from VDD to Gnd when both transistors are on


static power

• Static power consumption:

– Static current: in CMOS there is no static current as long as Vin < VTN or Vin > VDD+VTP

– Leakage current: determined by “off” transistor

– Influenced by transistor width, supply voltage, transistor threshold voltages

VDD

Vss

Ileak,n

VDDVDD

Ileak,p

Vss

VDD


Dynamic capacitive power

Energy for one complete cycle

(charge and discharge)fVCP

VCE

dVVC

dtdt

dVCV

dtVtiE

DDLdyn

DDLvdd

V

outDDL

outLDD

DDvccvdd

DD

2

2

0

0

0

)(


Dynamic capacitive power

• Formula for dynamic power:

• Observations

– Does not (directly) depend on device sizes

– Does not depend on switching delay

– Applies to general CMOS gate in which:

– Switched capacitances are lumped into CL

– Output swings from Gnd to VDD

– Input signal approximated as step function

– Gate switches with frequency f

fVCP DDLdyn2


Dynamic short-circuit power

• Short-circuit current flows from VDD to Gnd when both transistors are on

• Plot on VTC curve:

VDD

VDDVin

Vout ID

Imax

Imax: depends on saturation current of devices


Dynamic short-circuit power

• Approximate short-circuit current as a triangular wave

• Energy per cycle:

fIVtt

P

IVtttI

VtI

VE

DDfr

sc

DDfrf

DDr

DDsc

max

maxmaxmax

2

222

Imax


Inverter power consumption

• Total power consumption

leakDDfr

DDDDLtot

statscdyntot

IVftt

IVfVCP

PPPP

2max2

• Energy-delay product:

– Multiply energy x delay: EDP = E*D

– Often the goal of a design is to minimize EDP


Power reduction

• Reducing dynamic capacitive power:

– Lower the voltage!

– Quadratic effect on dynamic power

– Reduce capacitance

– Short interconnect lengths

– Drive small gate load (small gates, small fan-out)

– Reduce frequency

– Lower clock frequency -> use more parallelism

– Lower signal activity


Power reduction

• Reducing short-circuit current:

– Fast rise/fall times on input signal

– Reduce input capacitance

– Insert small buffers to “clean up” slow input signals before sending to large gate

• Reducing leakage current:

– Small transistors (leakage proportional to width)

– Lower voltage


Inverter design

• Consider chain of minimum-sized inverters:

Cload Cload Cload Cload

Wp, Wn Wp, Wn Wp, Wn Wp, Wn

• Now double the size of each inverter:

2Cload 2Cload 2Cload 2Cload

2Wp, 2Wn 2Wp, 2Wn 2Wp, 2Wn 2Wp, 2Wn

Delay of single inverter is tp0

What is new inverter delay?


Inverter chain delay

• Neglecting interconnect capacitance:

– Both delay and load capacitance scale linearly with inverter size

– Increasing inverter size also increases capacitance -> delay remains constant

• Including interconnect capacitance– Interconnect cap remains

constant– Increasing inverter size

reduces delay

size

dela

y


Inverter as a buffer

• Consider minimum-size inverter driving load Cload:

Cload

Wp,Wn

Cg

• Delay of inverter:

– Gate cap of min-size inverter = Cg

– Delay of min-size inverter driving another min-size inverter = tp0

0 , ppgload xttxCC


Inverter as buffer• Example:

– Assume tp0 = 1ns

Wp,Wn20Wp,20Wn

Inverter delay = 20ns!• Reduce delay by inserting extra buffer

– What is the optimum ratio u?

Cload

Wp,Wn

Cg

uWp,uWn

Wp,WnWp,Wn

Inverter delay = 1ns


Inverter as buffer

• Total delay = delay of first inverter + delay of buffer:

– First inverter has u-times larger load:delay = utp0

– Second inverter has x/u-times larger load:delay = (x/u)tp0

– Total delay:

000 pppp tu

xut

u

xutt

Cload

Wp,Wn

Cg

uWp,uWn


Inverter as buffer

• Find factor u which minimizes tp: take derivative of tp wrt u and set to 0

xtt

xuu

x

tu

xt

u

t

tu

xutt

poptp

opt

ppp

ppp

0,

2

020

00

2

,1

0


Inverter as buffer

• When should a single-inverter buffer be used?

– Only if combined delay of both inverters is faster than unbuffered case

4

2

2 00

x

xx

xtxt pp

xtt pp 02

0pp xtt unbuffered:

buffered:

single-inverter buffer is faster if load is > 4X larger


Superbuffer design• Large fixed load capacitance driven by chain of “n”

inverters

• Stage ratio = u

– First inverter is minimum size

– Each inverter is “u” times bigger than previous one

• What is optimum “u” and “n” ?

Cload

1 u u2 u3

Cg


Superbuffer design

• tp0 = average delay of one inverter driving another one of same size

• Delay of each stage = delay of inverter driving another inverter “u” times bigger = utp0

• Total delay = n u tp0

• Ratio of load cap to gate cap:

)ln(

)ln(),ln()ln(

,

u

xnunx

uxC

Cx

CuC

n

g

load

gn

load

number of buffers required


Superbuffer design

• Total delay:

0)ln()ln( pt

u

uxdelayTotal

• Optimum stage delay u = e ~ 2.7

• Including interconnect, u ranges from 3-5


Buffer example

• A minimum-sized inverter (size 1) needs to drive a fan-out of 4 size 20 inverters

• Find the delay for the (a) non-buffered, (b) single buffer, and (c) super-buffer case

Cg

1

20

20

20

20

tp0 = 0.5 ns


SESSION 5: DYNAMIC LOGIC Lecture 1

•Pre charge evaluate•Charge sharing, leakage•Domino Logic•C2MOS logic


Mp

Me

VDD

PDN

In1In2

In3

OutMe

Mp

VDD

PUN

In1In2

In3

Out

CL

CL

p networkn network

2 phase operation:• Evaluation

• Precharge

Dynamic Logic


Mp

Me

VDD

Out

A

B

C

• N + 1 Transistors

• Ratioless

• No Static Power Consumption

• Noise Margins small (NML)

• Requires Clock

Example


0.00e+00 2.00e-09 4.00e-09 6.00e-09t (nsec)

0.0

2.0

4.0

6.0V

out (

Vol

t)

Vout

PRECHARGEEVALUATION

Transient Response


In1

In2

In3

In4

Out

VDD

GND

Dynamic 4 Input NAND Gate


Charge Sharing

• Output is floating after clk = ‘1’ if inputs are ‘0’

• If upper transistors in a stack switch, the intermediate and output node voltages will be equalized, possibly leading to a drop in the output voltage = noise

• Final output

V=(C1V1+C2V2)/(C1+C2)

may be higher if NMOS turns off

C1 C2


• Output is floating after clk = ‘1’ if inputs are ‘0’

• Since the current is not 0 when transistors are in cutoff, current can leak away from the output when all inputs are ‘0’

• Changes in input signals couple to the output and intermediate nodes, also resulting in voltage drops

Charge Leakage & Cap. Coupling


Noise Solutions

• Charge sharing:

– Ensure the output capacitance is large enough such that the voltage drop is minimal

– Precharge internal stack nodes to VCC

– Pre-discharging internal stack nodes can increase performance, but worsens noise

• Charge leakage/sharing and cap. coupling:

– Add a keeper PMOS (weak P pullup) – increased evaluation contention


Mp

Me

VDD

Out

ACL

(1)

(2)

t

t

Vout

(b) Effect on waveforms(a) Leakage sources

precharge evaluate

Minimum Clock Frequency: > 1 MHz

Reliability Problems -Charge Leakage


Mp

Me

VDD

Out

A

B = 0

CL

Ca

Cb

Ma

Mb

X

CLVDD CLVout t Ca VDD VTn VX – +=

or

Vout Vout t VDD–CaCL-------- VDD VTn VX

– –= =

Vout VDD

CaCa CL+----------------------

–=

case 1) if Vout < VTn

case 2) if Vout > VTn

Charge Sharing (redistribution)


Mp

Me

VDD

Out

A

B

Ma

Mb

Mbl Mp

Me

VDD

Out

A

B

Ma

Mb

Mbl

(b) Precharge of internal nodes

(a) Static bleeder

Charge Redistribution - Solutions


Mp

Me

VDD

Out

A

B

CL

Ca

Cb

Ma

Mb

X

5V

overshoot

out

could potentially forwardbias the diode

Clock Feedthrough


Mp

Me

VDD

Mp

Me

VDD

In

Out1 Out2

Out2

Out1

In

V

t

V

VTn

(a) (b)

Only 0 1 Transitions allowed at inputs!

Cascading Dynamic Gates


Domino Logic

• Solves problem of cascading dynamic gates, but is non-inverting

– Add an inverter between dynamic gates

– Inverter drives the gate’s fanout – increased performance

– Sometimes the inverter is replaced with a more complex static CMOS gate

– Static CMOS gate improves dynamic noise margins

• Solve non-inverting problem by implementing both F and F separately

– Area/power doubles


Domino Logic


D

D

In

(a) Schematic diagram

(b) Non-overlapping clocks

Pseudo-static Latch

Charge-Based Storage


D

InA

B

Overlapping Clocks Can Cause

• Race Conditions

• Undefined Signals

Master-Slave Flip-Flop


D

In

t12

2 phase non-overlapping clocks


DIn

Input Sampled

Output Enable

2-phase dynamic flip-flop


DIn

VDDVDD

M1

M3

M4

M2 M6

M8

M7

M5

section section

CL1 CL2

X

C2MOS LATCH

Flip-flop insensitive to clock overlap


DIn

1

M1

M3

M2 M6

M7

M5

1

DIn

VDDVDD

M1

M4

M2 M6

M8

M5

0 0

VDDVDD

(a) (1-1) overlap (b) (0-0) overlap

X X

C2MOS avoids Race Conditions


InF Out

VDD

VDD

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?

Pipelined Logic using C2MOS


1

VDD

VDDVDD

Number of a static inversions should be even

Example


VDDVDD

PDN

In1In2In3

VDD

PUN

Out

VDD

Out

VDD

PDN

In1In2In3

VDD

In4

In4

VDD

(a)-module

(b)-module

Combinational logic Latch

NORA CMOS Modules


VDD

Out

VDD

Doubled n-C2MOS latch

In

VDD

Out

VDD

Doubled n-C2MOS latch

In

Doubled C2MOS Latches


VDD

Out

VDD

VDD

VDD

InStatic

Logic

PUN

PDN

Including logic into

the latch

Inserting logic between

latches

TSPC - True Single Phase Clock Logic


VDD

D

VDD

VDD

D

VDD

VDD

D

VDD

D

VDD

VDD

D

VDD

D

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY

Master-Slave Flip-flops


Cascading Domino

• For gates with all inputs coming from other domino gates, the bottom NMOS transistor can be eliminated

– Why? All inputs will be ‘0’ during precharge and can only transition from ‘0’ to ‘1’ during evaluate

– Results in increased performance due to decreased stack height

– Precharge now depends on input precharge time


Dynamic Logic Power

• Power depends upon switching activity

– Switching activity depends upon the probability of a ‘1’ input

– Effective capacitance is doubled when the gate evaluates because the gate must later precharge

– Frequency must be multiplied by the probability that an evaluation will occur

• Power is usually higher except for very high activity gates

fVCVCT

P DDloadDDloadavg221


SESSION 6: SCALING of MOS Lecture 1

•Velocity saturation•Mobility degradation•Threshold voltage variation•DIBL•Channel length modulation•Scaling•Constant field, constant voltage, Effects of scaling


Secondary effects

• Short-channel effects:

– Short channel device has channel length comparable to depth of drain and source junctions and depletion width

– Causes threshold voltage and I/V curve variations

• Narrow-channel effects:

– Narrow channel device has small channel width

• Sub-threshold conduction (leakage current)


Short-channel effects

• Short-channel device: channel length is comparable to depth of drain and source junctions and depletion width

– In general, visible when L ~ 1um and below

• Short-channel effects:

– Carrier velocity saturation

– Mobility degradation

– Threshold voltage variation


Carrier velocity saturation

• Electric field Ey exists along channel

– As channel length is reduced, electric field increases (if voltage is constant)

• Electron drift velocity vd is proportional to electric field

– only for small field values

– for large electric field, velocity saturates

source drain

Vds0 Vgs

N+N+

P

L


Carrier velocity saturation

• Effect of velocity saturation:

– Current saturates before “saturation region”

– VDSAT = voltage at which saturation occurs

– Drain current is reduced:

DSAToxdD VCsatvWsatI )()(

(no longer quadratic function of VGS)

– Saturation region is extended: VDSAT < VGS-VT


Mobility degradation

• MOS I/V equations depend on surface mobility n (or p)

• In short-channel devices, n and p are not constant

– As vertical electric field Ex increases, surface mobility decreases

0 = low-field mobility, is empirical constant

– As VGS increases, surface mobility decreases

TGS VV

10


Threshold voltage variation

• Until now, threshold voltage assumed constant

– VT changed only by substrate bias VSB

• In threshold voltage equations, channel depletion region assumed to be created by gate voltage only

• Depletion regions around source and drain neglected: valid if channel length is much larger than depletion region depths

• In short-channel devices, depletion regions from drain and source extend into channel



Short-channel effects cause threshold voltage variation:

• VT rolloff

– As channel length L decreases, threshold voltage decreases

• Drain-induced barrier lowering

– As drain voltage VDS increases, threshold voltage decreases

• Hot-carrier effect

– Threshold voltages drift over time


Source depletion region

Drain depletion region

Gate-induced depletion region


• Even with VGS=0, part of channel is already depleted

• Bulk depletion charge is smaller in short-channel device → VT is smaller

N+ source

N+ drain


• Change in VT0:

– xdS, xdD: depth of depletion regions at S, D

– xj: junction depth

1

211

21

222

10

j

dD

j

dSjFASi

oxT x

x

x

x

L

xNq

CV

VT0 is proportional to (xj/L)

– For short channel lengths, VT0 is large

– For large channel lengths, term approaches 0



Threshold voltage variations

Graphically: VT0 versus channel length L

VT0

L

Long-channel VT

Lnom

VT Roll-off:VT decreases rapidly with channel length


DIBL

• Drain-induced barrier lowering (DIBL)

– Drain voltage VDS causes change in threshold voltage

– As VDS is increased, threshold voltage decreases

• Cause: depletion region around drain

– Depletion region depth around drain depends on drain voltage

– As VDS is increased, drain depletion region gets deeper and extends further into channel

– For very large VDS, source and drain depletion regions can meet → punch-through!

• Issue: results in uncertainty in circuit design



• Hot-carrier effect

– increased electric fields causes increased electron velocity

– high-energy electrons can tunnel into gate oxide

– This changes the threshold voltage (increases VT for NMOS)

– Can lead to long-term reliability problems



• Hot electrons

– High-velocity electrons can also impact the drain, dislodging holes

– Holes are swept towards negatively-charged substrate → cause substrate current

– Called impact ionization

– This is another factor which limits the process scaling → voltage must scale down as length scales


Threshold voltage variations

• Summary of threshold variations in short-channel devices

– VT rolloff: threshold voltage reduces as channel length L

reduces

– DIBL: threshold voltage reduces as VDS increases

– Hot-carrier effect: threshold voltage drifts over time as electrons tunnel into oxide


Short-channel summary

• Both devices have same effective W/L ratio → I/V curves should be similar

• Short-channel device has ~ 40% less current at high VDS

• Note linear dependence on VGS in short-channel device

Long-channel Short-channel


Sub-threshold conduction

• When VGS < VT, transistor is “off”

– However, small drain current ID still flows

– Called subthreshold leakage current

• Model for subthreshold current:

– Increases as VGS increases (potential barrier lowered)

– Increases as VDS increases (DIBL)

DSGS BVAVkT

q

SD WeIldsubthreshoI

)(


Subthreshold conduction

• Exponential relationship to VGS

log IDS(sub)

VGSVT

subthreshold slope(mV/decade of current)

• Subthreshold slope:

• Shift in VGS required to reduce leakage by factor of 10

• Typical values: 80-120 mV/decade


Gate leakage

• Another source of leakage current is gate leakage (Fowler-Nordheim Tunneling)

• For very thin gate oxide, electrons can tunnel through the gate oxide, resulting in current from gate to drain or source

• Equation for gate leakage current:

oxE

E

oxFN eWLECI0

21

E0, C1 constantsEox = electric field across oxide

• IFN proportional to area of gate

• Limits scaling of gate oxide


Leakage

• Effect of leakage current

– “Wasted” power: power consumed even when circuit is inactive

– Leakage power raises temperature of chip

– Can cause functionality problem in some circuits: memory, dynamic logic, etc.

• Reducing transistor leakage

– Long-channel devices

– Small drain voltage

– Large threshold voltage VT


Leakage

• Leakage vs. performance tradeoff:

– For high-speed, need small VT and L

– For low leakage, need high VT and large L

• Process scaling

– VT reduces with each new process (historically)

– Leakage increases ~10X!

• One solution: dual-VT process

– Low-VT transistors: use in critical paths for high speed

– High-VT transistors: use to reduce power


Channel Length Modulation

• In saturation, pinch-off point moves

– As VDS is increased, pinch-off point moves closer to source

– Effective channel length becomes shorter

– Current increases due to shorter channel

DSTNGSoxnD VVVL

WCI

LLL

12

21

'

= channel length modulation coefficient


SPICE Model Equations

• SPICE Level 1

– Approximations (GCA) from SESSION 1

– Useful for hand calculations

• SPICE Level 2

– Variation of mobility with electric field

– Variation of channel length in saturation (more accurate)

– Carrier velocity saturation

– Subthreshold conduction

• SPICE Level 3

– Mostly empirical

– Accurate to 2m


• Improvement in CMOS process technology. Reduction in device dimensions, improved circuit performance

• First-order constant field scaling

Apply a dimensionless factor > 1 to all dimensions, device voltages and concentration densities

• Constant voltage scaling

VDD is kept constant, process is scaled

• Lateral scaling

Only the gate length is scaled (“gate shrink”)

Scaling


MOSFET Scaling

• Constant Voltage

– Traditional, board-level compatible

• Constant Field

– Ideal, helps reliability

• Hybrid

– practical


Scaling

• Scaling has a threefold objective:

– Reduce the gate delay by 30% (43% increase in frequency)

– Double the transistor density

– Saving 50% of power (at 43% increase in frequency)

• How is scaling achieved?

– All the device dimensions (lateral and vertical) are reduced by 1/

– Concentration densities are increased by

– Device voltages reduced by 1/ (not in all scaling methods)

– Typically 1/ = 0.7 (30% reduction in the dimensions)


Constant Field

Before Scaling After Scaling

Length L L/s

Width W W/s

Oxide Thickness tox tox/s

Diffusion/Junction Depth Xj Xj/s

Supply Voltage VDD VDD/s

Threshold Voltage VT VT/s

Doping Densities NA,ND sNA,sND

dxE

dxEV


Constant Voltage

Before Scaling After Scaling

Length L L/s

Width W W/s

Oxide Thickness tox tox/s

Diffusion/Junction Depth Xj Xj/s

Supply Voltage VDD VDD

Threshold Voltage VT VT

Doping Densities NA,ND s2NA,s2ND

dxE

dxEV


Scaling: Capacitance Effects

• Constant Field


oxscaledox sCC , s

CC g

scaledg ,

oxscaledox sCC ,s

CC g

scaledg ,


Scaling: Current Effects

• Constant Field

Current density increases by s


Current density increases by s3

s

Is

Vs

VsL

sW

stI DTGS

ox

oxscaledD

2

, 2

DTGSox

oxscaledD sIVV

sL

sW

stI 2

, 2


Scaling: Power Effects

• Constant Field


2s

P

s

I

s

VP DDS

scaled

PsLsW

sP

A

P

scaled

scaled 2

sPsIVP DDSscaled

PssLsW

sP

A

P

scaled

scaled 3


Scaling: Performance Effects

• Constant Field


ssI

sVsCscaled

2

)/(

ssI

VsCscaled


Technology scaling

Some consequencies 30% scaling in the constant field regime (s = 1.43, 1/s = 0.7):

• Device/die area:W L (1/s)2 = 0.49

– In practice, microprocessor die size grows about 25% per technology generation! This is a result of added functionality.

• Transistor density:(unit area) /(W L) s2 = 2.04

– In practice, memory density has been scaling as expected. (not true for microprocessors…)


Technology scaling

• Gate capacitance:W L / tox 1/s = 0.7

• Drain current:(W/L) (V2/tox) 1/s = 0.7

• Gate delay:(C V) / I 1/s = 0.7Frequency s = 1.43

– In practice, microprocessor frequency has doubled every technology generation (2 to 3 years)! This faster increase rate is due to two factors:

– the number of gate delays in a clock cycle decreases with time (the designs become highly pipelined)

– advanced circuit techniques reduce the average gate delay beyond 30% per generation.


Technology scaling

• Power:C V2 f (1/s)2 = 0.49

• Power density:1/tox V2 f 1

• Active capacitance/unit-area:Power dissipation is a function of the operation frequency, the power supply voltage and of the circuit size (number of devices).


Technology scaling

• Interconnects scaling:

– Higher densities are only possible if the interconnects also scale.

– Reduced width increased resistance

– Denser interconnects higher capacitance


Technology scaling

– To account for increased parasitics and integration complexity

– more interconnection layers are added:

– thinner and tighter layers local interconnections

– thicker and sparser layers global interconnections and power

Interconnects are scaling as expected


SESSION 7: CMOS Technology Lecture 1

•Photolithography•CMOS Fabrication Sequence•Latch up


Lithography

Lithography: process used to transfer patterns to each layer of the IC

Lithography sequence steps:

• Designer:

– Drawing the layer patterns on a layout editor

• Silicon Foundry:

– Masks generation from the layer patterns in the design data base

– Printing: transfer the mask pattern to the wafer surface

– Process the wafer to physically pattern each layer of the IC


Lithography

Basic sequence

• The surface to be patterned is:

– spin-coated with photoresist

– the photoresist is dehydrated in an oven (photo resist: light-sensitive organic polymer)

• The photoresist is exposed to ultra violet light:

– For a positive photoresist exposed areas become soluble and non exposed areas remain hard

• The soluble photoresist is chemically removed (development).

– The patterned photoresist will now serve as an etching mask for the SiO2

1. Photoresist coating

SiO2

Photoresist

Substrate

3. Development

Substrate

Substrate

Mask

Ultra violet lightOpaque

ExposedUnexposed

2. Exposure


Lithography

• The SiO2 is etched away leaving the substrate exposed:

– the patterned resist is used as the etching mask

• Ion Implantation:

– the substrate is subjected to highly energized donor or acceptor atoms

– The atoms impinge on the surface and travel below it

– The patterned silicon SiO2 serves as an implantation mask

• The doping is further driven into the bulk by a thermal cycle

4. Etching

Substrate

Substrate

5. Ion implant

Substrate

6. After doping

diffusion


Lithography

• The lithographic sequence is repeated for each physical layer used to construct the IC. The sequence is always the same:

– Photoresist application

– Printing (exposure)

– Development

– Etching


Lithography

Patterning a layer above the silicon surface

Substrate

SiO2

Polysilicon

1. Polysilicon deposition

2. Photoresist coating

photoresist

Substrate

Substrate

3. Exposure UV light

Substrate

4. Photoresist development

Substrate

5. Polysilicon etching

Substrate

6. Final polysilicon pattern


Lithography

• Etching:

– Process of removing unprotected material

– Etching occurs in all directions

– Horizontal etching causes an under cut

– “preferential” etching can be used to minimize the undercut

• Etching techniques:

– Wet etching: uses chemicals to remove the unprotected materials

– Dry or plasma etching: uses ionized gases rendered chemically active by an rf-generated plasma

anisotropic etch (ideal)resist

layer 1

layer 2

resist

layer 1

layer 2

isotropic etch

undercut

resist

layer 1

layer 2

preferential etch

undercut


CMOS fabrication sequence

0. Start:

– For an n-well process the starting point is a p-type silicon wafer:

– wafer: typically 75 to 230mm in diameter and less than 1mm thick

1. Epitaxial growth:

– A single p-type single crystal film is grown on the surface of the wafer by:

– subjecting the wafer to high temperature and a source of dopant material

– The epi layer is used as the base layer to build the devices

P+ -type wafer

p-epitaxial layer Diameter = 75 to 230mm

< 1mm



2. N-well Formation:

– PMOS transistors are fabricated in n-well regions

– The first mask defines the n-well regions

– N-well’s are formed by ion implantation or deposition and diffusion

– Lateral diffusion limits the proximity between structures

– Ion implantation results in shallower wells compatible with today’s fine-line processes

p-type epitaxial layer

n-well

Lateraldiffusion

Physical structure cross section Mask (top view)n-well mask



3. Active area definition:

– Active area:

– planar section of the surface where transistors are build

– defines the gate region (thin oxide)

– defines the n+ or p+ regions

– A thin layer of SiO2 is grown over the active region and covered with silicon nitride

n-well

Silicon NitrideStress-relief oxide

p-type

Active mask



4. Isolation:

– Parasitic (unwanted) FET’s exist between unrelated transistors (Field Oxide FET’s)

– Source and drains are existing source and drains of wanted devices

– Gates are metal and polysilicon interconnects

– The threshold voltage of FOX FET’s are higher than for normal FET’s

p-substrate (bulk)

n+ n+

Parasitic FOX device

n+ n+



– FOX FET’s threshold is made high by:

– introducing a channel-stop diffusion that raises the impurity concentration in the substrate in areas where transistors are not required

– making the FOX thick

4.1 Channel-stop implant

– The silicon nitride (over n-active) and the photoresist (over n-well) act as masks for the channel-stop implant

n-well

p-type

channel stop mask = ~(n-well mask)

resit

Implant (Boron)

p+ channel-stop implant



4.2 Local oxidation of silicon (LOCOS)

– The photoresist mask is removed

– The SiO2/SiN layers will now act as a masks

– The thick field oxide is then grown by:

– exposing the surface of the wafer to a flow of oxygen-rich gas

– The oxide grows in both the vertical and lateral directions

– This results in a active area smaller than patterned

n-well

p-type

Field oxide (FOX)patterned active area

active area after LOCOS



• Silicon oxidation is obtained by:

– Heating the wafer in a oxidizing atmosphere:

– Wet oxidation: water vapor, T = 900 to 1000ºC (rapid process)

– Dry oxidation: Pure oxygen, T = 1200ºC (high temperature required to achieve an acceptable growth rate)

• Oxidation consumes silicon

– SiO2 has approximately twice the volume of silicon

– The FOX is recedes below the silicon surface by 0.46XFOX

XFOX

0.54 XFOX

0.46 XFOX

Silicon wafer

Silicon surface

Field oxide



5. Gate oxide growth

– The nitride and stress-relief oxide are removed

– The devices threshold voltage is adjusted by:

– adding charge at the silicon/oxide interface

– The well controlled gate oxide is grown with thickness tox

n-well

p-type

n-well

p-type

tox tox

Gate oxide



6. Polysilicon deposition and patterning

– A layer of polysilicon is deposited over the entire wafer surface

– The polysilicon is then patterned by a lithography sequence

– All the MOSFET gates are defined in a single step

– The polysilicon gate can be doped (n+) while is being deposited to lower its parasitic resistance (important in high speed fine line processes)

n-well

p-type

Polysilicon gate

Polysilicon mask


CMOS fabrication sequence7. PMOS formation

– Photoresist is patterned to cover all but the p+ regions

– A boron ion beam creates the p+ source and drain regions

– The polysilicon serves as a mask to the underlying channel

– This is called a self-aligned process

– It allows precise placement of the source and drain regions

– During this process the gate gets doped with p-type impurities

– Since the gate had been doped n-type during deposition, the final type (n or p) will depend on which dopant is dominant

n-well

p-type

p+ implant (boron)p+ mask

Photoresist



8. NMOS formation

– Photoresist is patterned to define the n+ regions

– Donors (arsenic or phosphorous) are ion-implanted to dope the n+ source and drain regions

– The process is self-aligned

– The gate is n-type doped

n-well

p-type

n+ implant (arsenic or phosphorous)n+ mask

Photoresist



9. Annealing

– After the implants are completed a thermal annealing cycle is executed

– This allows the impurities to diffuse further into the bulk

– After thermal annealing, it is important to keep the remaining process steps at as low temperature as possible

n-well

p-type

n+ p+



10. Contact cuts

– The surface of the IC is covered by a layer of CVD oxide

– The oxide is deposited at low temperature (LTO) to avoid that underlying doped regions will undergo diffusive spreading

– Contact cuts are defined by etching SiO2 down to the surface to be contacted

– These allow metal to contact diffusion and/or polysilicon regions

n-well

p-type

n+ p+

Contact mask



11. Metal 1

– A first level of metallization is applied to the wafer surface and selectively etched to produce the interconnects

n-well

p-type

n+ p+

metal 1 maskmetal 1



12. Metal 2

– Another layer of LTO CVD oxide is added

– Via openings are created

– Metal 2 is deposited and patterned

n-well

p-type

n+ p+

Via metal 1

metal 2



13. Over glass and pad openings

– A protective layer is added over the surface:

– The protective layer consists of:

– A layer of SiO2

– Followed by a layer of silicon nitride

– The SiN layer acts as a diffusion barrier against contaminants (passivation)

– Finally, contact cuts are etched, over metal 2, on the passivation to allow for wire bonding.


Yield

• The yield is influenced by:

– the technology

– the chip area

– the layout

• Scribe cut and packaging also contribute to the final yield

• Yield can be approximated by:

A - chip area (cm2)

D - defect density (defects/cm2)

Ynumber of good chips on wafer

total number of chips

Y e A D 0 2 4 6 8 10

10

100

Yie

ld (

%)

Yield tendency

20

40

60

80

1.0 defects/cm2

2.5 defects/cm2

5.0 defects/cm2

Chip edge ( area in mm)


Other processes

• P-well process

– NMOS devices are build on a implanted p-well

– PMOS devices are build on the substrate

– P-well process moderates the difference between the p- and the n-transistors since the P devices reside in the native substrate

– Advantages: better balance between p- and n-transistors

p-well

n-typen+ p+


Other processes

• Twin-well process

– n+ or p+ substrate plus a lightly doped epi-layer (latchup prevention)

– wells for the n- and p-transistors

– Advantages, simultaneous optimization of p- and n-transistors:

– threshold voltages

– body effect

– gain

p-well

n+ substrate

n+ p+

n-well

epitaxial layer


Other processes

• Silicon On Insulator (SOI)

– Islands of silicon on an insulator form the transistors

• Advantages:

– No wells denser transistor structures

– Lower substrate capacitances

n+ p- n+

S DG

p+ n- p+

S DG

sapphire (insulator)

polysilicon

thinoxide

SiO2phosphorus glass or SiO2


Other processes

– Very low leakage currents

– No FOX FET exists between unrelated devices

– No latchup

– No body-effect:

– Radiation tolerance

• Disadvantages:

– Absence of substrate diodes (hard to implement protection circuits)

– Higher number of substrate defects lower gain devices

– More expensive processing


Advanced CMOS processes

• Shallow trench isolation

• n+ and p+-doped polysilicon gates (low threshold)

• source-drain extensions LDD (hot-electron effects)

• Self-aligned silicide (spacers)

• Non-uniform channel doping (short-channel effects)

n-well

p+ p+n+ n+p-doping n-doping

Silicide Oxide spacern+ poly p+ poly

Shallow-trench isolation

p-type substrateSource-drain

extension


Process enhancements

• Up to six metal levels in modern processes

• Copper for metal levels 2 and higher

• Stacked contacts and vias

• Chemical Metal Polishing for technologies with several metal levels

• For analogue applications some processes offer:

– capacitors

– resistors

– bipolar transistors (BiCMOS)


Latchup

• CMOS process contains parasitic bipolar transistors

• Under certain conditions, these parasitic transistors can turn on, shorting power and ground rails and usually destroying the chip → latchup

• Avoiding latchup requires certain layout design rules, and careful control of process

• Latchup was a major problem in early CMOS processes

• Now, latchup is mainly issue for I/O circuits, with high current demands and possibly noisy voltages


Latchup

• Current flowing in well or substrate can forward-bias bipolar transistor

• Positive feedback between transistors: when one turns on, Vdd and Gnd are connected

• Solution: reduce Rnwell and Rpsubs: use many substrate taps in layout

• High-current circuits use guard rings

NMOS PMOSsubstrate tap n-well tap


SESSION 8: DESIGN RULES Lecture 1

•Eular graph•Stick diagrams •Design rules•Layout example


Why we need design rules

• Masks are tooling for manufacturing.

• Manufacturing processes have inherent limitations in accuracy.

• Design rules specify geometry of masks which will provide reasonable yields.

• Design rules are determined by experience


Manufacturing problems

• Photoresist shrinkage, tearing.

• Variations in material deposition.

• Variations in temperature.

• Variations in oxide thickness.

• Impurities.

• Variations between lots.

• Variations across a wafer.


Transistor problems

• Variations in threshold voltage:

– oxide thickness;

– ion implantation;

– poly variations.

• Changes in source/drain diffusion overlap.

• Variations in substrate.


Wiring problems

• Diffusion: changes in doping -variations in resistance, capacitance.

• Poly, metal: variations in height, width - variations in resistance, capacitance.

• Shorts and opens.


Oxide problems

• Variations in height.

• Lack of planarity -> step coverage

metal 1metal 2

metal 2


Via problems

• Via may not be cut all the way through.

• Undersize via has too much resistance.

• Via may be too large and create short.


Constraints on Layout

Resolution constraints

– What is the smallest width feature than can be printed

– What is the smallest spacing that will guarantee no shorts

– Depends on lithography and processing steps that follow

– Resolution often depends on the smoothness of the surface

– need to keep the image in focus, since depth of field is small

– Most modern processes are planarized, to keep surface flat


Constraints on Layout

– Alignment/overlap constraints

– Like printing a color picture, need to align layers to each other

– Need to choose which layer to align to

– That layer will have better registration than the others.


Design Rules

• Interface between designer and process engineer

• Guidelines for constructing process masks

• Unit dimension: Minimum line width

– scalable design rules: lambda parameter

– absolute dimensions (micron rules)


MOSIS SCMOS design rules

• Designed to scale across a wide range of technologies.

• Designed to support multiple vendors.

• Designed for educational use.

• Ergo, fairly conservative.


and design rules

• is the size of a minimum feature.

• Specifying particularizes the scalable rules.

• Parasitics are generally not specified in units.


Resolution design rules

• Minimum line-width:

– smallest dimension permitted for any object in the layout drawing (minimum feature size)

• Minimum spacing:

– smallest distance permitted between the edges of two objects

• This rules originate from the resolution of the optical printing system, the etching process, or the surface roughness

Minimum spacing

Minimum width


and design rules

• Contacts and vias:

– minimum size limited by the lithography process

– large contacts can result in cracks and voids

– Dimensions of contact cuts are restricted to values that can be reliably manufactured

– A minimum distance between the edge of the oxide cut and the edge of the patterned region must be specified to allow for misalignment tolerances (registration errors)

n+p

metal 1

n+ diffusion

metal 1

d

dContact size

Registration tolerance

Contact

x2

n+ diffusion

metal 1

x1


and design rules

• MOSFET rules

– n+ and p+ regions are formed in two steps:

– the active area openings allow the implants to penetrate into the silicon substrate

– the nselect or pselect provide photoresist openings over the active areas to be implanted

– Since the formation of the diffusions depend on the overlap of two masks, the nselect and pselect regions must be larger than the corresponding active areas to allow for misalignments

Correct mask sizing

overlap

x

xactive

nselect

n+

p-substrate

Incorrect mask sizing

overlap

x

xactive

nselectp-substrate

n+


and design rules

• Gate overhang:

– The gate must overlap the active area by a minimum amount

– This is done to ensure that a misaligned gate will still yield a structure with separated drain and source regions

• A modern process has may hundreds of rules to be verified

– Programs called Design Rule Checkers assist the designer in that task

gate overhang

no overhang

no overhangand misalignment

Short circuit


CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green


Wires

metal 23

metal 13

pdiff/ndiff3

poly2


Intra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole


Transistor Layout

2

3

1

3 2

5


Via’s and Contacts

• In SCMOS, the spacing from contacts is often slightly larger than base material

– Poly contact to poly spacing is 3

– Diffusion contact to diffusion is 4

• This is done so the fabricator can make the surround of the actual contact cut slightly larger than 1 if needed


Via’s and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


Select Layer

1

3 3

2

2

2

WellSubstrate

Select3

5


CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’


Stick diagrams

• A stick diagram is a cartoon of a layout.

• Does show all components/vias (except possibly tub ties), relative placement.

• Transistor 1 is to the right of transistor 2, and under transistor 3

• Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

– Each wire is assigned a layer, and crossing wires must be on different layers


Stick Diagrams

But

– Wires are drawn as stick figures with no width

– The size of the objects is not to scale

– If you forgot a wire you can squeeze it in between two other wires

– It does not have to be beautiful

It is faster to draw a stick diagram first with pencils and paper


Stick layers

metal 2

metal 1

poly

ndiff

pdiff


Dynamic latch stick diagram

VDD

in

VSSphi

out

phi’


Using the Design Rules

• SCMOS design rules are simplified, there are still a number of rules to remember.

• Begin with a stick diagram of the cell you want to layout.

• Use a subset of the rules to estimate what the layout will look like,

• if it meets your standards-begin the actual layout.

• Good idea to have a plan on where things go before you start.

• Warning:

Layout is often (sometimes) fun to do- can be an infinite time sink

Can find a way to shrink the cell a few more microns.


Layout Issues

In CMOS there are two types of diffusion

• ndiff (green surrounded by hatched pwell)

– Poly crossing ndiff makes NMOS transistors

• pdiff (green surrounded by dotted nwell)

– Poly crossing pdiff makes PMOS transistors

Be careful, ndiff and pdiff are different

• Can’t directly connect ndiff to pdiff

– Must connect ndiff to metal and then metal to pdiff

• Can’t get ndiff too close to pdiff because of wells

– Large spacing rule between ndiff and pdiff

– Means you need to group NMOS devices together and PMOS devices together


Basic Layout Planning

Simple guidelines to CMOS layouts

• You need to route power and ground. (in metal)

– No one will auto connect it for you.

• Keep NMOS devices near NMOS devices and PMOS devices near PMOS devices.

– So NMOS usually are placed near Gnd, and PMOS near Vdd You need to route power and ground. (in metal)

– No one will auto connect it for you.

• Run poly vertically and diffusion horizontally, with metal1 horizontal (or the reverse, just keep them orthogonal)

– Good default layout plan


Basic Layout Planning

Simple guidelines to CMOS layouts

• Keep diffusion wires as short as possible (just connect to transistor)

• All long wires (wire that go outside a cell, for example) should be in either m1 or m2.

• Try to design/layout as little stuff as possible (use repetition/tools)

– Critical issue


Typical Cell Layout Plan

• The Parity

(note: no PMOS and no Vdd Gnd) (very unusual)

• CMOS Inverter/Buffer

Even

Odd

A A_b

Even Out

Odd Out

A A_b

Vdd

Gnd


Estimating Area from Sticks

• Draw stick diagram

• Find the critical length path in X and in Y

• Count the number of contacted pitches

– If transistors are not minimum width, remember to take that into account

• If you not happy with the answer, goto step 1 and try again.

– Else you are done, and you can try to layout the cell.

• May miss the real critical length path

• Will get better at seeing the critical path as you do more layout.


CMOS gate layout

• Goal: minimum area

• Method

– Minimize diffusion breaks (reduces capacitance on internal nodes)

– Align transistors with common gates above each other in layout (minimizes poly length)

– Group PMOS and NMOS transistors together

• Approach:

– Use Euler path method to find ordering of transistors in layout


Layout: Euler path method

• Goal: layout without diffusion breaks

• Method for finding ordering of transistors in layout → Euler path

– Euler path → path through a graph that traverses each edge only once

– Find common Euler path in pullup and pulldown graph

– This gives the ordering of inputs in the layout


Euler path method

• Example: complex CMOS gate

A

B

C

D

E

A

D

C

EB

NMOS network PMOS network

Euler path: B→A→C→E→D Euler path: B→A→C→E→D

Common Euler path!

gnd

F

FVdd


Layout: Euler path method

A

B

C

D E

C E

D

BA

Euler path: B→A→C→E→D

B A C E D

VDD

Gnd

F

F

1. Order transistors gates according to Euler path

2. Connect VDD and Gnd3. Make other connections according

to circuit diagram


GND

x

a

b c

d

VDDx

GND

x

a

b c

d

VDDx

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

a c d

x

VDD

GND

(c) stick diagram for ordering {a b c d}

b

Example: x = (ab+cd)’


CMOS layout styles

• Full-custom

– Design broken into complex logic blocks

– Each block is laid out “by hand”

– Limited re-usability

• Standard cell

– Design broken into gates, either by logic designer or automated synthesis tool

– Library of standard cells created

– Correct cells chosen from library, connected by layout designer or place and route tool


Standard cells

• Example standard cell gates:

– inverters, buffers, XOR gates

– 2,3,4-input NAND, NOR

– And-Or-Invert (AOI) gates

– Or-And-Invert (OAI) gates

– Latches, flip-flops, etc

• Multiple versions of each gate:

– Designed for different output loads

• Detailed specifications

– Delays for each input combination

cmos funda full course

Documents

oxoxoxbf gc

euler path

cload vout

work function

vt0 vd lt

final vout

gs ox

threshold