cmos adc & dac principles -...

Willy Sansen 10-05 201

CMOS ADC & DAC Principles

Willy Sansen

KULeuven, ESAT-MICASLeuven, Belgium

[email protected]


Table of contents

• Definitions• Digital-to-analog converters• Resistive• Capacitive• Current steering

• Analog-to-digital converters• Integrating• Successive approximation• Algorithmic• Flash / Two-step• Interpolating / Folding• Pipeline


ADC & DAC

Output code Analog output (wrt Vref)

0

1

0 1Analog input (with respect to Vref) Input code

Ideal

Ideal

0.5

0.5


DACs Resolution

VOUT = VREF BIN

VLSB =

b1

21= VREF ( + + + … )

VREF

b3

23

b2

22

bN

2N

2N

Resolution Nb1 is Most Significant bit (MSB)bN is Least Significant bit (LSB)

Analog output (wrt Vref)

0

1

Input code

Ideal


The quantisation error of a DAC

PNoise = ∫ ε2 dε =-∆/2

∆2

121∆

∆/2

Vptp = 2N ∆

PSignal =Vptp

2

8

SNR = 22N

SNR = 6 N + 1.76 dB

32


Static specs : INL & DNL

Differential Nonlinearity : DNL = YOUT(B) - YOUT(B-1) - 1 LSBIntegral Nonlinearity : INL = YOUT(B) - YOUT,id(B)

Analogoutput

Analogoutput

Digital inputDigital input

Monotonicity


Dynamic specifications


Spectral content : Spurious free dynamic range

SFDR

Frequency (Hz)

dB


Output SNR versus input Signal

Limited by distortion

-3 dB


Table of contents




Resistor string DAC

For 10 bit:1023 resistors and1024 switches !!

Resistive matching !


Binary weighted resistor DAC

One Resistor and Switch per bitNo guaranteed monotonicity (glitches !)


R-2R DAC

IRIR2

IR4

IR8

IR8

IRIR2

IR4

IR2

IR + + + IR4

IR8

Smaller area in Resistors !


3-bit charge redistribution DAC

Phase Φ1

Better capacitive matching !


4-bit Current steering DAC

Resolution limited byMismatch in theCurrent sources !

Glitches !


The Binary and thermometer codes

Monotonicity guaranteed !


Thermometer-code Current steering DAC


Binary, unary, segmented DAC

Binary

σ (∆I) =

Unary

SegmentedB LSBs & N-B MSBs

2B+1 - 1 LSBσ (I)

I

LSBσ (I)

I

2N - 1 LSBσ (I)

I

Van den Bosch, .., Kluwer 2004


σ(I)/I versus resolution

Yield =

10 %

50 %

99.7 %

σ (I) I

=1

2 C 2N

C ≈ 6.2 10-4

for INL_yield = 90%

90 %



Switching schemes

is centroide !


Miki, JSSC Dec.86,983-988


INL error for different switching schemes

Hierarchical symmetrical scheme (type A)


DAC Design: Static Accuracy

INL_yield = percentage of functional D/A converters with an INL specification smaller than half an LSB.

INL_yield = f (mismatch) = f ( )

High yield

small

Large current source area

σ (I) I

σ (I) I

σ (I) I

≤ 1

2 C 2N

WL = 1

2 ( )2[ Aβ

2 + ] (VGS-VT)2

4AVT2

σ (I) I

σ (Iunit)/Iunit = 0.25 %


DAC Design: Calculation W and L

WL = 1

2 ( )2[ Aβ

2 + ] (VGS-VT)2

4AVT2

σ (I) I

= LW

K’ (VGS-VT)2ILSB

σ (I)/I = 0.0025VGS-VT = 1 VFor 0.35 µm CMOS Aβ ≈ 2 %µm

AVT ≈ 7 mVµm

W = 1.8 µmL = 30 µm


Floorplan 10-bit segmented DAC

Van den Bosch, .., JSSC March 01, 315-324

Mcs

Msw

Mcas


Required output impedance versus resolution

10 bit 1GB/sINL = 99.7 %requires σ(I)/I < 0.5 % :W = 2 µm & L = 8 µmVan den Bosch, .., Kluwer 2004

JSSC March 01, 315-324


10-bit 1 GS/s Nyquist Current steering CMOS DAC

Van den Bosch, .., JSSC, March 01, 315-324

Current steeringDAC

10-bit 1 GS/s

0.35 µm CMOS110 mW


SFDR (dB) versus relative signal frequency

fsignal / fclock


FOM (MHz/mW) vs inverse area

FOM =

2N/area (mm2)

P2N fs(-6dB)


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FOM =

P4kT BW DR

Speed Resolution Limits ADC

P2N 2BW


Dual-slope (integrating) ADC

Time 1 is constant : T1 = 2N Tclk

Vx = T1Vin

R1C1

Time 2 : Vx decreases with constant slope :

Vx = T2Vref

R1C1

Bout =Vin

VrefT2 = T1

Vin

VrefJohns, Martin, Wiley 1997


Operation of integrating ADC

Time 1 : Vx = T1Vin

R1C1 Time 2 : Vx = T2

Vref

R1C1 T2 = T1

Vin

Vref


Integrating ADC

Advantages:High resolutionHigh linearityLow circuit complexityMainly for voltmeters, …Eliminates mains supply 50 Hz if T1 is n x 20 ms

Disadvantages:Very slow :Worst case for Vin = Vref : 22n+1 clock cycli required !

Ex. For n = 16 bit (64000) and Fclock = 1 MHz : 7.6 s conversion time

Mainly for voltmeters, …


Successive-approximation ADC

Johns, Martin, Wiley 1997

Divide interval by 2 ;Determine bit :< 1 : 0 b1 = MSB< 0.5 : 0 b2

> 0.25 : 1 b3

> 0.375 : 1 b4< 0.4375 : 0 b5…..

0 1 V0.25 0.5


5-bit Charge redistribution ADC

Vx ≈ 0

1. Sample Mode

Accuracy limited by capacitive matching to 10-12 bitSpeed limited by RswitchC time constants

McCreary, JSSC Dec 75, 371-379

Σ = 2N C




Vx = -Vin

2. Hold mode

Bottom plate C to Vref



Vx = -Vin +

3. Bit cycling

Vref

2

if Vin > Vref/2 SAR 1 leave Cb1 to Vref : try Cb2if Vin < Vref/2 SAR 0 leave Cb1 to Gnd : try Cb2

Bottom plate C to Vref


Charge redistribution ADC

Bottom plate Cto Vref

Charge redistribution ADC halves Vref in each cycleAlgorithmic ADC doubles Verror in each cycle


Algorithmic (or cyclic) ADC

Advantage : small amount of analog circuitryDifficulty : accuracy x2 Gain amplifier

(fully diff. ; Cpar insensitive)Johns, Martin, Wiley, 2003


Flash converter

3-bit flash ADC :

fastest23 comparatorsinput cap. ~ 23

limited to 6 bit(1 … 2 GS/s)


Evolution in ADC’s

Uyttenhove, KULeuven, 2003


Subranging (or two-step) ADC

8-bit two-step ADC :less comparatorsintroduces latency

28 = 256 comp. now 32 !All circuits : 8b accurateDigital correction required !



Interpolating saves amplifiers

Input amplifierswhich saturate

saturating

saturating

linear near threshold

Van de Grift, JSSC Dec. 87, 944-953; Steyaert CICC 1993

threshold latch


Interpolating ADC

4-bit interpolating ADCResistive interpolation

leave out 3 out of 4 ampsLess power consumptionLess input capacitance



Transfer curves

Resistors generate the intermediate outputsResistors average out offsets, etc.Add series resistors to latch inputs to equalize delay times

Only the zero crossings carry info

Gain ~ 10


Averaging with output currents

I2a = I1 + I232

31

I2b = I1 + I231

32

Interpolating by 3between output currents I1 & I2Requires 1/3 input amps.: Cin/3

Steyaert CICC 93


Interpolating/Averaging ADC - 1st amp

Current mirror interpolatorSteyaert CICC 93Roovers JSSC July 96, 938-944


Interpolating : limitations

Cmirror (fF) f-3dB (MHz)

Number of transistors


Folding ADC Analog preprocessing

foldingcircuit

fineADC

coarseADC

LSBs

MSBs

Vin

folded signal

Vin

folded signal Folding rate 8Less comparatorsSame input capacitance

1 2 3 4 5 6 7 8


= 4latches

Vin starts

from 0 to 1/4 :0001001101111111

from 1/4 to 1/2 :1110110010000000

4-bit flash: 16 comp.folding: 8 comp.

4 folding regions


4-bit Folding ADC


Folding block realization

Folding rate of 4

Differential pairsin parallel !

Output at higher freq. =fin x folding rate

Large Cin !



Folding rate of 4Interpolate by 2

Lower Cin !

Van Valburg JSSC Dec. 92, 1662-1666

Folding + interpolation



Pipelined ADC : nk and single bit per stage


nk bit per stagelatency of N clock periodsLimited to 12 bit by amp. Digital error correction

Algorithmic conversionin pipeline !

1 bit per stage


Pipelined ADC block diagram

New sample each clock cycle



Multiplying DAC

S/H

DAC + Gain Are mergedIn one building block:

Multiplying DAC

Ni bitsADC

Ni bitsDAC


Multiplying DAC : Phase 1

Vres(i+1)

Vres(i)

VDAC

Cf

Cs

Φ1Φ1

Vres(i+1)

Vres(i)Cf

Cs


Multiplying DAC : Phase 2

Vres(i+1)

Vres(i)

VDAC

Cf

Φ2

Vres(i+1) = Vres(i) + (Vres(i) - VDAC)VDAC

Cf

Cs

Cs

Cs

Cf

G = 1 + CsCf

= 2 if Cs = Cf


Non-idealities versus Cs

Uyttenhove, Kuleuven, 2003

0.25 µm CMOSfs = 400 MHz


Comparison ADCs

Resolution (bits)

Clock cyclesPer output sample

100 1000101


Impact of device mismatch on resolution/power

Two transistors : σ 2(Error) ~ WL1

(Accuracy) 2 ~ WL

By design : increasing W increases IDS and Power

decreasing L increases the speed

Speed x (Accuracy)Power

= Technol. constant

AVT

WLσVT =

Ref. Kinget, ...“Analog VLSI ..”pp 67, Kluwer 1997.


Power and mismatch/noise

Accuracy 1/σ 2(Vos) ~ Area / AVT

Dynamic range DR = VsRMS / (3 σ (Vos))Capacitance C ~ Cox AreaPower P = 8 f C VsRMS

2

Mismatch : P = 24 Cox AVT2 f DR2

Noise : P = 8 kT f DR2


Noise vs mismatch for DR

Mismatch

Noise

Ref. P.Kinget, ...“Analog VLSI ..”page 67,Kluwer 1997.


ADC limitations

Ref Walden IEEE Selected Areas Comm. April 1999, 539-550; Uyttenhove 2003


References

• D. Johns & K. Martin, “Analog Integrated Circuit Design”, Wiley 1997

• P. Jespers, “Integrated Converters”, Oxford Univ. Press, 2001

• B. Razavi, “Principles of Data Conversion System Design”, IEEE Press 1995

• K. Uyttenhove, “High-speed CMOS Analog-to-digital converters”, PhD KULeuven, 2003

• A. Van den Bosch, … “High-resolution high-speed CMOS current-steering Digital-to-Analog Converters, Kluwer Ac. Press 2004.

• R. Van de Plassche, “Integrated Analog-to-digital and Digital-to-Analog converters”, Kluwer Ac. Press, 1994


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