CloudV: A Cloud-Based Educational Digital Design Environment

Mohamed Shalan School of Sciences and Engineering The American University in Cairo

Cairo, Egypt mshalan@aucegypt.edu

Sherief Reda School of Engineering

Brown University Providence, RI 02912

sherief_reda@brown.edu

Abstract—This paper describes a cloud-based digital design environment for ASIC and FPGA. We call it CloudV. CloudV is built using open-source as well as homegrown EDA software tools. The ultimate goal of CloudV is to reduce the design costs by relying on cloud infrastructure and on collaborative design. Currently, CloudV v 1.0 allows students to gain hands-on experience in digital ASIC design tasks covering HDL design entry, HDL simulation, RTL synthesis and technology mapping. Physical implementation support for ASIC and FPGA is in the work to have a complete digital design flow. CloudV enhances the quality of teaching, as students focus on design activities instead of spending their time learning how to use new software tools. Moreover, students can, virtually, use CloudV anywhere using any connected computing device. The open-source nature of CloudV provides educators with a single shared platform for their tutorial and design assignments.

Keywords— Blended Learning, Cloud, Electronic Design Automation, CloudV, Digital Design, FPGA, ASIC, Open Source, Design Flow, Simulation, Verilog, RTL, Waveform Viewer, FSM

I. INTRODUCTION Modem Information Technology has enabled several new

possibilities in learning such as blended learning. Blended learning is a formal educational format in which a student learns, at least partially, through online delivery of content and instruction. Blended learning gives the students control over time, place, path, or pace. This way blended learning makes students, instructors and schools more productive, both academically and financially [1].

Cloud computing is a distributed computing paradigm that connects everyone across the world [2]. Cloud computing combines hardware and network resources to deliver different kinds of services via the web. Institutions started to migrate blended learning services to the cloud to overcome the cost of procuring, hosting and managing Information and communication Technology (ICT) infrastructure in their premises. Several researches have been involved in the construction of e-Learning platform in the cloud-computing environment [3][4][5][6][13][15].

To enable blended learning in engineering education, cloud-based web accessible design tools are needed. While there exists some cloud-based engineering tools [7][8], such tools are not widely available for all engineering domains. For

example, cloud-based design tools for digital ASIC/FPGA do not exist.

Teaching digital ASIC design involves real challenges when preparing hands-on laboratory exercises. As a starter, professional EDA (Electronic Design Automation) tools for digital ASIC usually involve expensive licenses, special computing requirements for the laboratory workstations and complex administrator tasks. In addition, students usually do not have enough time during the lab sessions to truly master the usage of several EDA tools required to carry out the design.

In order to overcome the aforementioned issues and to enable collaborative learning, we propose a cloud-based digital ASIC/FPGA design environment utilizing open-source and the freely available academic EDA tools. We call this design environment: CloudV, and it is available at http://cloudv.io. CloudV allows students to use EDA tools thorough standard and familiar web interfaces. Also, it allows them to do their lab exercises and projects, virtually, anywhere using, only, any connected computing device (e.g., laptop, desktop, or tablet). CloudV has been used successfully in teaching digital design courses at the American University in Cairo (AUC) [20][21]. Currently, the scope of CloudV v1.0 is limited to design entry, Verilog HDL simulation, RTL synthesis and technology mapping for digital ASIC. An effort is undergoing to extend this to cover physical implementation for ASIC and FPGA. The web-based interface of CloudV enables smooth collaborative work experience, where educators can share important design modules that can be incorporated into student designs, and also enables collaborative work on joint design projects by students. Another advantage for CloudV is that it enables educators to converge on a common platform for their coursework, which can facilitate the development of course material, such as laboratory instructions and tutorials.

This paper is organized as follows. In Section II, we provide an overview of CloudV and its components in details. The future plans for CloudV are discussed in Section III. Finally, we summarize our conclusions in Section IV.

II. CLOUDV OVERVIEW As illustrated in Figure 1, CloudV runs on cloud servers

hosting CloudV backend, including the EDA design tools, as well as the users’ design files/data. The backend of CloudV application is implemented using the MEAN software

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stack [9]. The frontend is an HTML-5 application that runs on top of any modern web browser. The frontend application relies on services provided by the backend components.

Figure 1. CloudV Overview

The tools and libraries, used to build CloudV backend and

frontend, are outlined in Figure 2. Any component labelled with a “*” next to it indicates an existing open-source free EDA tool; the rest are tools developed to complete the flow. The open-source components (not home-grown) are as follows:

• iVerilog [10]: used for simulation and RTL linting.

• Yosys and ABC [11]: used for Verilog RTL synthesis and technology mapping.

• ACE Editor [16]: ACE is an embeddable code editor developed in JavaScript. CloudV uses it as its primary HDL code editor.

• Oklahoma State University (OSU) standard cell libraries [12].

The following tools are developed to complete the flow:

• vUtilities: Set of backend utilities that includes developed in JavaScript utilizing Node.js framework:

o Value Dump Change (VCD) to JavaScript Object Notation (JSON) translator: needed by FlexWave waveform viewer.

o FSM to Verilog compiler: generates synthesizable Verilog HDL code from the FSM description captured by FSMEdit.

o Test Bench Generator: generates a testbench skeleton for the given Verilog module.

• gUtilities: set of utilities that operate on the synthesized gate level netlist to optimize the design and to report useful information about the design, such asdesign area, power, and timing paths slacks.

• FSMEdit: a graphical Finite State Machine (FSM) editor

• FlexWave: a waveform viewer that displays the VCD files generated from simulating the testbenches.

Figure 2. CloudV Backend and Frontend Components

Currently, students are able to access CloudV backend EDA tools through familiar web interfaces (CloudV frontend). These web interfaces provide means for:

• Account Management: Enables user to create their accounts and include their relevant technical personal information.

• Projects Management: includes the ability to create and organize projects, as well as import design modules from publically available modules in CloudV.

• Design Entry: browser-based Verilog HDL Editor and Finite State Machine Editor.

• FSM Compilation: compiles FSM diagrams into Verilog HDL.

• Design Simulation: simulates Verilog designs (RTL or gate-level) and display the generated waveforms on the browser.

• Automatic Test Bench Generation: automatically generates a skeleton for a test bench given a Verilog module.

• Design Synthesis and ASIC Technology Mapping: Submits a synthesis job to the cloud then displays the result gate level net list as well as synthesis reports.

Each CloudV user has cloud storage to store her/his design files. The design files are private to each user and are associated with the user’s account. Files can be shared between users to enable collaboration in joint projects. This way, a student can use CloudV, virtually, anytime and anywhere without the need of special hardware or software installations.

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Figure 3. CloudV Verilog HDL Editor

Figure 4. FSMEdit and FSM to Verilog RTL Compiler

A. Design Entry A student can describe the digital system using a full-

featured Verilog HDL editor (shown in Figure 3) that supports syntax highlighting and auto-completion. The student can work on multiple files concurrently and navigate among them easily. The editor has a utility that can check and highlight the Verilog code for syntactical and semantic errors.

Also, CloudV incorporates a graphical editor (FSMEdit) that captures FSM diagrams. The captured FSM diagrams may be translated into Verilog RTL. Figure 4 shows FSMEdit and the FSM to Verilog compiler in action.

Figure 5. FlexWave Waveform Viewer

Figure 6. Synthesis and Technology Mapping

B. Verilog HDL Simulation The captured models, by the Verilog editor or the FSM

editor, may be simulated to verify the functionality. To help in verification, CloudV has an integrated utility that generates a testbench skeleton for the selected Verilog module. The simulation is done at the backend using the open source Verilog simulator “iverilog” [10]. The simulation results (console output and/or VCD data) are communicated back to the student’s browser. The VCD data can be presented to the student, on the web browser, using our homegrown FlexWave waveform viewer, which is integrated into CloudV frontend. FlexWave supports powerful features such as zooming, panning, signals searching, sorting and adding/deleting. The waveform viewer is shown on Figure 5.

C. Synthesis and ASIC Technology Mapping After verification, the student may synthesize and

technology-map the RTL models. For this, CloudV relies on Yosys — the open framework for Verilog RTL synthesis [11]. Currently, the technology mapping is done for ASIC only using free standard cell libraries provided by the VLSI Architecture Research Group at the Oklahoma State University [12]. To synthesize, the user has to specify the top-level Verilog module and the target technology. The user may set options such as flattening the design (Figure 6).

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Figure 7. Interactive Timing Report Viewer

The synthesis and mapping are done at the backend side of CloudV. The resultant mapped gate level netlist is analyzed and a detailed timing report is generated. The gate level netlist and the design reports are sent back to the frontend and can be viewed by the user using an interactive timing report viewer (Figure 7).

III. EXTENDING CLOUDV At the moment, CloudV is complete for ASIC frontend

design steps: design capturing, simulation, RTL synthesis, technology mapping and pre-layout timing analysis. Currently, we are working on extending CloudV beyond this, to cover the ASIC backend (physical implementation) steps: floor-planning, cells placement, Clock Tree Synthesis (CTS), routing, extraction, physical verification, post-layout static timing analysis and chip assembly. For that, we are exploring the possibilities of using parts of QFlow [18] or Coriolis [19] and mix them with homegrown tools.

Also, we have plans to add support for FPGA synthesis as another implementation technology. For this, we are considering integrating IceStorm, the open source FPGA design tools chain [17] and/or Verilog to Routing (VTR) [14] into CloudV. Finally, we have plans to integrate more ASIC standard cell libraries and fabricate test chip(s) to validate CloudV.

IV. CONCLUSIONS A cloud-based environment, CloudV, for teaching ASIC

and FPGA based digital systems design, is presented. CloudV eliminates the complexities associated with adopting commercial EDA tools in education. CloudV is designed to enable blended learning and to enhance the quality of learning/teaching experience. With CloudV, students can focus on learning digital design skills instead of spending their time learning how to use new complex tools. It also enables collaborative design workspaces. Currently, CloudV covers, almost, all the ASIC design frontend steps. We plan to extend CloudV to cover all the frontend and backend steps needed for FPGA and ASIC design.

V. ACKNOWLEDGMENT This work is partially supported by a Teaching and

Learning Enhancement Support Grant (TLE) grant from the

American University in Cairo (AUC). We thank Ahmed Agiza, CloudV main web developer, for his great contributions to the project.

CloudV is free and open to everyone. It can be accessed at http://www.cloudv.io

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