class notes digital lec14

8/7/2019 Class Notes Digital Lec14

http://slidepdf.com/reader/full/class-notes-digital-lec14 1/4

July 27, 2010

`~ivjvcbx twc,G,we,G·, 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq XvKv-1000, evsjv‡`k

Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: [email protected]

Ref. No............................ Dated, the………………………….

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Programmable Logic Array: A programmable logic array device enables logic functions expressed in sum-of-products form to be implementeddirectly. It has a programmable AND gate array at the input and a programmable OR gate array at the output. Eachof the product terms of the given Boolean function is generated by an AND gate which can be programmed to formthe AND of any subset of inputs or their complements. The product terms so produced can be summed up in an arrayof programmable OR gates.The number of AND gates for n input variables is usually much less than 2 n, and the number of inputs of each of theOR gates equals the number of AND gates. Each OR gate can generate an arbitrary Boolean function with amaximum of minterms equal to the number of AND gates.Figure shows the internal architecture of a PLA device with four input lines, eight product lines and four output lines.

The programmable AND gate array has eight AND gates. Each of the AND gates has eight inputs, corresponding tofour input variables and their complements. The input of each of the AND gates can be programmed to be any of thepossible 16 combinations of four input variables and their complement.Four OR gates at the output can generate four different Boolean functions, each having a maximum of eightminterms out of 16 minterms possible with four variables.PLAs usually have inverters at the output of OR gates to enable them to implement a given Boolean function in either AND-OR or AND-OR-INVERT form.

Fig.: Internal structure of a PLA device.A PLA device having n inputs (number of input variables), m outputs (number of OR gates) and k product terms(number of AND gates) –

(I) the number of inputs to each OR gate is k,

A B C D

Programmable OR-array

Y1 Y2 Y3 Y4

Programmable AND-array

Lec-14, Pg-01



July 27, 2010

`~ivjvcbx twc,G,we,G·, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the………………………….


(II) the number of inputs to each AND gate is 2n and(III) total number of programmable interconnections is 2kn+km.

While implementing a given Boolean function with a PLA, it is important that each expression is simplified to aminimum number of product terms which would minimize the number of AND gates required for the purpose. Sinceall input variables are available to different AND gates, simplification of Boolean functions to reduce the number of literals in various product terms is not important.A PLA could be either –

(I) Mask programmable – the customer submits a program table to the manufacturer to produce a custom-madePLA having the desired internal paths between inputs and outputs.(II) Field programmable – FPLA is programmed by the users themselves by means of a hardware programmer unit available commercially.

Example: We have two two-bit binary numbers A1A0 and B1B0. Design a PLA device to implement a magnitude comparator toproduce outputs for A1A0 being equal to, not equal to, less than and greater than B1B0.Solution: Table shows the function with inputs and desired outputs.

A1 A0 B1 B0 O/P-1 O/P-2 O/P-3 O/P-4

0 0 0 0 1 0 0 00 0 0 1 0 1 1 00 0 1 0 0 1 1 00 0 1 1 0 1 1 0

0 1 0 0 0 1 0 10 1 0 1 1 0 0 00 1 1 0 0 1 1 00 1 1 1 0 1 1 01 0 0 0 0 1 0 11 0 0 1 0 1 0 11 0 1 0 1 0 0 01 0 1 1 0 1 1 01 1 0 0 0 1 0 11 1 0 1 0 1 0 11 1 1 0 0 1 0 11 1 1 1 1 0 0 0

The Boolean expressions for the desired outputs are given in the following equations –Output-1 (equal to) =

0101010101010101 ............ BBAABBAABBAABBAA +++

Output-2 (not equal to) =

01010101010101010101

0101010101010101010101010101

...............

.....................

BBAABBAABBAABBAABBAA

BBAABBAABBAABBAABBAABBAABBAA

+++++

++++++

Output-3 (less than) =

010101010101010101010101 .................. BBAABBAABBAABBAABBAABBAA +++++

Lec-14, Pg-02



July 27, 2010

`~ivjvcbx twc,G,we,G·, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the………………………….


Output-4 (greater than) =

010101010101010101010101 .................. BBAABBAABBAABBAABBAABBAA +++++

Fig.: Karnaugh maps.

Fig.: Programmed PLA device.

1

1

1

1

0 0 0

0 0

0 0

0 00

0

0

00

00

01 11 10

01

11

10

A1A0

B1B0

0

0

0

0

1 1 1

1 1

1 1

1 11

1

1

00

00

01 11 10

01

11

10

A1A0

B1B0

0

0

0

0

0 0 0

0 0

1 1

1 01

1

1

00

00

01 11 10

01

11

10

A1A0

B1B0

0

0

0

0

1 1 1

1 1

0 0

0 10

0

0

00

00

01 11 10

01

11

10

A1A0

B1B0

A1 A0 B1 B0

Programmable OR-array

O/P-1 O/P-2 O/P-3 O/P-4

Programmable AND-array

Lec-14, Pg-03



July 27, 2010

`~ivjvcbx twc,G,we,G·, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the………………………….

In case of any query or suggestion please contact Sazzad Lecturer APECE DU (url: sazzadmsi webs com)

Figures show the Karnaugh maps for the four outputs. The minimized Boolean expression can be written from theKarnaugh maps as follows.

Output-1 (equal to) = 0101010101010101 ............ BBAABBAABBAABBAA +++

Output-2 (not equal to) = 00001111 .... BABABABA +++

Output-3 (less than) = 01000111 ..... BBABAABA ++

Output-4 (greater than) = 01000111 ..... BBABAABA ++

Figure below the K-maps shows the programmed PLA device where an unprogrammed interconnection indicated bya cross (x) is a make connection.[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

Lec-14, Pg-04

class notes digital lec14

Documents