class notes digital lec13

8/7/2019 Class Notes Digital Lec13

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Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: [email protected]

Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

t3: CAS goes LOW to load the column address into the DRAM.t4: The DRAM responds by placing valid data from the selected memory cell onto the DATA OUT line.

t5: MUX, RAS , CAS and DATA OUT return to their initial states.Write Cycle

Fig.: Signal activity for a write operation on a dynamic RAM.The sequence of events during write operation is

t0: The LOW at MUX places the row address at the DRAM inputs.

t1: The NGT at RAS loads the row address into the DRAM.t2: MUX goes HIGH to place the column address at the DRAM inputs.

t3: The NGT at CAS loads the column address into the DRAM.t4: Data to be written are placed on the DATA IN line.

t5: R/W is pulsed LOW to write the data into the selected cell.

t6: Input data are removed from DATA IN.t7: MUX, RAS , CAS and R/W are returned to their initial states.

Expanding Word Size:When a given application requires a RAM or ROM with a capacity that is larger than what is available on a singlechip, more than one such chip can be used to achieve that objective. The required enhancement in capacity could beeither in terms of

(I) increasing the word size, or(II) increasing the number of memory locations.

DATA OUTData

valid

01 2 3 4

5

ROW COLUMN

Hi-Z

Address

CAS

RAS

MUX

6 7

WR /

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Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


Fig.: Combining two 16x4 RAMs for a 16x8 module.Figure shows the configuration how two 16x4 memory chips with common I/O lines can be combined to produce amemory that can store 16 eight-bit words.RAM-0 stores the four higher-order bits of each of the 16 words, and RAM-1 stores the four lower-order bits of eachof the 16 words. A full eight-bit word is available at the RAM outputs connected to the data bus.Any one of the 16 words is selected by applying the appropriate address code to the four-line address bus (AB3, AB2,AB1, AB0). Since the address inputs are common, the same location in each chip is accessed at the same time.

To read, first the address is selected and then R/W must be high and CS must be low. This causes RAM I/O linesto act as outputs. RAM-0 places its selected four-bit word on the upper four data bus lines and RAM-1 places itsselected four-bit word on the lower four data bus l ines. The data bus then contains the full selected eight-bit word,which can now be transmitted to some other device.

Expanding Memory Location:Figure shows how to produce a memory that can store 32 four-bit words by combining two 16x4 memory chips. EachRAM is used to store 16 four-bit words. The four data I/O pins of each RAM are connected to a common four-linedata bus. Only one of the RAM chips can be selected at one time so that there will be no bus-contention problems.Since the total capacity of this memory module is 32x4, there must be five address input lines. The MSB address bit

AB4 feeds the CS input of one chip directly and the CS input of other chip after inversion. This is used to selectone RAM or the other as the one that will be read from or written into. Four of the five address inputs AB 0 to AB3,other than the MSB address bit, are common to both 16x4 chips. They are used to select the one memory locationout of 16 from the selected RAM chip.

AB3

AB2

AB1

AB0

WR /

CS

CS

WR /

CS

WR /

Address

bus

Data

bus

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

A3 A2 A1 A0 A3 A2 A1 A0

I/O3 I/O2 I/O1 I/O0 I/O3 I/O2 I/O1 I/O0

RAM-016x4

RAM-116x4

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Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


Fig.: Combining two 16x4 chips for a 32x4 memory.

When AB4=0, the CS of RAM-0 enables this chip for read or write. Then any address location in RAM-0 can be

accessed by AB3 through AB0. Thus the range of addresses representing locations in RAM-0 is AB4AB3AB2AB1AB0 = 00000 to 01111.

The CS of RAM-1 is high, so that its I/O lines are disabled and cannot communicate with the data bus.When AB4=1, it enables RAM-1 for read or write and disables RAM-0. Then any address location in RAM-1 can beaccessed by AB3 through AB0. Thus the range of addresses representing locations in RAM-1 is

AB4AB3AB2AB1AB0 = 10000 to 11111.[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Fixed Logic Versus Programmable Logic:Three important classes of devices used to build digital electronics systems are

(I) Memory devices used to store information such as the software instructions of a program or the contents ofa database.(II) Microprocessors execute software instructions to perform a variety of functions.(III) Logic devices implement device-to-device interfacing, data timing, control and display operations etc.

There are two broad categories of logic devices (1) Fixed logic devices and(2) Programmable logic devices.

(1) Fixed Logic Devices:A fixed logic device performs a given logic function that is known at the time of device manufacture.The circuits or building blocks and their interconnections in a fixed logic device are permanent and cannot be alteredafter the device is manufactured.Logic gates, multiplexers, demultiplexers, arithmetic circuits, flip-flops, counters, registers etc. are some examples offixed logic devices.

AB3

AB2

AB1

AB0

WR /

CS

WR /

CS

WR /

Addressbus

Data

bus

AB4

DB3

DB2

DB1

DB0

A3 A2 A1 A0 A3 A2 A1 A0

I/O3 I/O2 I/O1 I/O0 I/O3 I/O2 I/O1 I/O0

RAM-016x4 RAM-116x4

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Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


Fig.: Fixed logic circuit.Figure shows a simple logic circuit comprising four three-input AND gates and a four-input OR gate.This circuit produces an output that is the sum output of a full adder. Here, A and B are the two bits to be added andC is the carry-in bit.It is a fixed logic device as the circuit is unalterable from outside owing to fixed interconnections between the variousbuilding blocks.(2) Programmable Logic Devices:

Fig.: Simple programmable logic circuit.

Y

ABC

ABC

ABC

AB

C

Y

A

B

C

+V

+V

+V

+V

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Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

The function to be performed by a programmable logic device is undefined at the time of its manufacture.These devices can be configured by the user to perform a large variety of logic functions.It offers to the user a wide range of logic capacity which can be configured by the user to perform the intendedfunction or set of functions. This configuration can be modified or altered any number of times by the user byreprogramming the device.Figure shows the logic diagram of a simple programmable device.The device has an array of four six-input AND gates at the input and a four-input OR gate at the output. Each ANDgate can handle three variables A, B and C. The three variables or their complements can be programmed to appearat the inputs of any of the four AND gates through antifuses. Thus each AND gate can produce the desired three-variable product term.Thus the circuit could be programmed to produce the sum output resulting from the addition of three bits or toproduce difference outputs resulting from subtraction of two bits with a borrow-in.[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

class notes digital lec13

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