class notes digital lec10

8/7/2019 Class Notes Digital Lec10

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July 11, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980

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Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: [email protected]

Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Mask-Programmed ROM:The mask-programmed ROM has its storage locations written into by the manufacturer according to the customersspecifications. It cannot be reprogrammed in the event of a design change requiring a modification of the stored data.The ROM would have to be replaced by a new one with the desired data written into it.

Fig.: Structure of a MOS MROM.Figure shows the structure of a small MOS MROM. It consists of 16 memory cells arranged in four rows of four cells.Each cell is an N-channel MOSFET transistor connected in the common-drain configuration. Each row of cells

constitutes a four-bit register.Any transistor that has a connection from the source to the output column line can switch V dd onto the column,making it a HIGH logic level, representing a data 1. If the source connection is absent then V dd is not connected tothe column line, the output will be held at a LOW logic level by the pull-down resistor, representing a data 0. Thecondition of each source connection is controlled during production by the photographic mask based on thecustomer-supplied data.The 1-of-4 decoder is used to decode the address inputs A 1A0 to select which row/register is to have its data read.The decoders active-HIGH outputs provide the ROW enable lines that are the gate inputs for the various rows of

cells. If the decoders enable input, EN , is held HIGH, all of the decoder outputs will be in their inactive LOW state,and all of the transistors in the array will be off because of the absence of any gate voltage. For this situation, thedata outputs will all be in the LOW state.

1-of-4decoder

0

1

2

3

A1

A0

EN

Row 0

Row 1

Row 2

Row 3

Q0

Q4

Q8

Q12

Q1

Q5

Q9

Q13

Q2

Q6

Q10

Q14

Q3

Q7

Q11

Q15

Q3 Q2 Q1 Q0

+Vdd

Address Data

A1 A0 D3 D2 D1 D00 0 1 0 1 00 1 1 0 0 11 0 1 1 1 01 1 0 1 1 1

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July 11, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


When EN is in its active LOW state, the conditions at the address inputs determine which row/register will beenabled so that its data can be read at the data outputs.For example, to read ROW 0, the A1A0 inputs are set to 00. This places HIGH at the ROW 0 lines, all other row linesare at 0V. This HIGH at ROW 0 turns on transistors Q0, Q1, Q2 and Q3. With all of the transistors in the rowconducting, Vdd will be switched on to each transistors source lead. Outputs D 3 and D1 will go HIGH, since Q0 and Q2are connected to their respective columns. D2 and D0 will remain LOW because there is no path from the Q 1 and Q3source leads to their columns.In a similar manner, application of the other address codes will produce data outputs from the corresponding register.

Programmable ROMs:

A mask-programmable ROM is very expensive and would not used except in high-volume applications, where thecost would be spread out over many units. For lower-volume applications, fusible-link PROMs are used. These areuser-programmable, that is, they are not programmed during the manufacturing process but are custom-programmedby the user. Once programmed, however, it cannot be erased and reprogrammed.In a PROM each of the connections from the MOSFET source lead to the output column is made with a thin fuse linkthat comes intact from the manufacturer. The user can selectively blow any of these fuse links to produce the desiredstored memory data.A data value is programmed or burned-into an address location by

(I) applying the address to the address inputs,(II) placing the desired data at the data pins and then(III) applying VPP, a high-voltage pulse of 10-30V, to a special programming pin on the IC.

Fig.: Basic memory cell of a PROM.

Figure shows the programming operation in a PROM. All of the transistors in the selected row are turned on and VPPis applied to their drain leads. Those columns/data lines that have a logic 0 on them will provide a high-current paththrough the fusible link, burning it open and permanently storing a logic 0.Those columns that have a logic 1 have VPP on one side of the fuse and Vdd on the other side, drawing much lesscurrent and leaving the fuse intact.Once all address locations have been programmed in this manner, the data are permanently stored in the PROM andcan be read over and over again by accessing the appropriate address. The data will not change when power isremoved from the PROM chip.The process of programming a PROM and verifying that the stored data are correct is done automatically by aspecial apparatus called a PROM programmer. The data to be burned into the PROM are input to the programmerfrom a keyboard or from a disk drive, or they are transferred from a computer.

+Vdd/Vpp

Q0

Fusiblelink

Vdd1

+Vdd/Vpp

Q1

Meltingfuse

0V0

High current

Row 0

Data lines (columns)

Stored data

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`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


Erasable Programmable ROM:An EPROM can be programmed by the user, and it can also be erased and reprogrammed as often as desired. Onceprogrammed, the EPROM is a nonvolatile memory that will hold its stored data indefinitely.The storage cells in an EPROM are MOS transistors with a silicon gate that has no electrical connections, i.e., afloating gate. In its normal state, each transistor is off and each cell is storing a logic 1. A transistor can be turned onby the application of a high-voltage programming pulse that injects high-energy electrons into the floating-gate region.These electrons remain trapped in this region once the pulse is terminated, since there is no discharge path. Thiskeeps the transistor on permanently even when power is removed from the device, and the cell is now storing a logic0.Once an EPROM cell has been programmed, it can be erased by exposing it to UV light applied through a window onthe chip package. The UV light produces a photocurrent from the floating gate back to the silicon substrate, therebyremoving the stored charges, turning the transistor off and restoring the cell to the logic 1 state. The UV light erasesall cells at the same time so that an erased EPROM stores all 1s. Once erased, the EPROM can be reprogrammed.

Fig.: Logic symbol and operating modes for 2764 EPROM.The 2764 is an 8Kx8 CMOS EPROM that operates from a single +5V power source during normal operation. It has

13 address inputs since 213=8192 and 8 data outputs. It has several operating modes that are controlled by thefollowing four control inputs

(I) CE is the chip enable input that is used to place the device in a standby mode where its power consumptionis reduced.

(II) OE is the output enable and is used to control the devices data output tristate buffers so that the devicecan be connected to a microprocessor data bus without bus contention.(III) VPP is the special programming voltage required during the programming process.

(IV) PGM is the program enable input that is activated to store data at the selected address.It has a characteristic window which allows the internal circuitry to be exposed to UV light when the complete memorycontents are to be erased. A sticker is placed over the window after erasure and reprogramming to protect againstaccidental erasure from ambient light.

EPROM

8Kx8

27C64

D7

D6

D5

D4

D3

D2

D1

D0

Addressinputs

Controlinputs

Data

outputs

---

+VCC +VPP

A12

A11

A1

A0

OE

CE

PGM

Inputs Outputs

ModeCE

OE

PGM

VPP D7-D0

Read 0 0 1 0-5V DATAoutOutputDisable

0 1 1 0-5V High Z

Standby 1 X X X High Z

Program 0 1 0 12.75V DATAinPGMVerify

0 0 1 12.75V DATAout

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July 11, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad Lecturer APECE DU (url: sazzadmsi webs com)

The programming process writes one eight-bit word into one address location at one time as follows (I) the address is applied to the address pins,(II) the desired data are placed at the data pins, which function as inputs during the programming process,(III) a higher programming voltage of 12.75V is applied to V PP,

(IV) CE is held LOW and

(V) PGM is pulsed LOW for 100s and the data are read back.This process is repeated for all memory locations.Some of the drawbacks of EPROMs include

(I) they must be removed from their circuit to be erased and reprogrammed,(II) the erase operation erases the entire chip, there is no way to select only certain addresses to be erased and

(III) the erase and reprogramming process can typically take 20 minutes or more.[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Lec-10, Pg-04

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