class notes digital lec07

8/7/2019 Class Notes Digital Lec07

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May 30, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980

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Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: [email protected]

Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Flash A/D Converter:The flash converter is based on using a number of comparators and the highest-speed ADC available, but it requiresmuch more circuitry than the other types. The number of comparators needed for n-bit A/D conversion is 2n-1.To understand the principle of operation of flash ADC, a three-bit flash converter is used in order to keep the circuitryat a workable level.

Priorityencoder

Fig.: Three-bit flash ADC circuitry and truth table.The three-bit flash converter uses seven comparators and the comparators are fed into an active-LOW priorityencoder that generates a binary output corresponding to the highest-numbered comparator output that is LOW.

The converter has a three-bit resolution and a step size of 1V. The analog signal, VA, to be digitized serves as one ofthe inputs to each of the comparators.The second input for each of the comparators is a reference input. The voltage divider sets up reference levels foreach comparator so that there are seven levels corresponding to 1V, 2V, 3V, . . ., and 7V. In general, the referencevoltages to be used for comparators are V/2n, 2V/2n, 3V/2n and so on, where V is the maximum amplitude of theanalog signal that the A/D converter can digitize and n is the number of bits in the digitized output.The output status of various comparators depends upon the input analog signal V A. For instance, with VA7V

10

000000

11

000000

11

100000

11

110000

11

111000

11

111100

11

111110

00

001111

00

110011

01

010101

+10V

1k

1k

1k

1k

1k

1k

1k

3k

7V

6V

5V.

4V.

3V.

2V

1V.

C7.

C6.

C5

C4.

C3.

C2.

C1

I7

I6.

I5.

I4.

I3.

I2.

I1.

Analog input, VA

A.

B.

C.

MSB.

Digitaloutput

Lec-07, Pg-01


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May 30, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

When VA is greater than 7V, C1 to C7 will all be LOW and the encoder will produce CBA=111 as the digital equivalentof VA.The flash ADC, described here, has a resolution of 1V because the analog input must change by 1V in order to bringthe digital output to its next step. To achieve finer resolutions, the number of input voltage levels and the number ofcomparators must be increased.The conversion time is the time it takes for a new digital output to appear in response to a change in analog input andit depends only on the propagation delays of the comparators and encoder logic. For this reason, flash convertershave extremely short conversion times.

Digital Voltmeter:A digital voltmeter converts an analog voltage to its BCD-code representation, which is then decoded and displayedon some type of readout. Figure shows a three-digit DVM circuit that uses a digital-ramp ADC

Fig.: Continuous-conversion DVM using a digital-ramp ADC.Three cascaded BCD counters provide the inputs to a three-digit BCD-to-analog converter that has a step size of10mV and a full-scale output of 9.99V. Each BCD counter stage also drives a four-bit register that feeds a

Decoder/driverand display

4-bitregister

BCD counter(MSD)


4-bitregister

BCD counter


4-bitregister

BCD counter(LSD)

BCD- o-Analog converter

F.S.=9.99V

Clock

COMP-

+

VAX

Analog inputVA

VT=0.1mV

TOS1

Q1

1Q

TOS2

Q2

2Q

To RESETinputs ofcounters

Lec-07, Pg-02


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May 30, 2010

`~ivjvcbx twc,G,we,G, 9661920-73/4980


Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad Lecturer APECE DU (url: sazzadmsi webs com)

decoder/driver and a display. The contents of the BCD counters are transferred to the registers at the end of eachconversion cycle, so that the displays do not show the counters resetting and counting, but only the final count thatrepresents the unknown voltage.

Fig.: Waveform for a DVM.As long as VAX

class notes digital lec07

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