May 25, 2010

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Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: APECE@univdhaka.edu

Ref. No............................ Dated, the………………………….

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Digital-Ramp A/D Converter: An A/D converter takes at its input an analog voltage and after a certain amount of time produces a digital output code representing the analog input.

Fig.: Digital-ramp analog-to-digital converter. Figure shows the general block diagram for a digital-ramp ADC, also known as counter-type ADC, that utilizes a DAC as part of their circuitry. The timing for the operation is provided by the input clock signal. The control AND gate is used for generating the proper sequence of operations in response to the START command, which initiates the conversion process. The op-amp comparator has two analog inputs and a digital output that serves as the active-LOW end-of-conversion

signal EOC . It uses a binary counter and allows the clock to increment the counter one step at a time. If the analog voltage VA, that is to be converted, is positive, the operation proceeds as follows –

(1) A START pulse is applied to reset the counter to 0. The HIGH at START also inhibits clock pulses from passing through the AND gate into the counter. (2) With all 0s at its input, the DAC’s output will be VAX=0V.

(3) Since VA>VAX, the comparator output, EOC , will be HIGH. (4) When START returns LOW, the AND gate is enabled and clock pulses get through to the counter. (5) As the counter advances, the DAC output, VAX, increases one step at a time.

(6) This continues until VAX reaches a step that just exceeds VA. At this point, EOC will go LOW and inhibit the flow of pulses into the counter, and the counter will stop counting.

(7) The conversion process is now complete as signaled by the HIGH-to-LOW transition at EOC , and the contents of the counter are the digital representation of VA. (8) The counter will hold the digital value until the next START pulse initiates a new conversion.

The counter-type A/D converter provides a very good method for digitizing to a high resolution. An unavoidable source of error in the digital-ramp method is that the step size or resolution of the internal DAC is the smallest unit of measure. The output voltage VAX is a staircase waveform that goes up in discrete steps until it exceeds the input voltage, VA. By making the step size smaller, the potential error can be reduced, but there will

VA

VAX

+ -

Comparator

Op-amp EOC

D/A

converter Counter

RESET

CLOCK

Digital result

Start

Clock

START

VA

VAX

tC

Comparison complete, counter stops counting

Time

EOC

Lec-06, Pg-01

May 25, 2010

`~ivjvcbx t wc,G,we,G·, 9661920-73/4980 dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq XvKv-1000, evsjv‡`k

Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: APECE@univdhaka.edu

Ref. No............................ Dated, the………………………….

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

always be a difference between the actual/analog quantity and the digital value assigned to it. This is called quantization error. The counter always begins from the all 0s position and counts through its normal binary sequence up until VAX exceeds VA. That is, the conversion time depends on VA, a larger value will require more steps. The maximum conversion time will occur when VA is just below full scale. For an N-bit converter this will be –

tC(max)=(2N-1) clock cycles The average conversion time is half of the maximum conversion time and for the digital-ramp converter this would be

122

(max))( −

≈=NC

C

tavgt clock cycles.

The major disadvantages of the digital-ramp method is that conversion time essentially doubles for each bit that is added to the counter, so that resolution can be improved only at the cost of a longer tC. This makes the counter-type A/D converter unsuitable for digitizing rapidly changing analog signals. Successive Approximation ADC:

Fig.: Successive-approximation ADC – simplified block diagram and flowchart of operation. Here the control logic modifies the contents of the register bit by bit until the register data are the digital equivalent of the analog input within the resolution of the converter. The process of A/D conversion by this technique can be illustrated by taking a four-bit successive approximation type A/D converter as an example.

Analog

input

VA VAX

VAX

START

EOC

Clock

Control

logic

Control register

MSB LSB

DAC

START

Clear all bits

Start at MSB

Set bit = 1

Is VAX>VA ?

Clear bit

back to 0

Have all bits been checked?

Go to next lower bit

Conversion is complete and result is in REGISTER

END

Yes

Yes

No

No

Lec-06, Pg-02

May 25, 2010

`~ivjvcbx t wc,G,we,G·, 9661920-73/4980 dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq XvKv-1000, evsjv‡`k

Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: APECE@univdhaka.edu

Ref. No............................ Dated, the………………………….

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Fig.: Illustration of four-bit SAC operation using DAC step size of 1V and VA=10.4V. The DAC have weights of Q3=8, Q2=4, Q1=2 and Q0=1V, respectively. Let’s assume that the analog input VA=10.4V. At t=t0, the operation begins with the control logic clearing all of the register bits to 0 so that [Q]=0000. This makes the DAC output VAX=0. With VAX<VA, the comparator output is HIGH. At t=t1, the control logic sets the MSB of the register to 1 so that [Q]=1000. This produces VAX=8V. Since VAX<VA, the COMP output is still HIGH. This HIGH tells the control logic that the setting of the MSB did not make VAX exceed VA, so that the MSB is kept at 1. AT t=t2, the control logic proceeds to the next lower bit Q2 and sets it to 1 to produce [Q]=1100 and VAX=12V. Since VAX>VA, the COMP output goes LOW. This LOW signals the control logic that the value of VAX is too large, and at t=t3 the control logic clears Q2 back to 0. The register contents are back to 1000 and VAX is back to 8V. At t=t4, the control logic sets the next lower bit Q1 so that [Q]=1010 and VAX=10V. With VAX<VA, COMP is HIGH and tells the control logic to keep Q1 set at 1. At t=t5, the control logic sets the next lower bit Q0 so that [Q]=1011 and VAX=11V. Since VAX>VA, COMP goes LOW to signal that VAX is too large, and at t=t6, the control logic clears Q0 back to 0. The register contents are back to 1010 and VAX to 10V. At this point, all of the register bits have been processed, the conversion completes and the control logic activates its EOC output to signal that the digital equivalent of VA is now in the register. The successive approximation ADC has more complex circuitry than the digital-ramp ADC but a much shorter conversion time. In addition, it has a fixed value of conversion time that is not dependent on the value of the analog input. In general, the number of clock cycles required for each conversion will be n for an n-bit A/D converter. [Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Volts

Time

12 11 10 9 8

0 t0 t1 t2 t3 t4 t5 t6

Conversion

completed

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

1111

1101

1011

1001

0111

0101

0011

0001

1110

1010

0110

0010

1100

0100

1000 0000

Lec-06, Pg-03