Joseph A. Elias, PhD 1

Class 05: Device Physics II

Topics:1. Introduction2. NFET Model and Cross Section with Parasitics 3. NFET as a Capacitor 4. Capacitance vs. Voltage Curves 5. NFET as a Capacitor - Band Diagrams at V=0 6. NFET as a Capacitor - Accumulation V<0 7. NFET as a Capacitor - Depletion V>0 8. NFET as a Capacitor - Inversion V>>0 9. Band Diagrams, Charges, E-Field, and Potential10. Band Diagrams at various biasing11. Depletion Layer Width vs. Substrate Doping12. NFET Cross Section, Parasitics, and Biasing 13. Full CV Curve for reference

Joseph A. Elias, PhD 2

Class 05: Device Physics II

•Goal is to understand the parasitic regions and terms shown in the model and cross section•Last lecture covered the pn junctions of the source and drain•This lecture will cover the channel•Question - where is the biggest capacitor?

NFET Model and Cross Section with Parasitics (Martin p.101)

Joseph A. Elias, PhD 3

Class 05: Device Physics IINFET as a Capacitor (Martin p.87, Singh p.418)

•The channel region of an FET can be thought of as a series connectionof capacitors, the capacitance due to the thin oxide, and the capacitance due tothe semiconductor.•The thin oxide capacitance is fixed.•The semiconductor capacitance depends on the biasing

Joseph A. Elias, PhD 4

Class 05: Device Physics IICapacitance vs. Voltage Curves (Singh p.419)

•Much like IV curves define a transistor, CV curves define capacitors•Three regions of importance: (1) accumulation (2) depletion (3) inversion•Further foils will describe each of these regions•Once again, this is the channel region of a transistor and how it behaves when biased•To obtain a CV curve, one biases the top plate with a DC bias, and uses an AC signalto determine the response of the carriers at the surface to the AC signal. So fromI=C dv/dt, one can back out the capacitance based on the measured current

Joseph A. Elias, PhD 5

Class 05: Device Physics IINFET as a Capacitor - Band Diagrams at V=0 (Sze p.427)

This state is referred to as the “flat-band”conditionthat is, no applied potential, the bands are flat in the idealcase. So why is Vfb not at Vg=0 in the CV plot below?

Important terms to take from these diagrams are:d insulator thicknessqΨB Energy of offset between Fermi and intrinsic levels

Important observations to make:•How can you tell from the band diagram which is n-type andwhich is p-type semiconductor?•Even the oxide has bands of allowed states, it is just thatthe band gap is very large•This portion of CV curve referred to as the flat band capacitance

Joseph A. Elias, PhD 6

Class 05: Device Physics IINFET as a Capacitor - Accumulation V<0 (Sze p.428; Martin p.89; Mason)

This state is referred to as the “accumulation”conditionthat is, where the majority carriers are accumulated at the surface

Important observations to make:•With a parallel plate analogy, this is where the total capacitanceis due to the Cox and Cs is zero

Accumulation: In accumulation, charges are separated bythe gate oxide so we can write the gate capacitance per unit area as

CG = COX = εOX / tOX

where εOX is the permittivity of the oxide (= 3.9 ε0), and tOX

is the thickness of the oxide.The total capacitance would be multiplied by the area of the

gate which is the product of the width, W, and length, L, of thegate (A=W*L).

Joseph A. Elias, PhD 7

Class 05: Device Physics IINFET as a Capacitor - Depletion V>0 (Sze p.428; Martin p.89)

This state is referred to as the “depletion”condition because themajority carrier are depleted from the surface

Important observations to make:•With a parallel plate analogy, this is where the thickness of the Cs plateis increasing, due to the increase in the depletion regions.•Thus the capacitance is going down.

•CG = COX Cdep / (COX + Cdep) < COX

Joseph A. Elias, PhD 8

Class 05: Device Physics IINFET as a Capacitor - Inversion V>>0 (Sze p.428; Martin p.89)

This state is referred to as the “inversion”condition because theminority carriers are brought to the surface of the channel. However,minority carrier respond slower to the AC signal (minoritycarrier lifetimes). Thus inversion in a CV curve is only obtainedwith very slow varying signals.

Important observations to make:•With a parallel plate analogy, this is where the thickness of the Cs plateis at its maximum.•During normal operation of a transistor, the carriers are suppliedby the source and drain, so there is no lack of carriers.•The definition of inversion is where surface potential > bulk potential•Vt is defined as the condition in which the surface is inverted, based on Cmin

Joseph A. Elias, PhD 9

Class 05: Device Physics IIBand Diagrams, Charges, E-Field, and Potential (Sze p.434)

Spice model parameterPHI is 2Ψs

Joseph A. Elias, PhD 10

Class 05: Device Physics IIBand Diagrams at various biasing (Sze p.430)

Joseph A. Elias, PhD 11

Class 05: Device Physics IIDepletion Layer Width vs. Substrate Doping (Sze p.437)

Joseph A. Elias, PhD 12

Class 05: Device Physics IINFET Cross Section, Parasitics, and Biasing (Martin p.101)

•We have covered the source/drain to substrate junctions, and nowthe gate/oxide/surface junction•Next, how they come together for the operation of an NFET

Joseph A. Elias, PhD 13

Class 05: Device Physics IIFull CV Curve for reference (Sze p.438)