chip-aware power integrity - ansys · fgb channel power only vcc vss die current 0 on the left is...

© 2012 ANSYS, Inc. November 14, 2012 1

Chip-Aware Power Integrity

Greg Pitner Isaac Waldron


• Power integrity challenges and solution

• New PI features in R14.5

• Power integrity case study

Agenda


Power Integrity Challenges and Solution


The die-to-die system is extremely complex:

• Silicon driver/receiver • 3D component interconnect • Chip to package • Package to daughter card • Daughter card to backplane • Power delivery network effects

Complex problems • High risk

– New unfamiliar phenomena? • High cost of design errors

Solving them is requiring new strategies and simulation tools.

Trends Requiring Chip Aware System Design

+

-

+

-

Via Via Via

MS SL SLPackage Package Connector Backplane Daughter Card


What is a Power Distribution Network (PDN)?

Complex multi-stage network supplying power to all devices in a system.

PDN Requirements: • Must deliver clean power to the ICs • Must provide low impedance, low noise reference path for signals • Must not contribute excessive EMI

For typical products the PDN includes:

• Voltage regulator module (VRM)

• Board power/ground planes and decoupling capacitors

• Package power/ground planes and decoupling capacitors

• Chip power/ground structures and capacitance


Board Level Power Integrity?

Chip

Package PCB

ΔI Wire Bonding

Package P/G Network

Ball Bonding

PCB P/G Network

VRM

Bulk Capacitor Near VRM

Decoupling Capacitor On PCB

Decoupling Capacitor On Package

Decoupling Capacitor On Chip

Full PDN

Very Low Frequency Current Low Frequency Current Medium Frequency Current High Frequency Current Very High Frequency Current

It’s important to consider the entire PDN when simulating. Interactions between components can cause unexpected results.


Redhawk generates a chip power model (CPM) including chip PDN parasitics and switching currents.

PSI and SIwave provide robust extraction of IC packages and boards with broadband S-parameter models.

PI Advisor optimizes decoupling capacitor selection to meet a target impedance.

Designer SI simulates power noise in the time domain.

ANSYS Chip-Aware PDN Solution

0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_vc

c) [V

]

CPM CurrentU1 VCCCurve Info min max pk2pk avg

V(u1_vcc)NexximTransient 1.4507 1.5489 0.0982 1.4946


Chip Power Model (CPM)


Chip Design

Prototype

Design

Sign-off

Package / PCB Design

Selection, Planning

Package Design

System Sign-off

Chip Power Model

CPS Convergence Using CPM

© 2012 ANSYS, Inc. November 14, 2012 10 10

Each C4 bump (power & ground) will be associated to its corresponding:

Chip PDN RLC Physical model of chip layout Transistor/cell current /cap/ESR Electrical model of chip layout

CPM is topological, physical and activity based

PCB + Package

What’s in a CPM?


Traditional Die Model

RedHawk (SoC)

Layout

Chip Power Model

RLC reduction: billions of parasitics to thousands of Spice elements

Distributed with full couplings

Apache CPM™

Library

Chip

Cur

rent

Ch

ip P

aras

itics

Traditional die model

Single Lumped Model

Benefits of CPM


Traditional Die Model

RedHawk (SoC)

Layout

Chip Power Model

RLC reduction: billions of parasitics to thousands of Spice elements

Distributed with full couplings

Apache CPM™

Library

Chip

Cur

rent

Ch

ip P

aras

itics

Traditional die model

Single Lumped Model

Apache CPM

Benefits of CPM


SIwave CPM integration includes the following:

• Import of die PDN for inclusion in frequency-domain extractions

• Automatic matching of die pin to CPM pin locations

SIwave CPM Integration


SIwave CPM Setup File > Import > Apache CPM/PLOC File menu item. Select Part Name and Reference Designator of target device. Click Auto-Connect.


SIwave CPM Setup You can review the automatic assignments and if necessary adjust the rotation angle before clicking Auto Connect again. Manual connecting of pins is also supported.

Once complete the device footprint will change to indicate that a model has been added to it and you can continue with regular project setup.


CPM Impedance Effect

0.10 1.00 10.00Freq [GHz]

0.10

1.00

10.00

100.00

1000.00

mag

(Z(F

CH

IP_V

DD

_15,

FCH

IP_V

DD

_15)

)

analysis_v2PDN Impedance at DieCurve Info

mag(Z(FCHIP_VDD_15,FCHIP_VDD_15))SYZ Sw eep 1

mag(Z(FCHIP_VDD_15,FCHIP_VDD_15))SYZ Sw eep 2

PKG PKG+CPM

Adding the die power network to this package significantly reduces the impedance over a broad frequency range.


Sentinel PSI


ANSYS Package/Board Solvers

Hybrid full-wave 3D full-wave

SIwave Sentinel-PSI

• Fast FEM using prism elements • Tailored for PI package analysis

• FAST Hybrid method for PKG/BRD • Handles many, but not all 3D effects

Fast Trade-off speed for 3D accuracy

SPEED


• Package/PCB structures containing: – Highly perforated metal planes

• Swiss Cheese PWR/GND planes • Hatched PWR/GND planes

– Two layer PCBs without reference layers – Transmission lines over non-ideal ground – Ports with unreferenced terminals – Visualization of PWR/GND AC currents – Vias with large anti-pads

Sentinel PSI Strengths


PI Advisor is an addon for Siwave that automatically optimizes capacitor selection to meet a target impedance:

Inputs:

• Capacitor locations

• Candidate capacitors

Outputs:

• Capacitor schemes that indicate which candidate, if any, to populate at each location.

• Impedance versus target for each scheme.

PI Advisor


Target Impedance


Target Impedance • Designing for power integrity often involves a target impedance

– Maximum allowable impedance magnitude over frequency which will result in acceptable voltage noise

• Several technical references contain something like

• An example can illustrate the complexities with this approach…

PDN Ipwr

ZPDN

Vnoise

+

_ Vnoise = Ipwr ZPDN

Ztarget = Vnoise(max)

Ipwr(ACpeak)

(Quantities are phasors)

f

|Z|

Mag. of Z

targetZ


A Simple Target Impedance Example • Suppose we have a power current with the periodic AC component shown

below (peak amplitude of 2A):

• Suppose we have a maximum allowable voltage amplitude of 1V • The simple approach suggests a max ZPDN of 0.5Ω over the frequency

components contained in the current will satisfy the noise requirement

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

ZPDN

0.5Ω

Freq But our impedance tolerance does not specify phase


Effects of Different Impedance Phases • Assume our PDN impedance just satisfies the requirement at each frequency:

|Z1|= |Z2|= |Z3|= 0.5Ω, but vary the impedance phase assumptions

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

Voltage (V)

θΖ1 = θΖ2 = θΖ3 = 0

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

Voltage (V)

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

Voltage (V)

θΖ1 =0 θΖ2 =90o θΖ3 = 0

θΖ1 =-90o θΖ2 =-90o θΖ3 = -90o

Simple approaches to calculating target impedance can provide a useful guide, but results should be verified with time-domain simulation


Target Impedance Notes

Reliance on a purely resistive target impedance may not bound the resulting time-domain voltage waveform to the desired amplitude.

Target impedance calculations should take into account the impedance phase as well as magnitude, but the current state-of-the-art does not.

More to come from ANSYS on this topic…


Power Integrity Case Study


1.5V power supply for FPGA on board.

Chip included as Apache CPM.

Package included as static S-parameters.

Board extracted with SIwave 7.

Simulation includes:

• GND

• VCC_1V5

System excited by CPM currents.

PDN Under Test


Time Domain Circuit

0

V5

DC=1.5V

AName=i_u1

VName=u1_vcc

Port1Port2

FGB Channel Power Only

VCCVSS

Die Current

0

On the left is the die current from the CPM. The FGB Channel Power Only block is a subcircuit containing the die, package, and board PDN models; Port1 is attached at the VRM before the power inductor and Port2 is attached at the die. On the right is a 1.5V voltage source representing the VRM.


0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

300.00

400.00

500.00

600.00

700.00

800.00

900.00

1000.00

Ipos

itive

(i_u1

) [m

A]

CPM CurrentDie Current

m2

m1

Curve InfoIpositive(i_u1)

NexximTransient

Name X Ym1 7.3200 444.1449m2 9.8700 422.7601

Name Delta(X) Delta(Y) Slope(Y) InvSlope(Y)d(m1,m2) 2.5500 -21.3847 -8.3862 -0.1192

Die Current

0

V5

DC=1.5V

AName=i_u1

VName=u1_vcc

Port1Port2


VCCVSS

Die Current

0

Die Current

This is the die current from the CPM. It runs for 10 ns. The final period of oscillation runs from 7.32 ns to 9.87 ns, which corresponds to a fundamental frequency of 392 MHz.


PDN Channel

0

V5

DC=1.5V

AName=i_u1

VName=u1_vcc

Port1Port2


VCCVSS

Die Current

0

0

Port1Port2 VCCVSS

Die PDNVCC_DIE VCC_BGA

FGB Package

VCC_BGA VCC_VRM

FGB Board

Board Package Die

From left to right: die, package, board. The die block is the passive chip PDN from the CPM, and the package and board in this case are included as static Nexxim state-space models extracted from SIwave.


PDN Impedance Components

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

10.00

100.00

1000.00

Y1

[ohm

]

FGB BoardPDN Impedance ComponentsCurve Info

BoardLinearFrequency

PackageImported

DieImported

Board Package CPM

The board provides the lowest impedance up to almost 200 MHz while the package is the most effective above 600 MHz. In this case the die provides some decoupling at a broad frequency range from 100 MHz up.


Full PDN Impedance

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

mag

(Z(P

ort2

,Por

t2))

[ohm

]

FGB Channel Power OnlyFull PDN ImpedanceCurve Info

mag(Z(Port2,Port2))LinearFrequencyFull PDN

The first resonant frequency of the board by itself is at 275 MHz, while in the full PDN this drops down to 129 MHz. In order to best use PI Advisor on the board we need to include the effects of the package and die.


Package Model Fit

0

Port1

883.15pF

C236

485.35pF

C237

23.855pH

L238

23.855pH

L239

0.0136ohm

R240

0.0139ohm

R241

883.15 pF

23.855 pH

13.6 mohm

485.35 pF

23.855 pH

13.9 mohm

The package looks like two mostly uncoupled RLC series resonators in parallel. The two resonant frequencies are 1096 MHz and 1479 MHz. This model was fit to the data and produces a reasonable match to the actual package impedance up to about 2 GHz as shown on the next slide.


Package Model Fit

0.00 0.01 0.10 1.00 10.00F [GHz]

0.01

0.10

1.00

10.00

100.00

1000.00

Y1

[ohm

]

Circuit3Package Model FitCurve Info

Package FitLinearFrequency

PackageImported

Package Fit Package


Die Model Fit

0.3

R54

3e-009farad

C55

0

Port1

3 nF

0.3 ohm

The die looks like a series RC combination. The fit here is not as good at high frequencies, but at the frequencies where the board will be optimized (< 1 GHz) it is reasonably well-matched.


Die Model Fit

0.00 0.01 0.10 1.00 10.00F [GHz]

0.10

1.00

10.00

100.00

Y1

[ohm

]

Circuit1Die Model FitCurve Info

Die FitLinearFrequency

DieImported

Die Fit Die


Board with Package/Die Fits

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

Y1

[ohm

]

FGB BoardBoard PDN ImpedanceCurve Info

Board w ith Package/Die FitsLinearFrequency

Full PDNImported

Board w/ Package/Die Fits Full PDN

Here is the full PDN impedance overlaid with the approximation created by the board impedance in parallel with the package and die fits.


1. As initially designed. – Eight 100 uF bulk capacitors at VRM output, two 10 uF capacitors, and two 1

uF capacitors.

2. With added high-frequency capacitors. – 12 0.01 uF capacitors placed on bottom layer below FPGA

3. With PI Advisor-optimized capacitor solution. – Target impedance: 0.3 ohms up to 1 GHz – Package RLC fit and die RC fit included at board FPGA footprint

Board Variations Analyzed


0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_vc

c) [V

]



Variation 1: As-Designed

U1 VCC Final period peak-to-peak: 62.3 mV

This is the power plane voltage for the as-designed board. The power noise is relatively well controlled even in this variation, and the peak-to-peak value over the final current draw period (starting at 7.32 ns) is 62.3 mV.


Variation 2: Added Capacitors

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

Y1

[ohm

]


mag(Z(Port2,Port2))LinearFrequency

mag(Z(Port2,Port2))_1Imported

Variation 2 As-built

The impedance at the clock frequency, 392 MHz, has increased from 53.6 mohm to 203 mohm so we expect worse performance despite the added capacitors.


0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_vc

c) [V

]



Variation 2: Added Capacitors


As expected the voltage noise is worse in this case, increasing after the start of the final clock period from 62.3 mV to 67.2 mV or 7.9 percent. Can we improve this with PI Advisor?


Variation 3: PI Advisor This is the best fit decoupling scheme found by PI Advisor. The impedance is predicted to be below 0.3 ohm up to 1 GHz using 8 of the 16 original high-frequency capacitor locations populated.


Variation 3: PI Advisor

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

Y1

[ohm

]


mag(Z(Port2,Port2))LinearFrequency

mag(Z(Port2,Port2))_1Imported

Variation 3 Variation 2

The reduced impedance at the clock frequency (80.6 mohm from 203 mohm) and the reduced peak impedance (338 mohm at 219 MHz from 725 mohm at 128 MHz) indicate the potential for better time-domain performance than the original variation.


0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_vc

c) [V

]



Variation 3: PI Advisor


As expected the noise voltage is better in this variation that either the original board or variation 2. The peak-to-peak voltage after the start of the final clock period is just 40.6 mV now; this is a reduction of 35 percent from the original value.


Power integrity simulation requires accurate package and chip PDN models to ensure correct designs.

The ANSYS chip-package-system technologies provide full coverage for PI simulation needs:

• CPM: chip PDN and current draw

• SIwave and PSI: package PDN

• SIwave: board PDN

• Designer: frequency- and time-domain simulation for full PDN

Conclusion

chip-aware power integrity - ansys · fgb channel power only vcc vss die current 0 on the left is...

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