cheat sheet 4

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Memory Capacity defined as MxN bit memory: M is length or # of separately addressable memory locations || N is width or # of bits at each location || HC12/S12:64Kx8 (or 64Kx16) memory space =>2^16=65,536 memory locations, each storing a byte or a double byte || individual bits not typically accessible. Information read/written a byte/word at a time. | Typical control pins associated with memory devices (all usually active low):WE: Write enable – when activated during write cycle, data line input written to specified memory address || OE: Output enable – when activated during read cycle, data at specified memory location placed on data out and data lines connected to memory system’s data bus using tristate outputs || CS: Chip select - used to select a specific chip in a memory array for read/write || Other control signals: system clock, signals to specify 8/16-bit access RAM: Random access memory-volatile(doesn’t keep data after power off) | maybe written to or read from | Has shorter access time compare to other technologies | in embedded microcontroller applications, used during program execution to temporarily store data or dynamically allocate variables | DRAM: 1-T design => density | Logic value stored as presence or absence of capacitive charge=> need to periodically refresh at a minimum rate to preserve logic value | world line for access, bit line for data I/O | requires more peripheral circuitry | SRAM: Typically 6-T cell design => lower density | WL = 0 (hold), 1 (read/write) | higher power consumption compared to DRAM | No refresh required | Faster to access compared to DRAM ROM: Read only memory-Nonvolatile | Read only – no capabilities for “online” writes: write typically requires UV light or high voltage | Longer access time compared to SRAM | In embedded microcontroller applications, used to store instructions and constants during program execution | Different variants: all nonvolatile, but differing in re-programmability and length of reprogram cycle || ROM: Programmed at factory using masks that create and omit connections || PROM: User-programmable once by blowing or keeping intact fusible links using a universal programmer hardware || EPROM: Out-of-circuit programmable multiple times by exposing to UV light and resetting contents so it may be reprogrammed – useful when developing a prototype || Byte – erasable EEPROM: In-circuit- programmable multiple times at byte-level: used as scratch pad memory, data storage, storing end-product characteristics || Flash EEPROM: In-circuit-programmable multiple times as block level; used to store code once it is fully developed and tested. Memory Map Tracks current allocation of memory components within available memory space. | Unused gaps available for expanded, external memory components. | Internal memory resources may be remapped by setting bits in three mapping registers. | Memory resource conflicts, if any, resolved by the following mapping precedence: 1. BDM ROM (if active), 2. Register Space, 3. Internal RAM, 4. Internal EEPROM, 5. External Memory Register Block Mapping: REG{15:11} specify upper five bits of register blocks starting address – 512B reg. block can be mapped to beginning of any 2KB block. | RAM Mapping: RAM{15}11 specify upper five bits of RAM starting address – 1KB internal static RAM can be mapped to beginning of any 2-KB block. | EEPROM Mapping: EE{15:12} specify upper four bits of EEPROM starting address – 4KB internal EEPROM can be mapped to beginning of any 4-KB block. Memory expansion allows use of external memory components within the 64k linearly addressable memory space | We consider the HC12 A4 in the Normal Expanded Wide Mode (BKGD/MODC, MODB, MODA pins =111) | ports A and B: for 16-bit address bus | ports C and D: for 16-bit data bus | During memory expansion, need to ensure the following: Unique addresses for each memory location | Data bus and control lines connected appropriately to all external memory chips | Timing and electrical compatibility between uC external memory chips. Expanding Memory Length: Tristate logic allows multiple chips to be connected to bus simultaneously. Only one chip output enabled at a time and hence electrically connected to bus. Expanding Memory Length and Width: Control Signal Connections. | Micro control signals: When operating in expanded mode, control signals provided from Port E of uC to external memory devices | ECLK: Basic bus clock with frequency half that of external timing crystal | Address valid when ECLK high | Data lines considered valid on falling edge of ECLK | R/W : Read when high, write when low | Connecting control lines from uC to external memory in normal expanded wide

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Page 1: Cheat Sheet 4

Memory Capacity defined as MxN bit memory: M is length or # of separately addressable memory locations || N is width or # of bits at each location || HC12/S12:64Kx8 (or 64Kx16) memory space =>2^16=65,536 memory locations, each storing a byte or a double byte || individual bits not typically accessible. Information read/written a byte/word at a time. | Typical control pins associated with memory devices (all usually active low):WE: Write enable – when activated during write cycle, data line input written to specified memory address || OE: Output enable – when activated during read cycle, data at specified memory location placed on data out and data lines connected to memory system’s data bus using tristate outputs || CS: Chip select - used to select a specific chip in a memory array for read/write || Other control signals: system clock, signals to specify 8/16-bit accessRAM: Random access memory-volatile(doesn’t keep data after power off) | maybe written to or read from | Has shorter access time compare to other technologies | in embedded microcontroller applications, used during program execution to temporarily store data or dynamically allocate variables | DRAM: 1-T design => density | Logic value stored as presence or absence of capacitive charge=> need to periodically refresh at a minimum rate to preserve logic value | world line for access, bit line for data I/O | requires more peripheral circuitry | SRAM: Typically 6-T cell design => lower density | WL = 0 (hold), 1 (read/write) | higher power consumption compared to DRAM | No refresh required | Faster to access compared to DRAMROM: Read only memory-Nonvolatile | Read only – no capabilities for “online” writes: write typically requires UV light or high voltage | Longer access time compared to SRAM | In embedded microcontroller applications, used to store instructions and constants during program execution | Different variants: all nonvolatile, but differing in re-programmability and length of reprogram cycle || ROM: Programmed at factory using masks that create and omit connections || PROM: User-programmable once by blowing or keeping intact fusible links using a universal programmer hardware || EPROM: Out-of-circuit programmable multiple times by exposing to UV light and resetting contents so it may be reprogrammed – useful when developing a prototype || Byte – erasable EEPROM: In-circuit-programmable multiple times at byte-level: used as scratch pad memory, data storage, storing end-product characteristics || Flash EEPROM: In-circuit-programmable multiple times as block level; used to store code once it is fully developed and tested.Memory Map Tracks current allocation of memory components within available memory space. | Unused gaps available for expanded, external memory components. | Internal memory resources may be remapped by setting bits in three mapping registers. | Memory resource conflicts, if any, resolved by the following mapping precedence: 1. BDM ROM (if active), 2. Register Space, 3. Internal RAM, 4. Internal EEPROM, 5. External Memory Register Block Mapping: REG{15:11} specify upper five bits of register blocks starting address – 512B reg. block can be mapped to beginning of any 2KB block. | RAM Mapping: RAM{15}11 specify upper five bits of RAM starting address – 1KB internal static RAM can be mapped to beginning of any 2-KB block. | EEPROM Mapping: EE{15:12} specify upper four bits of EEPROM starting address – 4KB internal EEPROM can be mapped to beginning of any 4-KB block. Memory expansion allows use of external memory components within the 64k linearly addressable memory space | We consider the HC12 A4 in the Normal Expanded Wide Mode (BKGD/MODC, MODB, MODA pins =111) | ports A and B: for 16-bit address bus | ports C and D: for 16-bit data bus | During memory expansion, need to ensure the following: Unique addresses for each memory location | Data bus and control lines connected appropriately to all external memory chips | Timing and electrical compatibility between uC external memory chips.Expanding Memory Length: Tristate logic allows multiple chips to be connected to bus simultaneously. Only one chip output enabled at a time and hence electrically connected to

bus. Expanding Memory Length and Width: Control Signal Connections. | Micro control signals: When operating in expanded mode, control signals provided from Port E of uC to

external memory devices | ECLK: Basic bus clock with frequency half that of external timing crystal | Address valid when ECLK high | Data lines considered valid on falling edge of ECLK | R/W: Read when high, write when low | Connecting control lines from uC to external memory in normal expanded wide mode: || Port A (ADDR{15:8}) and Port B (ADDR{7:0}) provide address lines || Port C (DATA{15:8}) and Port D (DATA{7:0}) provide data lines || Memory output should be enabled (OE = 0) when address is valid (ECLK = 1) and it is in read mode (R/W=1) => OE =! (ECLK*R/W) || Memory write should be enabled (WE=0) when address is valid (ECLK = 1) and it is in write mode (R/W =0) => WE=!(ECLK*!R/W) || Active-low chip select (CS) should be enabled for a memory device when address is valid (ECLK =1) and the particular address maps to the device (determined by appropriate address lines)

Homework (8): Length of addressable memory=2^(data lines=width)= length of memory, length/data lines=bits, length/2=bytes

Homework (9):

Page 2: Cheat Sheet 4

Overview and Transducer Interface Design: ATD Examples: temperature, pressure, humidity, precipitation, weight, displacement, light sensitivity, etc. | Converts a physical to voltage | Electrical signal may require conditioning to make it compatible with an embedded uC system || Conditioning: Scaling (amplification/attenuation), filtering of undesired frequency components, and/or addition of a DC bias | Transducer output assumed to be a linear function of input | V2min and V1min available from transducer specifications | V2max and V1max available from uC ATD converter specifications | two equations in two unknowns K and B – therefore, K and B can be determined for a specific transducer-uC interface || K and B realized using OP AMP circuitryATD Conversion: Sampling Rate/Frequency: Continuous-time analog signal sampled at regular time intervals to produce a discrete-time analog signal | Nquist criterion: Minimum sampling rate or frequency required for adequate reconstruction of original signal fs>=2fh | Time interval between samples Ts=1/fs | Anti-aliasing filter: use LPF with foutoff=fh before sampling to reduce distortion caused by frequency folding or aliasing || Phone company samples human voice at 8 KHz, uses 4 KHz LPF to prevent aliasingATD Conversion: Encoding: ATD converter converts each voltage sample to an unsigned binary value || sampled value held constant for ATD conversion using sample-and-hold circuit | A unique binary code is produced for every discrete voltage step between Vrh and Vrl || n=2^b| HC12 has an 8-bit ATD converter system => 2^8 = 256 different voltage levelsATD conversion: Quantization and Resolution: Quantization: Number of discrete levels the analog signal is divided into between Vrh and Vrl || More levels provide better representation of sampled signal || Example: Vrh = 5VDC and Vrl =0VDC, quantization: 256 levels; voltage per step = (5V-0V)/(256 steps) = 19.53mV/step | Resolution: voltage per step | Resolution = (Vrh-Vrl)/(number of steps) = (Vrh-Vrl)/2^b | Dynamic range = 20log 2^b = 6.02 b (in decibels, dB) Data rate: d=fsb || x={(Vx-Vrl)/[(Vrh-Vrl)/2^b]} Vrl -> 00…00 Vrh ->11…11 x: encoded value, Vx: sampled voltageSuccessive-Approximation ATD converter: Controller first produces bit pattern 10,000,000=128 | DAC produces corresponding voltage: (128/256) x 5V = 2.5V | Comparator produces 1 if unknown voltage is >=DAC output, else produces 0 | If comparator produced 1, then next bit pattern produced by controller is 11,000,000 (192/256x5V = 3.75V), else next bit pattern is 01,000,000 (64/256 x 5V = 1.25V) | Process continues until all 8 bits determinedHC12 ATD Conversion System: Timing provided by P clock | Vrh and Vrl line inputs are used as reference voltage levels | HC12 ATD system contains 8 channels with analog inputs provided on pins AN0/PAD0-AN7/PAD7 | Analog inputs fed to analog MUX which selects signals to be input to ATD converter as specified by ATD control registers | ATD conversion sequence initiated by writing to one of the ATD control registers | At the completion of ATD conversion: || Results placed in corresponding ATD Converter Result Register (ADR0H through ADR 7H) || Corresponding flags set in ATD status Register (ATDSTAT)HC12 ATD Control Registers: HC12 ATD system operation configured for a specific application by setting a 16-word (32-byte) memory-mapped control register bank and by selection of Vrh and Vrl reference volrages | There are 6 ATD control registers used to tailor an ATD conversion sequence to user specifications: ATDCTL0 through ATDCTL5; ATDCTL2, 4, and 5 are the most important onesATDCTL2 || ADPU (ATD Powerup): ||| 1 -> ATD system powered up; must wait for 100us for ATD system to become stable, 0-> ATD system off || AFFC (ATD Fast Flag Clear All): 0 -> ATD system flags cleared in a normal manner, 1 -> ATD conversion complete flags are set for a fast, clear sequence || ASCIE (ATD Sequence complete interrupt Enable): 1 -> Interrupt requrest generated by ATD sequence complete interrupt flag (ASCIF) are enabled, 0 -> ASCIF – based interrupts disabled || ASCIF ( ATD Sequence Complete Interrupt Flag): Set to 1 when an ATD conversion sequence is finished; if ASCIE bit set, setting of ASCIF also generates an interrupt || Example: To power up ATD system and set it for normal flag-clearing operations: ||| ATDCTL2 = 1000 0000 = $80ATDCTL4: Controls sample timing for the ATD system || ATD clock frequency = [(P clock frequency)/(PRS[4:0]+1)]x1/2 || Total conversion time for an 8-bit conversion consists of four components ||| three componenets take a fixed time of 16 ATD clock periods ||| Remaining component (final sample time) is variable and set by user via bits SMP1 and SMP0 (Select Sample Time bits)ATDCTL5: S8CM (Select 8 channel mode); 0 -> selects a sequence of 4 conversions 1 -> selects a 8 conversions || SCAN (Enable Continuous Channel Scan): 0 -> Single conversion sequence is performed then ATD system stops 1 -> Continuous conversion sequence performed || MULT (Enable Multichannel Conversion) 0 -> ATD system performs conversion on a single input channel 1-> ATD system performs conversions on sequential channels as specified by CD, CC, CB, and CA bits || CD, CC, CB, CA: Used to specify channels for conversion to ATD system || When S8CM and CD both set to 1 reference signals Vrh and Vrl may be converted and analyzed || Example: To set ATDCTL5 for continuous sequence of conversion with 8 conversions per sequence: ||| S8CM, SCAN, MULT=1; CD=0; CC, CB, CA = don't care ATDCTL5 = 0111 0000 = $70HC12 ATD Status Register: ATD Status register: Two-byte register contain flags that indicate status of ATD system | SCF (Sequence Complete Flag): ||Setting: When SCAN = 0: Set at the end of the conversion sequence, when 1: set at the end of the 1st conversion sequence ||Clearing: When AFFC = 0: cleared when write performed to ATDCTL5 to initiate a new conversion sequence, when 1: cleared after the first result register is read | CC[2:0] (3-bit conversion counter): Indicates which channel is currently undergoing conversion and hence which result register is written to next in a 4 or 8 channel conversion sequence | CCF [7:0] (Conversion Complete Flags): | Set on completion of conversion associated with a given channel || Clearing AFFC = 0: when status register is read, CCF bits cleared, when 1 associated result register read, corresponding CCF bit cleared || CCF flags may be continuously polled to determine if a specific channel conversion is completeHC12 ATD Input Register: Input signals provided to ATD system via port AD data input register (PORTAD) | PORTAD may also be used as a general-purpose digital input port | When PORTAD read, signal levels connected to PORTAD pins sensedHC12ATD Result Registers: After specified conversion is complete, ATD results placed into corresponding ATD result register: ADR0H through ADR7H | Results in an 8-bit unsigned binary value in the range 0 – 255 || To interpret result as a voltage ||| Unknown volrage = [{unsigned binary value in ADRxH)/256]x(Vrh-Vrl) ||| Example: An 8-bit analog converter with Vrh = 5V and Vrl= 0V converts an unknown volrage to an unsigned binary representation of 1000 1010. What is the unknown volrage –> 1000 1010 = 138 -> 138/256x5V=2.695VTo successfully configure and program the ATD for proper operation, follow these simple steps: 1. Connect the appropriate reference volrage sources to HC12 external pins Vrh and Vrl. The reference volrage for pin Vrh cannot exceed 5 volts and the reference volrage for pin Vrl cannot be less than 0V. 2. Connect the analog signals(s) for conversion to the appropriate A/D input pin(s):PAD0 through PAD7. 3. Write 1 to the ADPU bit in the ATDCTL2 register located at memory address $0062. Then you must wait 100us before using the ATD system. 4. Configure the ATD for proper operation using the ATD control registers. 5. Initialize the ATD conversion process by writing to (ATDCTL5). 6. Monitor for ATD conversion completion with status registers. 7. Use results of the conversion located in the corresponding result register (ADR0H-ADR7H). 8. ATD can be powered down after conversion using the ADPU bit in ATDCTL2

Page 3: Cheat Sheet 4

An alternative to polling is to use ATD sequence complete interrupt -> when ASCIE bit in ATDCTL2 set, ASCIF in ATDCTL2 causes an interrupt when set after a conversion sequence is complete.