charles kime & thomas kaminski © 2008 pearson education, inc. ( edited by dr. muhamed mudawar...

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Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic and Computer Design Fundamentals

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Page 1: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Charles Kime & Thomas Kaminski

© 2008 Pearson Education, Inc.

( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM )

Circuit Optimization

Logic and Computer Design Fundamentals

Page 2: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 2

Circuit Optimization Goal: To obtain the simplest

implementation for a given function Optimization is a more formal approach

to simplification that is performed using a specific procedure or algorithm

Optimization requires a cost criterion to measure the simplicity of a circuit

Distinct cost criteria we will use:• Literal cost (L)• Gate input cost (G)• Gate input cost including inverters (GN)

Page 3: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 3

Literal – a variable or it complement

Literal cost – the number of literal appearances in a Boolean expression corresponding to the logic circuit diagram

Example: Boolean expressions for F• F = B D + A B C + A C D

• F = B D + A B C + A B D + A B C

• F = (A+B)(A+D)(B+C+D)(B+C+D)

• Which solution is best?

Literal Cost

L = 8

L = 11

L = 10

First solution is best

Page 4: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 4

Gate Input Cost Gate Input Cost: Count of total number of inputs to the

gates in the logic circuit implementation

Two gate input costs are defined:

G = Count of gate inputs without counting Inverters

GN = Count of gate inputs + count of Inverters

For SOP and POS equations, the gate input cost can be found from the Boolean expression by finding the sum of:• All literal appearances

• Number of terms excluding single literal terms (added to G)

• Number of distinct complemented single literals (added to GN)

Example:

• F = B D + A B C + A C DL = 8 G = L+3 = 11GN = G+3 = 14

Page 5: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 5

Example 1:

F = A + B C +

Cost Criteria (continued)

A

BC

F

B CL = 5

L (literal count) counts the AND inputs and the single literal OR input.

G = L + 2 = 7

G (gate input count) adds the remaining OR gate inputs

GN = G + 2 = 9

GN(gate input count with NOTs) adds the inverter inputs

Page 6: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 6

Example 2:

F = A B C + L = 6 G = 8 GN = 11 F = (A + )( + C)( + B) L = 6 G = 9 GN = 12 Same function and same

literal cost But first circuit has better

gate input count and bettergate input count with NOTs

Select first circuit!

Cost Criteria (continued)

B C

A

ABC

F

C B

F

ABC

A

Page 7: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 7

Cost Criteria Summary Literal Count:

• Simple to evaluate by counting all literals • However, does not represent circuit complexity

accurately in all cases

Gate Input Cost (or Count):• Good measure of logic implementation• Proportional to the number of transistors and

wires used in the implementation• Important when measuring cost of circuits with

more than two levels

Page 8: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 8

Boolean Function Optimization

Minimizing the gate input (or literal) cost of a Boolean equation reduces the circuit cost

We choose gate input cost Boolean Algebra and graphical techniques are

tools to minimize cost criteria values Some important questions:

• When do we stop trying to reduce the cost?

• Do we know when we have a minimum cost?

Treat optimum or near-optimum cost functionsfor two-level (SOP and POS) circuits first

Introduce a graphical technique using Karnaugh maps (K-maps for short)

Page 9: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 9

Karnaugh Map (K-map) A K-map is a collection of squares

• Each square represents a minterm

• The collection of squares is a graphical representation of a Boolean function

• Adjacent squares differ in the value of one variable

• Alternative algebraic expressions for the same function are derived by recognizing patterns of squares

The K-map can be viewed as

• A reorganized version of the truth table

Page 10: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 10

Some Uses of K-Maps

Provide a means for:• Finding optimum or near optimum

SOP and POS standard forms

Two-level AND/OR and OR/AND circuits

for functions with small numbers of variables

• Visualizing concepts related to manipulating Boolean expressions, and

• Demonstrating concepts used by computer-aided design programs to simplify large circuits

Page 11: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 11

Two-Variable K-Map A 2-variable Karnaugh Map:

• Minterm m0 and minterm m1 are “adjacent”

they differ in the value of variable y

• Similarly, minterm m0 and minterm m2 are adjacent and differ in x

• Also, m1 and m3 differ in the x variable

• Finally, m2 and m3 differ in the y variable

m3 = x ym2 = x yx = 1

m1 = x ym0 = x yx = 0

y = 1y = 0x y

Page 12: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 12

K-Map and Truth Tables The K-Map is a different form of the truth table

Truth Table

Input Values (x,y)

Function Value F(x,y)

0 0 1 0 1 0 1 0 1 1 1 1

K-Map

11x = 1

01x = 0

y = 1y = 0x y

Page 13: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 13

K-Map Function Minimization

F(x,y) = m0 + m2 + m3

F = x y + x y + x y

Two adjacent cells containing 1’s can be combined using the Minimization Theorem

K-Map

11x = 1

01x = 0

y = 1y = 0x y

m0 + m2 = x y + x y = (x + x) y = y

Therefore, F can be simplified as F = x + y

m2 + m3 = x y + x y = x (y + y) = x

Page 14: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 14

Three Variable K-Map

Where each minterm corresponds to the product terms:

Note that if the binary value for an index differs in one bit position, the minterms are adjacent on the K-Map

yz=00 yz=01 yz=11 yz=10

x=0 m0 m1 m3 m2

x=1 m4 m5 m7 m6

yz=00 yz=01 yz=11 yz=10

x=0

x=1

zyx zyx zyx zyx

zyx zyx zyx zyx

xyz

xyz

Page 15: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 15

Alternative K-Map Labeling

K-Map largely involves:• Entering values into the map, and

• Reading off product terms from the map

Alternate labelings are useful:

y

z

x

10 2

4

3

5 67

x

y

zz

yy z

z

10 2

4

3

5 67

x

0

1

00 01 11 10

x

Page 16: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 16

Example Functions By convention, we represent the minterms of F by a ‘1’

in the map and leave the entries that contain ‘0’ blank Example 1:

Example 2:

Learn the locations of the 8 indices based on the variable order shown

y

x

10 2

4

3

5 67

1

11

1

z

x

y10 2

4

3

5 671 11

1

z

F(x, y, z) = ∑(2, 3, 4, 5)

G(x, y, z) = ∑(3, 4, 6, 7)

Page 17: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 17

Combining Squares By combining squares, we reduce number of literals in

a product term, thereby reducing the gate input cost

On a 3-variable K-Map:

• One square represents a minterm with 3 variables

• Two adjacent squares represent a term with 2 variables

• Four adjacent squares represent a term with 1 variable

• Eight adjacent square is the function 1 (no variables)

Page 18: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 18

Example: Combining Squares Example:

Applying the Minimization Theorem 3 times:

Thus the four terms that form a 2 × 2 square correspond to the term ‘y’.

yzyyz

zyxzyxzyxzyx)z,y,x(F

x

y10 2

4

3

5 671 1

11

z

F = ∑(2, 3, 6, 7)

Page 19: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 19

Combining Four Squares Example Shapes of 4-square Rectangles:

y0 1 3 2

5 64 7

z

x

x y z

Page 20: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 20

Combining Two Squares Example Shapes of 2-square Rectangles:

y0 1 3 2

5 64 7x

z

x y x z

y z

Page 21: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 21

Simplifying 3-Variable Functions

K-Maps can be used to simplify Boolean functions Example: find an optimum SOP equation for

F(x, y, z) = ∑ (0, 1, 2, 4, 6, 7)

x y zy0 1 3 2

5 64 7xz

1 1 1

1 1 1

x yF = z + x y + x y

Page 22: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 22

Four-Variable K-Map

00 01 11 10

00 m0 = w x y z m1 = w x y z m3 = w x y z m2 = w x y z

01 m4 = w x y z m5 = w x y z m7 = w x y z m6 = w x y z

11 m12 = w x y z m13 = w x y z m15 = w x y z m14 = w x y z

10 m8 = w x y z m9 = w x y z m11 = w x y z m10 = w x y z

yzwx

YY

Z

W

X

W

ZZ

X

X

Page 23: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 23

4-Variable K-map Terms

4-variable K-maps can have rectangles corresponding to:

• Single square = 4-variable minterm

• 2 combined squares = 3-variable term

• 4 combined squares = 2-variable term

• 8 combined squares = 1 variable term

• 16 (all) combined squares = constant ‘1’

Page 24: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 24

Combining Eight Squares Examples of 8-square Rectangles:

X

Y

Z

8 9 1011

12 13 1415

0 1 3 2

5 64 7

W

W

Z

Page 25: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 25

Combining Four Squares Examples of 4-square Rectangles:

8 9 1011

12 13 1415

0 1 3 2

5 64 7

X

Y

Z

W

W YX ZX Z

Page 26: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 26

Combining Two Squares Examples of 2-square Rectangles:

8 9 1011

12 13 1415

0 1 3 2

5 64 7

X

Y

Z

W

W Y ZW X Z

X Y Z

W X Z

Page 27: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 27

Simplifying 4-Variable Functions

F(W, X, Y, Z) = ∑ (0, 2, 4, 5, 6, 7, 8, 12)

8 9 1011

12 13 1415

0 1 3 2

5 64 7

X

Y

Z

W

1 1

1 1

1

1

1 1

Y Z W Z

F = W X + Y Z + W Z

W X

Page 28: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 28

Product-of-Sum (POS) Simplification F (W, X, Y, Z) = ∑ (1, 2, 3, 9, 10, 11, 13, 14, 15) F = F (W, X, Y, Z) = ∑ (0, 4, 5, 6, 7, 8, 12) =

F = Y Z + W X = (Y + Z) (W + X)

1

1

1

1 1

11

1 1

8 9 1011

12 13 1415

0 1 3 2

5 64 7

X

Y

Z

W 8 9 1011

12 13 1415

0 1 3 2

5 64 7

X

Y

Z

W

1

1

1

11 1 1

F

W Z + W Y + X Z + X Y

+ W XY Z

(G = 8+4 = 12)

(G = 4+2 = 6)

Page 29: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 29

Product-of-Sum Simplification Step 1: Draw the K-map for F, replacing the 0’s of

F with 1’s in F and vice versa

Step 2: Obtain a minimal Sum-of-Product (SOP) expression for F

Step 3: Use DeMorgan’s Theorem to obtain F = F

The result is a minimal Product-of-Sum (POS) expression for F

Step 4: Compare the cost of the minimal SOP and POS expressions to find which one is better

Page 30: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 30

Five-Variable K-Maps For five variable problems, we use two adjacent 4-variable

K-maps that can be visualized to be on top of each other Each square in the A=0 map is adjacent to the

corresponding square in the A=1 map (e.g. m4 and m20)

C

D

E

B

A = 0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

C

E

B

A = 1D

16 17 19 18

20 21 23 22

28 29 31 30

24 25 27 26

Page 31: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 31

Example of a Five-Variable K-map F(A, B, C, D, E) = ∑(0, 1, 8, 9, 16, 17, 22, 23, 24, 25)

F =

1 1

1 1

1 1

1 1

1 1C

D

E

B

A = 0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

C

E

B

A = 1D

16 17 19 18

20 21 23 22

28 29 31 30

24 25 27 26

C D + A B C D

Page 32: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 32

Sometimes a function table or K-map contains entries for which it is known:

• The input values for the minterm will never occur, or

• The output value for the minterm is not used

In these cases, the output value need not be defined

Instead, the output value is defined as a “don't care”

By placing “don't cares” ( an “x” entry) in the function table or map, the cost of the logic circuit may be lowered.

Example: A logic function having the binary codes for the BCD digits as its inputs. Only the codes for 0 through 9 are used. The six codes, 1010 through 1111 never occur, so the output values for these codes are “x = don’t cares.”

Don't Cares in K-Maps

Page 33: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 33

Example: BCD “5 or More” The map below gives a function F(w,x,y,z) which is

defined as "5 or more" over BCD inputs. With the don't cares used for the 6 non-BCD combinations:

If the don’t cares were treated as 0’s we get:

F1 = w x z + w x y + w x y (G = 12) If the don’t cares were 1’s we get:

F2 = w + x z + x y (G = 7 better)

z

w

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

1

11

1

X X X

X X

X

0 0 0 0

0x

y

The selection of don’t cares depends on which combination gives the simplest expression

Page 34: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 34

Product-of-Sums Example Find the optimum POS expression for :

F(A, B, C, D) = ∑ (3,9,11,12,13,14,15) + ∑d (1,4,6)

Where ∑d indicates the don’t care minterms

Solution: Find F =

F = B D + A B

Optimum POS expression:

F = (B + D) (A + B)

Gate input cost (G = 6)

∑ (0, 2, 5, 7, 8, 10) + ∑d (1,4,6)

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

X1

1

1

1 X 1

XB

CF

Page 35: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 35

Systematic Simplification

A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle, with the number of squares equal to a power of 2

A prime implicant is called an Essential Prime Implicant if it is the only prime implicant that covers one or more minterms

Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map

A set of prime implicants covers all minterms if, for each minterm of the function, at least one prime implicant in the set of prime implicants includes the minterm

Page 36: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 36

DB

CB

1 1

1 1

1 1

B

D

A

1 1

1 1

1

Example of Prime Implicants Find ALL Prime Implicants

C

BD

CD

BD

Only 2 Essential Prime Implicants

DB

1 1

1 1

1 1

B

C

D

A

1 1

1 1

1

AD

BA

Page 37: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 37

Prime Implicant Practice Find all prime implicants for

F(A, B, C, D) = ∑ (0,2,3,8,9,10,11,12,13,14,15)

1 1

1 1

1

1 1

1

1 11

B C

A8 9 1011

12 13 1415

0 1 3 2

5 64 7

B

C

D

A

B D

3 prime implicants:

A, B C, B D

All 3 prime implicants are essential

Page 38: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 38

Optimization Algorithm Find all prime implicants

Include all essential prime implicants in the solution

Select a minimum cost set of non-essential prime implicants to cover all minterms not yet covered

Prime implicant selection rule:

• Minimize the overlap among prime implicants

• In particular, in the final solution, make sure that each prime implicant selected includes at least one minterm not included in any other prime implicant selected

Page 39: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 39

Selection Rule Example Simplify F(A, B, C, D) given on the K-map

1

1

1

1 1

1

1

B

D

A

C

1

1

1

1

1

1 1

1

1

B

D

A

C

1

1

Essential

Minterms covered by essential prime implicants

Selected

Page 40: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 40

Selection Rule Example with Don't Cares

Simplify F(A, B, C, D) given on the K-map. Selected

Minterms covered by essential prime implicants

1

1

x

x

x x

x

1

B

D

A

C

1

1 1

1

x

x

x x

x

1

B

D

A

C

1

1

Essential

Page 41: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 41

Multiple-Level Optimization Multiple-level circuits - circuits that are more

than two levels (inverters are not counted)

Multiple-level circuits can have reduced gate input cost compared to two-level (SOP and POS) circuits

Multiple-level optimization is performed by applying transformations to circuits represented by equations while evaluating cost

Page 42: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 42

Transformations Factoring: finding a factored form from SOP or

POS expression

Decomposition: expressing a function as a set of new functions

Substitution of H into F: Expressing F as a function of H and some of its original variables

Elimination: Inverse of substitution, called also flattening

Extraction: decomposition applied to multiple functions simultaneously

Page 43: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 43

Factoring Example Algebraic Factoring F = A C D + A B C + A B C + A C D (G = 16)

Factoring: F = A (C D + B C) + A (B C + C D) (G = 16)

Factoring again: F = A C (B + D) + A C (B + D) (G = 12)

Factoring again: F = (A C + A C) (B + D) (G = 10)

This factoring example has reduced G from 16 to 10Resulting circuit has three levels plus input inverters

Page 44: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 44

Decomposition Example Given the following function:

F = (A (B + C) + D) (B + C) (G = 10)

Define 2 new functions X and Y as follows:

X = (B + C) and Y = (A X + D)

Then function F can be decomposed as follows:

F = X Y, where

X = (B + C) and

Y = (A X + D) (G = 8)

Page 45: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 45

Substitution Example Given the following function:

H = A(C + D)(E + F) + B C D E F (G = 14) Define X and Y as new functions :

X = C D and Y = E + F The complement of X and Y are:

X = (C + D) and Y = E F Substitute C D with X and (C + D) with X

Substitute (E + F) with Y and E F with Y

H = A X Y + B X Y

where, X = C D and Y = E + F (G = 12)

Page 46: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 46

Elimination Example Given a set of functions:

X = B+C, Y = A+B, and Z = A X + C Y (G = 10) Eliminate X and Y from Z:

Z = A (B + C) + C (A + B) (G = 10) Flatten Z (Convert to SOP expression):

Z = A B + A C + A C + B C (G = 12) Two-Level Optimization (using K-map):

Z = A B + C (G = 4)

This example shows that elimination begins with any set of functions. It can increase gate input cost (G) temporarily, but can result in a final solution with optimum cost (G)

Page 47: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 47

Extraction Example Given the following two functions:

E = A B D + A B D

H = B C D + B C D (G = 16)

Find a common factor for E and H Define the common factor as a function:

F = B D + B D Perform extraction by expressing E and H as a

function of F:

F = B D + B D, E = A F, H = C F (G = 10) Reduced cost because of the sharing of F

Page 48: Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. ( Edited by Dr. Muhamed Mudawar for COE 202 and EE 200 at KFUPM ) Circuit Optimization Logic

Circuit Optimization 48

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